--- /dev/null
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/starfive,jh7110-pinfunc.h>
+
+&gpio {
+ gmac0_pins: gmac0-pins {
+ gmac0-pins-reset {
+ sf,pins = <PAD_GPIO63>;
+ sf,pinmux = <PAD_GPIO63_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_HIGH>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ i2c0_pins: i2c0-pins {
+ i2c0-pins-scl {
+ sf,pins = <PAD_GPIO52>;
+ sf,pinmux = <PAD_GPIO52_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_LOW>;
+ sf,pin-gpio-doen = <OEN_I2C0_IC_CLK_OE>;
+ sf,pin-gpio-din = <GPI_I2C0_IC_CLK_IN_A>;
+ };
+
+ i2c0-pins-sda {
+ sf,pins = <PAD_GPIO51>;
+ sf,pinmux = <PAD_GPIO51_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_LOW>;
+ sf,pin-gpio-doen = <OEN_I2C0_IC_DATA_OE>;
+ sf,pin-gpio-din = <GPI_I2C0_IC_DATA_IN_A>;
+ };
+ };
+
+ i2c6_pins: i2c6-pins {
+ i2c6-pins-scl {
+ sf,pins = <PAD_GPIO20>;
+ sf,pinmux = <PAD_GPIO20_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_LOW>;
+ sf,pin-gpio-doen = <OEN_I2C6_IC_CLK_OE>;
+ sf,pin-gpio-din = <GPI_I2C6_IC_CLK_IN_A>;
+ };
+
+ i2c6-pins-sda {
+ sf,pins = <PAD_GPIO19>;
+ sf,pinmux = <PAD_GPIO19_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_LOW>;
+ sf,pin-gpio-doen = <OEN_I2C6_IC_DATA_OE>;
+ sf,pin-gpio-din = <GPI_I2C6_IC_DATA_IN_A>;
+ };
+ };
+
+ mmc0_pins: mmc0-pins {
+ mmc0-pins-rest {
+ sf,pins = <PAD_GPIO62>;
+ sf,pinmux = <PAD_GPIO62_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO0_RST_N>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ mmc1_pins: mmc1-pins {
+ mmc1-pins0 {
+ sf,pins = <PAD_GPIO10>;
+ sf,pinmux = <PAD_GPIO10_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CCLK_OUT>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ mmc1-pins1 {
+ sf,pins = <PAD_GPIO9>;
+ sf,pinmux = <PAD_GPIO9_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CCMD_OUT>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CCMD_OUT_EN>;
+ sf,pin-gpio-din = <GPI_SDIO1_CCMD_IN>;
+ };
+
+ mmc1-pins2 {
+ sf,pins = <PAD_GPIO11>;
+ sf,pinmux = <PAD_GPIO11_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_0>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_0>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_0>;
+ };
+
+ mmc1-pins3 {
+ sf,pins = <PAD_GPIO12>;
+ sf,pinmux = <PAD_GPIO12_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_1>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_1>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_1>;
+ };
+
+ mmc1-pins4 {
+ sf,pins = <PAD_GPIO7>;
+ sf,pinmux = <PAD_GPIO7_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_2>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_2>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_2>;
+ };
+
+ mmc1-pins5 {
+ sf,pins = <PAD_GPIO8>;
+ sf,pinmux = <PAD_GPIO8_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_SDIO1_CDATA_OUT_3>;
+ sf,pin-gpio-doen = <OEN_SDIO1_CDATA_OUT_EN_3>;
+ sf,pin-gpio-din = <GPI_SDIO1_CDATA_IN_3>;
+ };
+ };
+
+ pwmdac0_pins: pwmdac0-pins {
+ pwmdac0-pins-left {
+ sf,pins = <PAD_GPIO19>;
+ sf,pinmux = <PAD_GPIO19_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_PWMDAC0_LEFT_OUTPUT>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ pwmdac0-pins-right {
+ sf,pins = <PAD_GPIO42>;
+ sf,pinmux = <PAD_GPIO42_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1)|(GPIO_PU(1)))>;
+ sf,pin-gpio-dout = <GPO_PWMDAC0_RIGHT_OUTPUT>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ i2s_clk_pins: i2s-clk0 {
+ i2s-clk0_mclk {
+ sf,pins = <PAD_GPIO32>;
+ sf,pinmux = <PAD_GPIO32_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_CRG0_MCLK_OUT>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ i2s-clk0_bclk {
+ sf,pins = <PAD_GPIO37>;
+ sf,pinmux = <PAD_GPIO37_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_I2SRX0_BCLK_MST>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ i2s-clk0_lrclk {
+ sf,pins = <PAD_GPIO25>;
+ sf,pinmux = <PAD_GPIO25_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_I2SRX0_LRCK_MST>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ i2stx_pins: i2stx-pins {
+ i2stx-pins0 {
+ sf,pins = <PAD_GPIO18>;
+ sf,pinmux = <PAD_GPIO18_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_I2STX_4CH1_SDO0>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ i2srx_pins: i2srx-pins {
+ i2srx-pins0 {
+ sf,pins = <PAD_GPIO17>;
+ sf,pinmux = <PAD_GPIO17_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-doen = <OEN_HIGH>;
+ sf,pin-gpio-din = <GPI_I2SRX0_EXT_SDIN0>;
+ };
+ };
+
+
+ can0_pins: can0-pins {
+ can0-pins0 {
+ sf,pins = <PAD_GPIO28>;
+ sf,pinmux = <PAD_GPIO28_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_CAN0_CTRL_TXD>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ can0-pins1 {
+ sf,pins = <PAD_GPIO27>;
+ sf,pinmux = <PAD_GPIO27_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-doen = <OEN_HIGH>;
+ sf,pin-gpio-din = <GPI_CAN0_CTRL_RXD>;
+ };
+
+ can0-pins2 {
+ sf,pins = <PAD_GPIO45>;
+ sf,pinmux = <PAD_GPIO45_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_CAN0_CTRL_STBY>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ can1_pins: can1-pins {
+ can1-pins0 {
+ sf,pins = <PAD_GPIO28>;
+ sf,pinmux = <PAD_GPIO28_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_CAN1_CTRL_TXD>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ can1-pins1 {
+ sf,pins = <PAD_GPIO27>;
+ sf,pinmux = <PAD_GPIO27_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-doen = <OEN_HIGH>;
+ sf,pin-gpio-din = <GPI_CAN1_CTRL_RXD>;
+ };
+
+ can1-pins2 {
+ sf,pins = <PAD_GPIO45>;
+ sf,pinmux = <PAD_GPIO45_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_CAN1_CTRL_STBY>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ pwm_ch0_pins: pwm_ch0-pins {
+ pwm_ch0-pins0 {
+ sf,pins = <PAD_GPIO51>;
+ sf,pinmux = <PAD_GPIO51_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_PTC0_PWM_0>;
+ sf,pin-gpio-doen = <OEN_PTC0_PWM_0_OE_N>;
+ };
+ };
+
+ ssp0_pins: ssp0-pins {
+ ssp0-pins_tx {
+ sf,pins = <PAD_GPIO57>;
+ sf,pinmux = <PAD_GPIO57_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_SPI0_SSPTXD>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ ssp0-pins_rx {
+ sf,pins = <PAD_GPIO58>;
+ sf,pinmux = <PAD_GPIO58_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-doen = <OEN_HIGH>;
+ sf,pin-gpio-din = <GPI_SPI0_SSPRXD>;
+ };
+
+ ssp0-pins_clk {
+ sf,pins = <PAD_GPIO61>;
+ sf,pinmux = <PAD_GPIO61_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_SPI0_SSPCLKOUT>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ ssp0-pins_cs {
+ sf,pins = <PAD_GPIO14>;
+ sf,pinmux = <PAD_GPIO14_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_SPI0_SSPFSSOUT>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+
+ sc2235_pins: sc2235-pins {
+ sc2235-1V8-pins {
+ sf,pins = <PAD_GPIO11>;
+ sf,pinmux = <PAD_GPIO11_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_HIGH>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ sc2235-1V5-pins {
+ sf,pins = <PAD_GPIO12>;
+ sf,pinmux = <PAD_GPIO12_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_HIGH>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ sc2235-2V8-pins {
+ sf,pins = <PAD_GPIO10>;
+ sf,pinmux = <PAD_GPIO10_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_HIGH>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ sc2235-reset-pins {
+ sf,pins = <PAD_GPIO16>;
+ sf,pinmux = <PAD_GPIO16_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_HIGH>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ sc2235-pwdn-pins {
+ sf,pins = <PAD_GPIO15>;
+ sf,pinmux = <PAD_GPIO15_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_HIGH>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ sc2235-esync-pins {
+ sf,pins = <PAD_GPIO17>;
+ sf,pinmux = <PAD_GPIO17_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_LOW>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+
+ sc2235-oen-pins {
+ sf,pins = <PAD_GPIO18>;
+ sf,pinmux = <PAD_GPIO18_FUNC_SEL 0>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <GPO_LOW>;
+ sf,pin-gpio-doen = <OEN_LOW>;
+ };
+ };
+};
+
+&gpioa {
+
+ pwm_ch4_pins: pwm_ch4-pins {
+ pwm_ch4-pins0 {
+ sf,pins = <PAD_RGPIO2>;
+ sf,pin-ioconfig = <IO(GPIO_IE(1))>;
+ sf,pin-gpio-dout = <U0_PWM_8CH_PTC_PWM_4>;
+ sf,pin-gpio-doen = <U0_PWM_8CH_PTC_OE_N_4>;
+ };
+ };
+
+};
+
+&gmac0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_pins>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+};
+
+&i2stx_4ch1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s_clk_pins &i2stx_pins>;
+ status = "okay";
+};
+
+&i2srx_3ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2srx_pins>;
+ status = "okay";
+};
+
+&ipmscan0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0_pins>;
+ status = "okay";
+};
+
+&pwmdac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwmdac0_pins>;
+ status = "okay";
+};
+
source "drivers/pinctrl/meson/Kconfig"
source "drivers/pinctrl/cirrus/Kconfig"
source "drivers/pinctrl/visconti/Kconfig"
+source "drivers/pinctrl/starfive/Kconfig"
config PINCTRL_XWAY
bool
obj-y += mediatek/
obj-y += cirrus/
obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/
+obj-$(CONFIG_PINCTRL_STARFIVE) += starfive/
\ No newline at end of file
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only
+
+config PINCTRL_STARFIVE
+ bool "Pinctrl driver for the StarFive SoC"
+ depends on OF
+ depends on RISCV || COMPILE_TEST
+ select GENERIC_PINCTRL_GROUPS
+ select GENERIC_PINMUX_FUNCTIONS
+ select GENERIC_PINCONF
+ select GPIOLIB
+ select GPIOLIB_IRQCHIP
+ select OF_GPIO
+ help
+ Say yes here to support pin control on the StarFive RISC-V SoC.
+ This also provides an interface to the GPIO pins not used by other
+ peripherals supporting inputs, outputs, configuring pull-up/pull-down
+ and interrupts on input changes.
+
+config PINCTRL_STARFIVE_JH7110
+ bool "Pinctrl and GPIO driver for the StarFive jh7100 SoC"
+ depends on PINCTRL_STARFIVE
+ help
+ This selects the pinctrl driver for jh7100 starfive.
\ No newline at end of file
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_PINCTRL_STARFIVE) += pinctrl-starfive.o
+
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_STARFIVE_JH7110) += pinctrl-starfive-jh7110.o
\ No newline at end of file
--- /dev/null
+/**
+ ******************************************************************************
+ * @file pinctrl-starfive-jh7110.c
+ * @author StarFive Technology
+ * @version V1.0
+ * @date 11/30/2021
+ * @brief
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 20120 Shanghai StarFive Technology Co., Ltd. </center></h2>
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/gpio/driver.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
+#include "pinctrl-starfive.h"
+
+/*************************************sys_iomux***********************************/
+#define SYS_GPO_DOEN_CFG_BASE_REG 0x0
+#define SYS_GPO_DOEN_CFG_END_REG 0x3c
+
+#define SYS_GPO_DOUT_CFG_BASE_REG 0x40
+#define SYS_GPO_DOUT_CFG_END_REG 0x7c
+
+#define SYS_GPI_DIN_CFG_BASE_REG 0x80
+#define SYS_GPI_DIN_CFG_END_REG 0xd8
+
+/*sys_iomux PIN 0-74 ioconfig reg*/
+#define SYS_GPO_PDA_0_74_CFG_BASE_REG 0x120
+#define SYS_GPO_PDA_0_74_CFG_END_REG 0x248
+
+/*sys_iomux PIN 75-88 gamc1 no ioconfig reg*/
+
+/*sys_iomux PIN 89-94 ioconfig reg*/
+#define SYS_GPO_PDA_89_94_CFG_BASE_REG 0x284
+#define SYS_GPO_PDA_89_94_CFG_END_REG 0x298
+
+//sys_iomux GPIO CTRL
+#define GPIO_EN 0xdc
+#define GPIO_IS_LOW 0xe0
+#define GPIO_IS_HIGH 0xe4
+#define GPIO_IC_LOW 0xe8
+#define GPIO_IC_HIGH 0xec
+#define GPIO_IBE_LOW 0xf0
+#define GPIO_IBE_HIGH 0xf4
+#define GPIO_IEV_LOW 0xf8
+#define GPIO_IEV_HIGH 0xfc
+#define GPIO_IE_LOW 0x100
+#define GPIO_IE_HIGH 0x104
+//read only
+#define GPIO_RIS_LOW 0x108
+#define GPIO_RIS_HIGH 0x10c
+#define GPIO_MIS_LOW 0x110
+#define GPIO_MIS_HIGH 0x114
+#define GPIO_DIN_LOW 0x118
+#define GPIO_DIN_HIGH 0x11c
+
+#define GPIO_DOEN_X_REG 0x0
+#define GPIO_DOUT_X_REG 0x40
+
+#define GPIO_INPUT_ENABLE_X_REG 0x120
+
+#define MAX_GPIO 64
+/*************************************sys_iomux***********************************/
+
+
+/*************************************aon_iomux***********************************/
+#define AON_GPO_DOEN_CFG_BASE_REG 0x0
+#define AON_GPO_DOUT_CFG_BASE_REG 0x4
+#define AON_GPI_DIN_CFG_BASE_REG 0x8
+
+//aon_iomux GPIO CTRL
+#define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_3_ADDR (0xcU)
+#define AON_GPIOEN_0_REG_SHIFT 0x0U
+#define AON_GPIOEN_0_REG_MASK 0x1U
+#define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_4_ADDR (0x10U)
+#define AON_GPIOIS_0_REG_SHIFT 0x0U
+#define AON_GPIOIS_0_REG_MASK 0xFU
+#define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_5_ADDR (0x14U)
+#define AON_GPIOIC_0_REG_SHIFT 0x0U
+#define AON_GPIOIC_0_REG_MASK 0xFU
+#define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_6_ADDR (0x18U)
+#define AON_GPIOIBE_0_REG_SHIFT 0x0U
+#define AON_GPIOIBE_0_REG_MASK 0xFU
+#define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_7_ADDR (0x1cU)
+#define AON_GPIOIEV_0_REG_SHIFT 0x0U
+#define AON_GPIOIEV_0_REG_MASK 0xFU
+#define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_8_ADDR (0x20U)
+#define AON_GPIOIE_0_REG_SHIFT 0x0U
+#define AON_GPIOIE_0_REG_MASK 0xFU
+#define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_9_ADDR (0x24U)
+#define AON_GPIORIS_0_REG_SHIFT 0x0U
+#define AON_GPIORIS_0_REG_MASK 0xFU
+#define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_10_ADDR (0x28U)
+#define AON_GPIOMIS_0_REG_SHIFT 0x0U
+#define AON_GPIOMIS_0_REG_MASK 0xFU
+#define AON_IOMUX_CFGSAIF__SYSCFG_IOIRQ_11_ADDR (0x2cU)
+#define AON_GPIO_IN_SYNC2_0_REG_SHIFT 0x0U
+#define AON_GPIO_IN_SYNC2_0_REG_MASK 0xFU
+
+
+/* aon_iomux PIN ioconfig reg*/
+#define AON_IOMUX_CFG__SAIF__SYSCFG_48_ADDR (0x30U)
+#define PADCFG_PAD_TESTEN_POS_WIDTH 0x1U
+#define PADCFG_PAD_TESTEN_POS_SHIFT 0x0U
+#define PADCFG_PAD_TESTEN_POS_MASK 0x1U
+#define AON_IOMUX_CFG__SAIF__SYSCFG_52_ADDR (0x34U)
+#define PADCFG_PAD_RGPIO0_IE_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO0_IE_SHIFT 0x0U
+#define PADCFG_PAD_RGPIO0_IE_MASK 0x1U
+#define PADCFG_PAD_RGPIO0_DS_WIDTH 0x2U
+#define PADCFG_PAD_RGPIO0_DS_SHIFT 0x1U
+#define PADCFG_PAD_RGPIO0_DS_MASK 0x6U
+#define PADCFG_PAD_RGPIO0_PU_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO0_PU_SHIFT 0x3U
+#define PADCFG_PAD_RGPIO0_PU_MASK 0x8U
+#define PADCFG_PAD_RGPIO0_PD_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO0_PD_SHIFT 0x4U
+#define PADCFG_PAD_RGPIO0_PD_MASK 0x10U
+#define PADCFG_PAD_RGPIO0_SLEW_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO0_SLEW_SHIFT 0x5U
+#define PADCFG_PAD_RGPIO0_SLEW_MASK 0x20U
+#define PADCFG_PAD_RGPIO0_SMT_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO0_SMT_SHIFT 0x6U
+#define PADCFG_PAD_RGPIO0_SMT_MASK 0x40U
+#define PADCFG_PAD_RGPIO0_POS_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO0_POS_SHIFT 0x7U
+#define PADCFG_PAD_RGPIO0_POS_MASK 0x80U
+#define AON_IOMUX_CFG__SAIF__SYSCFG_56_ADDR (0x38U)
+#define PADCFG_PAD_RGPIO1_IE_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO1_IE_SHIFT 0x0U
+#define PADCFG_PAD_RGPIO1_IE_MASK 0x1U
+#define PADCFG_PAD_RGPIO1_DS_WIDTH 0x2U
+#define PADCFG_PAD_RGPIO1_DS_SHIFT 0x1U
+#define PADCFG_PAD_RGPIO1_DS_MASK 0x6U
+#define PADCFG_PAD_RGPIO1_PU_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO1_PU_SHIFT 0x3U
+#define PADCFG_PAD_RGPIO1_PU_MASK 0x8U
+#define PADCFG_PAD_RGPIO1_PD_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO1_PD_SHIFT 0x4U
+#define PADCFG_PAD_RGPIO1_PD_MASK 0x10U
+#define PADCFG_PAD_RGPIO1_SLEW_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO1_SLEW_SHIFT 0x5U
+#define PADCFG_PAD_RGPIO1_SLEW_MASK 0x20U
+#define PADCFG_PAD_RGPIO1_SMT_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO1_SMT_SHIFT 0x6U
+#define PADCFG_PAD_RGPIO1_SMT_MASK 0x40U
+#define PADCFG_PAD_RGPIO1_POS_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO1_POS_SHIFT 0x7U
+#define PADCFG_PAD_RGPIO1_POS_MASK 0x80U
+#define AON_IOMUX_CFG__SAIF__SYSCFG_60_ADDR (0x3cU)
+#define PADCFG_PAD_RGPIO2_IE_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO2_IE_SHIFT 0x0U
+#define PADCFG_PAD_RGPIO2_IE_MASK 0x1U
+#define PADCFG_PAD_RGPIO2_DS_WIDTH 0x2U
+#define PADCFG_PAD_RGPIO2_DS_SHIFT 0x1U
+#define PADCFG_PAD_RGPIO2_DS_MASK 0x6U
+#define PADCFG_PAD_RGPIO2_PU_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO2_PU_SHIFT 0x3U
+#define PADCFG_PAD_RGPIO2_PU_MASK 0x8U
+#define PADCFG_PAD_RGPIO2_PD_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO2_PD_SHIFT 0x4U
+#define PADCFG_PAD_RGPIO2_PD_MASK 0x10U
+#define PADCFG_PAD_RGPIO2_SLEW_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO2_SLEW_SHIFT 0x5U
+#define PADCFG_PAD_RGPIO2_SLEW_MASK 0x20U
+#define PADCFG_PAD_RGPIO2_SMT_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO2_SMT_SHIFT 0x6U
+#define PADCFG_PAD_RGPIO2_SMT_MASK 0x40U
+#define PADCFG_PAD_RGPIO2_POS_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO2_POS_SHIFT 0x7U
+#define PADCFG_PAD_RGPIO2_POS_MASK 0x80U
+#define AON_IOMUX_CFG__SAIF__SYSCFG_64_ADDR (0x40U)
+#define PADCFG_PAD_RGPIO3_IE_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO3_IE_SHIFT 0x0U
+#define PADCFG_PAD_RGPIO3_IE_MASK 0x1U
+#define PADCFG_PAD_RGPIO3_DS_WIDTH 0x2U
+#define PADCFG_PAD_RGPIO3_DS_SHIFT 0x1U
+#define PADCFG_PAD_RGPIO3_DS_MASK 0x6U
+#define PADCFG_PAD_RGPIO3_PU_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO3_PU_SHIFT 0x3U
+#define PADCFG_PAD_RGPIO3_PU_MASK 0x8U
+#define PADCFG_PAD_RGPIO3_PD_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO3_PD_SHIFT 0x4U
+#define PADCFG_PAD_RGPIO3_PD_MASK 0x10U
+#define PADCFG_PAD_RGPIO3_SLEW_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO3_SLEW_SHIFT 0x5U
+#define PADCFG_PAD_RGPIO3_SLEW_MASK 0x20U
+#define PADCFG_PAD_RGPIO3_SMT_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO3_SMT_SHIFT 0x6U
+#define PADCFG_PAD_RGPIO3_SMT_MASK 0x40U
+#define PADCFG_PAD_RGPIO3_POS_WIDTH 0x1U
+#define PADCFG_PAD_RGPIO3_POS_SHIFT 0x7U
+#define PADCFG_PAD_RGPIO3_POS_MASK 0x80U
+#define AON_IOMUX_CFG__SAIF__SYSCFG_68_ADDR (0x44U)
+#define PADCFG_PAD_RSTN_SMT_WIDTH 0x1U
+#define PADCFG_PAD_RSTN_SMT_SHIFT 0x0U
+#define PADCFG_PAD_RSTN_SMT_MASK 0x1U
+#define PADCFG_PAD_RSTN_POS_WIDTH 0x1U
+#define PADCFG_PAD_RSTN_POS_SHIFT 0x1U
+#define PADCFG_PAD_RSTN_POS_MASK 0x2U
+#define AON_IOMUX_CFG__SAIF__SYSCFG_72_ADDR (0x48U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_76_ADDR (0x4cU)
+#define PADCFG_PAD_RTC_DS_WIDTH 0x2U
+#define PADCFG_PAD_RTC_DS_SHIFT 0x0U
+#define PADCFG_PAD_RTC_DS_MASK 0x3U
+#define AON_IOMUX_CFG__SAIF__SYSCFG_80_ADDR (0x50U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_84_ADDR (0x54U)
+#define PADCFG_PAD_OSC_DS_WIDTH 0x2U
+#define PADCFG_PAD_OSC_DS_SHIFT 0x0U
+#define PADCFG_PAD_OSC_DS_MASK 0x3U
+
+/*aon_iomux PIN 0-5 ioconfig reg*/
+#define AON_GPO_PDA_0_5_CFG_BASE_REG AON_IOMUX_CFG__SAIF__SYSCFG_48_ADDR
+#define AON_GPO_PDA_0_5_CFG_END_REG AON_IOMUX_CFG__SAIF__SYSCFG_68_ADDR
+#define AON_GPO_PDA_RTC_CFG_REG AON_IOMUX_CFG__SAIF__SYSCFG_76_ADDR
+/*************************************aon_iomux***********************************/
+
+#define PADCFG_PAD_GMAC_SYSCON_WIDTH 0x2U
+#define PADCFG_PAD_GMAC_SYSCON_SHIFT 0x0U
+#define PADCFG_PAD_GMAC_SYSCON_MASK 0x3U
+
+#define GPO_PDA_CFG_OFFSET 0x4U
+
+#define GPIO_NUM_SHIFT 2 //one dword include 4 gpios
+#define GPIO_BYTE_SHIFT 3 //8 bits for each gpio
+#define GPIO_INDEX_MASK 0x3 //gpio index in dword
+#define GPIO_VAL_MASK 0x7f //
+
+enum starfive_jh7110_sys_pads {
+ PAD_GPIO0 = 0,
+ PAD_GPIO1 = 1,
+ PAD_GPIO2 = 2,
+ PAD_GPIO3 = 3,
+ PAD_GPIO4 = 4,
+ PAD_GPIO5 = 5,
+ PAD_GPIO6 = 6,
+ PAD_GPIO7 = 7,
+ PAD_GPIO8 = 8,
+ PAD_GPIO9 = 9,
+ PAD_GPIO10 = 10,
+ PAD_GPIO11 = 11,
+ PAD_GPIO12 = 12,
+ PAD_GPIO13 = 13,
+ PAD_GPIO14 = 14,
+ PAD_GPIO15 = 15,
+ PAD_GPIO16 = 16,
+ PAD_GPIO17 = 17,
+ PAD_GPIO18 = 18,
+ PAD_GPIO19 = 19,
+ PAD_GPIO20 = 20,
+ PAD_GPIO21 = 21,
+ PAD_GPIO22 = 22,
+ PAD_GPIO23 = 23,
+ PAD_GPIO24 = 24,
+ PAD_GPIO25 = 25,
+ PAD_GPIO26 = 26,
+ PAD_GPIO27 = 27,
+ PAD_GPIO28 = 28,
+ PAD_GPIO29 = 29,
+ PAD_GPIO30 = 30,
+ PAD_GPIO31 = 31,
+ PAD_GPIO32 = 32,
+ PAD_GPIO33 = 33,
+ PAD_GPIO34 = 34,
+ PAD_GPIO35 = 35,
+ PAD_GPIO36 = 36,
+ PAD_GPIO37 = 37,
+ PAD_GPIO38 = 38,
+ PAD_GPIO39 = 39,
+ PAD_GPIO40 = 40,
+ PAD_GPIO41 = 41,
+ PAD_GPIO42 = 42,
+ PAD_GPIO43 = 43,
+ PAD_GPIO44 = 44,
+ PAD_GPIO45 = 45,
+ PAD_GPIO46 = 46,
+ PAD_GPIO47 = 47,
+ PAD_GPIO48 = 48,
+ PAD_GPIO49 = 49,
+ PAD_GPIO50 = 50,
+ PAD_GPIO51 = 51,
+ PAD_GPIO52 = 52,
+ PAD_GPIO53 = 53,
+ PAD_GPIO54 = 54,
+ PAD_GPIO55 = 55,
+ PAD_GPIO56 = 56,
+ PAD_GPIO57 = 57,
+ PAD_GPIO58 = 58,
+ PAD_GPIO59 = 59,
+ PAD_GPIO60 = 60,
+ PAD_GPIO61 = 61,
+ PAD_GPIO62 = 62,
+ PAD_GPIO63 = 63,
+ PAD_SD0_CLK = 64,
+ PAD_SD0_CMD = 65,
+ PAD_SD0_DATA0 = 66,
+ PAD_SD0_DATA1 = 67,
+ PAD_SD0_DATA2 = 68,
+ PAD_SD0_DATA3 = 69,
+ PAD_SD0_DATA4 = 70,
+ PAD_SD0_DATA5 = 71,
+ PAD_SD0_DATA6 = 72,
+ PAD_SD0_DATA7 = 73,
+ PAD_SD0_STRB = 74,
+ PAD_GMAC1_MDC = 75,
+ PAD_GMAC1_MDIO = 76,
+ PAD_GMAC1_RXD0 = 77,
+ PAD_GMAC1_RXD1 = 78,
+ PAD_GMAC1_RXD2 = 79,
+ PAD_GMAC1_RXD3 = 80,
+ PAD_GMAC1_RXDV = 81,
+ PAD_GMAC1_RXC = 82,
+ PAD_GMAC1_TXD0 = 83,
+ PAD_GMAC1_TXD1 = 84,
+ PAD_GMAC1_TXD2 = 85,
+ PAD_GMAC1_TXD3 = 86,
+ PAD_GMAC1_TXEN = 87,
+ PAD_GMAC1_TXC = 88,
+ PAD_QSPI_SCLK = 89,
+ PAD_QSPI_CSn0 = 90,
+ PAD_QSPI_DATA0 = 91,
+ PAD_QSPI_DATA1 = 92,
+ PAD_QSPI_DATA2 = 93,
+ PAD_QSPI_DATA3 = 94,
+};
+
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc starfive_jh7110_sys_pinctrl_pads[] = {
+ STARFIVE_PINCTRL_PIN(PAD_GPIO0),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO1),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO2),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO3),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO4),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO5),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO6),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO7),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO8),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO9),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO10),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO11),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO12),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO13),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO14),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO15),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO16),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO17),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO18),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO19),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO20),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO21),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO22),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO23),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO24),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO25),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO26),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO27),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO28),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO29),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO30),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO31),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO32),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO33),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO34),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO35),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO36),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO37),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO38),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO39),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO40),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO41),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO42),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO43),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO44),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO45),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO46),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO47),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO48),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO49),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO50),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO51),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO52),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO53),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO54),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO55),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO56),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO57),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO58),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO59),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO60),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO61),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO62),
+ STARFIVE_PINCTRL_PIN(PAD_GPIO63),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_CLK),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_CMD),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_DATA0),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_DATA1),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_DATA2),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_DATA3),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_DATA4),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_DATA5),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_DATA6),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_DATA7),
+ STARFIVE_PINCTRL_PIN(PAD_SD0_STRB),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_MDC),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_MDIO),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXD0),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXD1),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXD2),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXD3),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXDV),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_RXC),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXD0),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXD1),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXD2),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXD3),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXEN),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC1_TXC),
+ STARFIVE_PINCTRL_PIN(PAD_QSPI_SCLK),
+ STARFIVE_PINCTRL_PIN(PAD_QSPI_CSn0),
+ STARFIVE_PINCTRL_PIN(PAD_QSPI_DATA0),
+ STARFIVE_PINCTRL_PIN(PAD_QSPI_DATA1),
+ STARFIVE_PINCTRL_PIN(PAD_QSPI_DATA2),
+ STARFIVE_PINCTRL_PIN(PAD_QSPI_DATA3),
+};
+
+enum starfive_jh7110_aon_pads {
+ PAD_TESTEN = 0,
+ PAD_RGPIO0 = 1,
+ PAD_RGPIO1 = 2,
+ PAD_RGPIO2 = 3,
+ PAD_RGPIO3 = 4,
+ PAD_RSTN = 5,
+ PAD_GMAC0_MDC = 6,
+ PAD_GMAC0_MDIO = 7,
+ PAD_GMAC0_RXD0 = 8,
+ PAD_GMAC0_RXD1 = 9,
+ PAD_GMAC0_RXD2 = 10,
+ PAD_GMAC0_RXD3 = 11,
+ PAD_GMAC0_RXDV = 12,
+ PAD_GMAC0_RXC = 13,
+ PAD_GMAC0_TXD0 = 14,
+ PAD_GMAC0_TXD1 = 15,
+ PAD_GMAC0_TXD2 = 16,
+ PAD_GMAC0_TXD3 = 17,
+ PAD_GMAC0_TXEN = 18,
+ PAD_GMAC0_TXC = 19,
+};
+
+static const struct pinctrl_pin_desc starfive_jh7110_aon_pinctrl_pads[] = {
+ STARFIVE_PINCTRL_PIN(PAD_TESTEN),
+ STARFIVE_PINCTRL_PIN(PAD_RGPIO0),
+ STARFIVE_PINCTRL_PIN(PAD_RGPIO1),
+ STARFIVE_PINCTRL_PIN(PAD_RGPIO2),
+ STARFIVE_PINCTRL_PIN(PAD_RGPIO3),
+ STARFIVE_PINCTRL_PIN(PAD_RSTN),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_MDC),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_MDIO),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXD0),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXD1),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXD2),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXD3),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXDV),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_RXC),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXD0),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXD1),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXD2),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXD3),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXEN),
+ STARFIVE_PINCTRL_PIN(PAD_GMAC0_TXC),
+};
+
+static void pinctrl_write_reg(volatile void __iomem *addr, u32 mask, u32 val)
+{
+ u32 value;
+
+ value = readl_relaxed(addr);
+ value &= ~mask;
+ value |= (val & mask);
+ writel_relaxed(value,addr);
+}
+
+uint32_t pinctrl_get_reg(volatile void __iomem *addr,u32 shift,u32 mask)
+{
+ u32 tmp;
+ tmp = readl_relaxed(addr);
+ tmp = (tmp & mask) >> shift;
+ return tmp;
+}
+
+void pinctrl_set_reg(volatile void __iomem *addr,u32 data,u32 shift,u32 mask)
+{
+ u32 tmp;
+
+ tmp = readl_relaxed(addr);
+ tmp &= ~mask;
+ tmp |= (data<<shift) & mask;
+ writel_relaxed(tmp,addr);
+}
+
+static int starfive_jh7110_sys_direction_input(struct gpio_chip *gc, unsigned offset)
+{
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ unsigned long flags;
+ unsigned int v;
+
+ if (offset >= gc->ngpio)
+ return -EINVAL;
+
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ v = readl_relaxed(chip->padctl_base + GPIO_DOEN_X_REG + (offset & ~0x3));
+ v &= ~(0x3f << ((offset & 0x3) * 8));
+ v |= 1 << ((offset & 0x3) * 8);
+ writel_relaxed(v, chip->padctl_base + GPIO_DOEN_X_REG + (offset & ~0x3));
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+ return 0;
+}
+
+static int starfive_jh7110_sys_direction_output(struct gpio_chip *gc, unsigned offset, int value)
+{
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ unsigned long flags;
+ unsigned int v;
+
+ if (offset >= gc->ngpio)
+ return -EINVAL;
+
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ v = readl_relaxed(chip->padctl_base + GPIO_DOEN_X_REG + (offset & ~0x3));
+ v &= ~(0x3f << ((offset & 0x3) * 8));
+ writel_relaxed(v, chip->padctl_base + GPIO_DOEN_X_REG + (offset & ~0x3));
+
+ v = readl_relaxed(chip->padctl_base + GPIO_DOUT_X_REG + (offset & ~0x3));
+ v &= ~(0x7f << ((offset & 0x3) * 8));
+ v |= value << ((offset & 0x3) * 8);
+ writel_relaxed(v, chip->padctl_base + GPIO_DOUT_X_REG + (offset & ~0x3));
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+
+ return 0;
+}
+
+static int starfive_jh7110_sys_get_direction(struct gpio_chip *gc, unsigned offset)
+{
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ unsigned int v;
+
+ if (offset >= gc->ngpio)
+ return -EINVAL;
+
+ v = readl_relaxed(chip->padctl_base + GPIO_DOEN_X_REG + (offset & ~0x3));
+ return !!(v & (0x3f << ((offset & 0x3) * 8)));
+}
+
+static int starfive_jh7110_sys_get_value(struct gpio_chip *gc, unsigned offset)
+{
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ int value;
+
+ if (offset >= gc->ngpio)
+ return -EINVAL;
+
+ if(offset < 32){
+ value = readl_relaxed(chip->padctl_base + GPIO_DIN_LOW);
+ return (value >> offset) & 0x1;
+ } else {
+ value = readl_relaxed(chip->padctl_base + GPIO_DIN_HIGH);
+ return (value >> (offset - 32)) & 0x1;
+ }
+}
+
+static void starfive_jh7110_sys_set_value(struct gpio_chip *gc, unsigned offset, int value)
+{
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ unsigned long flags;
+ unsigned int v;
+
+ if (offset >= gc->ngpio)
+ return;
+
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ v = readl_relaxed(chip->padctl_base + GPIO_DOUT_X_REG + (offset & ~0x3));
+ v &= ~(0x7f << ((offset & 0x3) * 8));
+ v |= value << ((offset & 0x3) * 8);
+ writel_relaxed(v, chip->padctl_base + GPIO_DOUT_X_REG + (offset & ~0x3));
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+}
+
+static void starfive_jh7110_sys_set_ie(struct starfive_pinctrl *chip, int offset)
+{
+ unsigned long flags;
+ int old_value, new_value;
+ int reg_offset, index;
+
+ if(offset < 32) {
+ reg_offset = 0;
+ index = offset;
+ } else {
+ reg_offset = 4;
+ index = offset - 32;
+ }
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ old_value = readl_relaxed(chip->padctl_base + GPIO_IE_LOW + reg_offset);
+ new_value = old_value | ( 1 << index);
+ writel_relaxed(new_value, chip->padctl_base + GPIO_IE_LOW + reg_offset);
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+}
+
+static int starfive_jh7110_sys_irq_set_type(struct irq_data *d, unsigned trigger)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ int offset = irqd_to_hwirq(d);
+ unsigned int reg_is, reg_ibe, reg_iev;
+ int reg_offset, index;
+
+ if (offset < 0 || offset >= gc->ngpio)
+ return -EINVAL;
+
+ if(offset < 32) {
+ reg_offset = 0;
+ index = offset;
+ } else {
+ reg_offset = 4;
+ index = offset - 32;
+ }
+ switch(trigger) {
+ case IRQ_TYPE_LEVEL_HIGH:
+ reg_is = readl_relaxed(chip->padctl_base + GPIO_IS_LOW + reg_offset);
+ reg_ibe = readl_relaxed(chip->padctl_base + GPIO_IBE_LOW + reg_offset);
+ reg_iev = readl_relaxed(chip->padctl_base + GPIO_IEV_LOW + reg_offset);
+ reg_is &= (~(0x1<< index));
+ reg_ibe &= (~(0x1<< index));
+ reg_iev |= (~(0x1<< index));
+ writel_relaxed(reg_is, chip->padctl_base + GPIO_IS_LOW + reg_offset);
+ writel_relaxed(reg_ibe, chip->padctl_base + GPIO_IBE_LOW + reg_offset);
+ writel_relaxed(reg_iev, chip->padctl_base + GPIO_IEV_LOW + reg_offset);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ reg_is = readl_relaxed(chip->padctl_base + GPIO_IS_LOW + reg_offset);
+ reg_ibe = readl_relaxed(chip->padctl_base + GPIO_IBE_LOW + reg_offset);
+ reg_iev = readl_relaxed(chip->padctl_base + GPIO_IEV_LOW + reg_offset);
+ reg_is &= (~(0x1<< index));
+ reg_ibe &= (~(0x1<< index));
+ reg_iev &= (0x1<< index);
+ writel_relaxed(reg_is, chip->padctl_base + GPIO_IS_LOW + reg_offset);
+ writel_relaxed(reg_ibe, chip->padctl_base + GPIO_IBE_LOW + reg_offset);
+ writel_relaxed(reg_iev, chip->padctl_base + GPIO_IEV_LOW + reg_offset);
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ reg_is = readl_relaxed(chip->padctl_base + GPIO_IS_LOW + reg_offset);
+ reg_ibe = readl_relaxed(chip->padctl_base + GPIO_IBE_LOW + reg_offset);
+ reg_iev = readl_relaxed(chip->padctl_base + GPIO_IEV_LOW + reg_offset);
+ reg_is |= (0x1<< index);
+ reg_ibe |= (0x1<< index);
+ reg_iev |= (~(0x1<< index));
+ writel_relaxed(reg_is, chip->padctl_base + GPIO_IS_LOW + reg_offset);
+ writel_relaxed(reg_ibe, chip->padctl_base + GPIO_IBE_LOW + reg_offset);
+ writel_relaxed(reg_iev, chip->padctl_base + GPIO_IEV_LOW + reg_offset);
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ reg_is = readl_relaxed(chip->padctl_base + GPIO_IS_LOW + reg_offset);
+ reg_ibe = readl_relaxed(chip->padctl_base + GPIO_IBE_LOW + reg_offset);
+ reg_iev = readl_relaxed(chip->padctl_base + GPIO_IEV_LOW + reg_offset);
+ reg_is |= (0x1<< index);
+ reg_ibe &= (~(0x1<< index));
+ reg_iev |= (0x1<< index);
+ writel_relaxed(reg_is, chip->padctl_base + GPIO_IS_LOW + reg_offset);
+ writel_relaxed(reg_ibe, chip->padctl_base + GPIO_IBE_LOW + reg_offset);
+ writel_relaxed(reg_iev, chip->padctl_base + GPIO_IEV_LOW + reg_offset);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ reg_is = readl_relaxed(chip->padctl_base + GPIO_IS_LOW + reg_offset);
+ reg_ibe = readl_relaxed(chip->padctl_base + GPIO_IBE_LOW + reg_offset);
+ reg_iev = readl_relaxed(chip->padctl_base + GPIO_IEV_LOW + reg_offset);
+ reg_is |= (0x1<< index);
+ reg_ibe &= (~(0x1<< index));
+ reg_iev &= (~(0x1<< index));
+ writel_relaxed(reg_is, chip->padctl_base + GPIO_IS_LOW + reg_offset);
+ writel_relaxed(reg_ibe, chip->padctl_base + GPIO_IBE_LOW + reg_offset);
+ writel_relaxed(reg_iev, chip->padctl_base + GPIO_IEV_LOW + reg_offset);
+ break;
+ }
+
+ chip->trigger[offset] = trigger;
+ starfive_jh7110_sys_set_ie(chip, offset);
+ return 0;
+}
+
+/* chained_irq_{enter,exit} already mask the parent */
+static void starfive_jh7110_sys_irq_mask(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ unsigned int value;
+ int offset = irqd_to_hwirq(d);
+ int reg_offset, index;
+
+ if (offset < 0 || offset >= gc->ngpio)
+ return;
+
+ if(offset < 32) {
+ reg_offset = 0;
+ index = offset;
+ } else {
+ reg_offset = 4;
+ index = offset - 32;
+ }
+
+ value = readl_relaxed(chip->padctl_base + GPIO_IE_LOW + reg_offset);
+ value &= ~(0x1 << index);
+ writel_relaxed(value,chip->padctl_base + GPIO_IE_LOW + reg_offset);
+}
+
+static void starfive_jh7110_sys_irq_unmask(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ unsigned int value;
+ int offset = irqd_to_hwirq(d);
+ int reg_offset, index;
+
+ if (offset < 0 || offset >= gc->ngpio)
+ return;
+
+ if(offset < 32) {
+ reg_offset = 0;
+ index = offset;
+ } else {
+ reg_offset = 4;
+ index = offset - 32;
+ }
+
+ value = readl_relaxed(chip->padctl_base + GPIO_IE_LOW + reg_offset);
+ value |= (0x1 << index);
+ writel_relaxed(value,chip->padctl_base + GPIO_IE_LOW + reg_offset);
+}
+
+static void starfive_jh7110_sys_irq_enable(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ int offset = irqd_to_hwirq(d);
+
+ starfive_jh7110_sys_irq_unmask(d);
+ assign_bit(offset, &chip->enabled, 1);
+}
+
+static void starfive_jh7110_sys_irq_disable(struct irq_data *d)
+{
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct starfive_pinctrl *chip = gpiochip_get_data(gc);
+ int offset = irqd_to_hwirq(d) % MAX_GPIO; // must not fail
+
+ assign_bit(offset, &chip->enabled, 0);
+ starfive_jh7110_sys_set_ie(chip, offset);
+}
+
+static struct irq_chip starfive_jh7110_sys_irqchip = {
+ .name = "starfive_jh7110_sys-gpio",
+ .irq_set_type = starfive_jh7110_sys_irq_set_type,
+ .irq_mask = starfive_jh7110_sys_irq_mask,
+ .irq_unmask = starfive_jh7110_sys_irq_unmask,
+ .irq_enable = starfive_jh7110_sys_irq_enable,
+ .irq_disable = starfive_jh7110_sys_irq_disable,
+};
+
+static irqreturn_t starfive_jh7110_sys_irq_handler(int irq, void *gc)
+{
+ int offset;
+ int reg_offset, index;
+ unsigned int value;
+ unsigned long flags;
+ struct starfive_pinctrl *chip = gc;
+
+ for (offset = 0; offset < 64; offset++) {
+ if(offset < 32) {
+ reg_offset = 0;
+ index = offset;
+ } else {
+ reg_offset = 4;
+ index = offset - 32;
+ }
+
+ raw_spin_lock_irqsave(&chip->lock, flags);
+ value = readl_relaxed(chip->padctl_base + GPIO_MIS_LOW + reg_offset);
+ if(value & BIT(index))
+ writel_relaxed(BIT(index), chip->padctl_base + GPIO_IC_LOW +
+ reg_offset);
+
+ //generic_handle_irq(irq_find_mapping(chip->gc.irq.domain,
+ // offset));
+ raw_spin_unlock_irqrestore(&chip->lock, flags);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static int starfive_jh7110_sys_gpio_register(struct platform_device *pdev,
+ struct starfive_pinctrl *ipctl)
+{
+ struct device *dev = &pdev->dev;
+ int irq, ret, ngpio;
+ int loop;
+
+ ngpio = 64;
+
+ ipctl->gc.direction_input = starfive_jh7110_sys_direction_input;
+ ipctl->gc.direction_output = starfive_jh7110_sys_direction_output;
+ ipctl->gc.get_direction = starfive_jh7110_sys_get_direction;
+ ipctl->gc.get = starfive_jh7110_sys_get_value;
+ ipctl->gc.set = starfive_jh7110_sys_set_value;
+ ipctl->gc.base = 0;
+ ipctl->gc.ngpio = ngpio;
+ ipctl->gc.label = dev_name(dev);
+ ipctl->gc.parent = dev;
+ ipctl->gc.owner = THIS_MODULE;
+
+ ret = gpiochip_add_data(&ipctl->gc, ipctl);
+ if (ret){
+ dev_err(dev, "gpiochip_add_data ret=%d!\n", ret);
+ return ret;
+ }
+
+ /* Disable all GPIO interrupts before enabling parent interrupts */
+ iowrite32(0, ipctl->padctl_base + GPIO_IE_HIGH);
+ iowrite32(0, ipctl->padctl_base + GPIO_IE_LOW);
+ ipctl->enabled = 0;
+
+ ret = gpiochip_irqchip_add(&ipctl->gc, &starfive_jh7110_sys_irqchip, 0,
+ handle_simple_irq, IRQ_TYPE_NONE);
+ if (ret) {
+ dev_err(dev, "could not add irqchip\n");
+ gpiochip_remove(&ipctl->gc);
+ return ret;
+ }
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(dev, "Cannot get IRQ resource\n");
+ return irq;
+ }
+
+ ret = devm_request_irq(dev, irq, starfive_jh7110_sys_irq_handler, IRQF_SHARED,
+ dev_name(dev), ipctl);
+ if (ret) {
+ dev_err(dev, "IRQ handler registering failed (%d)\n", ret);
+ return ret;
+ }
+
+ writel_relaxed(1, ipctl->padctl_base + GPIO_EN);
+
+ for(loop = 0; loop < MAX_GPIO; loop++) {
+ unsigned int v;
+ v = readl_relaxed(ipctl->padctl_base + GPIO_INPUT_ENABLE_X_REG + (loop << 2));
+ v |= 0x1;
+ writel_relaxed(v, ipctl->padctl_base + GPIO_INPUT_ENABLE_X_REG + (loop << 2));
+ }
+
+ dev_info(dev, "SiFive GPIO chip registered %d GPIOs\n", ngpio);
+
+ return 0;
+}
+
+
+static int starfive_jh7110_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin_id,
+ unsigned long *config)
+{
+ struct starfive_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct starfive_pinctrl_soc_info *info = ipctl->info;
+ const struct starfive_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
+ u32 value;
+
+ if (pin_reg->io_conf_reg == -1) {
+ dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
+ info->pins[pin_id].name);
+ return -EINVAL;
+ }
+
+ value = readl_relaxed(ipctl->padctl_base + pin_reg->io_conf_reg);
+ *config = value & 0xff;
+ return 0;
+}
+
+static int starfive_jh7110_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct starfive_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct starfive_pinctrl_soc_info *info = ipctl->info;
+ const struct starfive_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
+ int i;
+ u32 value;
+ unsigned long flags;
+
+ if (pin_reg->io_conf_reg == -1) {
+ dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
+ info->pins[pin_id].name);
+ return -EINVAL;
+ }
+
+ raw_spin_lock_irqsave(&ipctl->lock, flags);
+ for (i = 0; i < num_configs; i++) {
+ value = readl_relaxed(ipctl->padctl_base + pin_reg->io_conf_reg);
+ value = value|(configs[i] & 0xFF);
+ writel_relaxed(value, ipctl->padctl_base + pin_reg->io_conf_reg);
+ }
+ raw_spin_unlock_irqrestore(&ipctl->lock, flags);
+
+ return 0;
+}
+
+static int starfive_jh7110_sys_pmx_set_one_pin_mux(struct starfive_pinctrl *ipctl,
+ struct starfive_pin *pin)
+{
+ const struct starfive_pinctrl_soc_info *info = ipctl->info;
+ struct starfive_pin_config *pin_config = &pin->pin_config;
+ const struct starfive_pin_reg *pin_reg;
+ unsigned int gpio,pin_id;
+ int i;
+ unsigned long flags;
+ int n,shift;
+
+
+ gpio = pin->pin_config.gpio_num;
+ pin_id = pin->pin;
+ pin_reg = &ipctl->pin_regs[pin_id];
+
+ raw_spin_lock_irqsave(&ipctl->lock, flags);
+ if(pin_reg->func_sel_reg != -1){
+ pinctrl_set_reg(ipctl->padctl_base + pin_reg->func_sel_reg,
+ pin_config->pinmux_func, pin_reg->func_sel_shift, pin_reg->func_sel_mask);
+ }
+
+ shift = (gpio & GPIO_INDEX_MASK) << GPIO_BYTE_SHIFT;
+ if(pin_reg->gpo_dout_reg != -1){
+ pinctrl_write_reg(ipctl->padctl_base + pin_reg->gpo_dout_reg,
+ 0x7F<<shift, pin_config->gpio_dout<<shift);
+ }
+
+ if(pin_reg->gpo_doen_reg != -1){
+ pinctrl_write_reg(ipctl->padctl_base + pin_reg->gpo_doen_reg,
+ 0x3F<<shift, pin_config->gpio_doen<<shift);
+ }
+
+ for(i = 0; i < pin_config->gpio_din_num; i++){
+ n = pin_config->gpio_din_reg[i] >> 2;
+ shift = (pin_config->gpio_din_reg[i] & 3) << 3;
+ pinctrl_write_reg(ipctl->padctl_base + info->din_reg_base + n * 4,
+ 0x3F<<shift, (gpio+2)<<shift);
+ }
+
+ if(pin_reg->syscon_reg != -1){
+ pinctrl_set_reg(ipctl->padctl_base + pin_reg->syscon_reg,
+ pin_config->syscon, PADCFG_PAD_GMAC_SYSCON_SHIFT,
+ PADCFG_PAD_GMAC_SYSCON_MASK);
+ }
+ raw_spin_unlock_irqrestore(&ipctl->lock, flags);
+
+ return 0;
+}
+
+
+static void starfive_jh7110_sys_parse_pin_config(struct starfive_pinctrl *ipctl,
+ unsigned int *pins_id, struct starfive_pin *pin_data,
+ const __be32 *list_p,
+ struct device_node *np)
+{
+ const struct starfive_pinctrl_soc_info *info = ipctl->info;
+ struct starfive_pin_reg *pin_reg;
+ const __be32 *list = list_p;
+ const __be32 *list_din;
+ int size;
+ int size_din;
+ int pin_size;
+ u32 value;
+ int i;
+ int n;
+
+ pin_size = 4;
+ *pins_id = be32_to_cpu(*list);
+ pin_reg = &ipctl->pin_regs[*pins_id];
+ pin_data->pin = *pins_id;
+
+ if(pin_data->pin > PAD_QSPI_DATA3){
+ dev_err(ipctl->dev,"err pin num\n");
+ return;
+ }
+
+ if(pin_data->pin < PAD_GMAC1_MDC){
+ pin_reg->io_conf_reg = (pin_data->pin * GPO_PDA_CFG_OFFSET) \
+ + SYS_GPO_PDA_0_74_CFG_BASE_REG;
+ }
+ else if(pin_data->pin > PAD_GMAC1_TXC){
+ pin_reg->io_conf_reg = (pin_data->pin * GPO_PDA_CFG_OFFSET) \
+ + SYS_GPO_PDA_89_94_CFG_BASE_REG;
+ }
+
+ if (!of_property_read_u32(np, "sf,pin-ioconfig", &value)) {
+ pin_data->pin_config.io_config = value;
+ }
+
+ list = of_get_property(np, "sf,pinmux", &size);
+ if (list) {
+ pin_reg->func_sel_reg = be32_to_cpu(*list++);
+ pin_reg->func_sel_shift = be32_to_cpu(*list++);
+ pin_reg->func_sel_mask = be32_to_cpu(*list++);
+ pin_data->pin_config.pinmux_func = be32_to_cpu(*list++);
+ }
+
+ list = of_get_property(np, "sf,pin-syscon", &size);
+ if (list) {
+ pin_reg->syscon_reg = be32_to_cpu(*list++);
+ pin_data->pin_config.syscon = be32_to_cpu(*list++);
+ }
+
+ if(pin_data->pin < PAD_SD0_CLK){
+
+ pin_data->pin_config.gpio_num = pin_data->pin;
+ n = pin_data->pin_config.gpio_num >> GPIO_NUM_SHIFT;
+
+ if (!of_property_read_u32(np, "sf,pin-gpio-dout", &value)) {
+ pin_data->pin_config.gpio_dout = value;
+ pin_reg->gpo_dout_reg = info->dout_reg_base + n * 4;
+ }
+
+ if (!of_property_read_u32(np, "sf,pin-gpio-doen", &value)) {
+ pin_data->pin_config.gpio_doen = value;
+ pin_reg->gpo_doen_reg = info->doen_reg_base + n * 4;
+ }
+
+ list_din = of_get_property(np, "sf,pin-gpio-din", &size_din);
+ if (list_din) {
+ if (!size_din || size_din % pin_size) {
+ dev_err(ipctl->dev,
+ "Invalid sf,pin-gpio-din property in node\n");
+ return;
+ }
+
+ pin_data->pin_config.gpio_din_num = size_din / pin_size;
+ pin_data->pin_config.gpio_din_reg = devm_kcalloc(ipctl->dev,
+ pin_data->pin_config.gpio_din_num, sizeof(s32),
+ GFP_KERNEL);
+
+ for(i = 0; i < pin_data->pin_config.gpio_din_num; i++){
+ value = be32_to_cpu(*list_din++);
+ pin_data->pin_config.gpio_din_reg[i] = value;
+ }
+ }
+ }
+ return;
+}
+
+
+
+static const struct starfive_pinctrl_soc_info starfive_jh7110_sys_pinctrl_info = {
+ .pins = starfive_jh7110_sys_pinctrl_pads,
+ .npins = ARRAY_SIZE(starfive_jh7110_sys_pinctrl_pads),
+ .flags = 1,
+ .dout_reg_base = SYS_GPO_DOUT_CFG_BASE_REG,
+ .doen_reg_base = SYS_GPO_DOEN_CFG_BASE_REG,
+ .din_reg_base = SYS_GPI_DIN_CFG_BASE_REG,
+ .starfive_pinconf_get = starfive_jh7110_pinconf_get,
+ .starfive_pinconf_set = starfive_jh7110_pinconf_set,
+ .starfive_pmx_set_one_pin_mux = starfive_jh7110_sys_pmx_set_one_pin_mux,
+ .starfive_gpio_register = starfive_jh7110_sys_gpio_register,
+ .starfive_pinctrl_parse_pin = starfive_jh7110_sys_parse_pin_config,
+};
+
+static int starfive_jh7110_aon_pmx_set_one_pin_mux(struct starfive_pinctrl *ipctl,
+ struct starfive_pin *pin)
+{
+ const struct starfive_pinctrl_soc_info *info = ipctl->info;
+ struct starfive_pin_config *pin_config = &pin->pin_config;
+ const struct starfive_pin_reg *pin_reg;
+ unsigned int gpio,pin_id;
+ int i;
+ unsigned long flags;
+ int n,shift;
+
+ gpio = pin->pin_config.gpio_num;
+ pin_id = pin->pin;
+ pin_reg = &ipctl->pin_regs[pin_id];
+
+ raw_spin_lock_irqsave(&ipctl->lock, flags);
+ if(pin_reg->func_sel_reg != -1){
+ pinctrl_set_reg(ipctl->padctl_base + pin_reg->func_sel_reg,
+ pin_config->pinmux_func, pin_reg->func_sel_shift, pin_reg->func_sel_mask);
+ }
+
+ shift = (gpio & GPIO_INDEX_MASK) << GPIO_BYTE_SHIFT;
+ if(pin_reg->gpo_dout_reg != -1){
+ pinctrl_write_reg(ipctl->padctl_base + pin_reg->gpo_dout_reg,
+ 0xF<<shift, pin_config->gpio_dout<<shift);
+
+ }
+
+ if(pin_reg->gpo_doen_reg != -1){
+ pinctrl_write_reg(ipctl->padctl_base + pin_reg->gpo_doen_reg,
+ 0x7<<shift, pin_config->gpio_doen<<shift);
+
+ }
+
+ for(i = 0; i < pin_config->gpio_din_num; i++){
+ n = pin_config->gpio_din_reg[i] >> 2;
+ shift = (pin_config->gpio_din_reg[i] & 3) << 3;
+ pinctrl_write_reg(ipctl->padctl_base + info->din_reg_base + n * 4,
+ 0x7<<shift, (gpio+2)<<shift);
+ }
+
+ if(pin_reg->syscon_reg != -1){
+ pinctrl_set_reg(ipctl->padctl_base + pin_reg->syscon_reg,
+ pin_config->syscon, PADCFG_PAD_GMAC_SYSCON_SHIFT, PADCFG_PAD_GMAC_SYSCON_MASK);
+ }
+
+ raw_spin_unlock_irqrestore(&ipctl->lock, flags);
+
+ return 0;
+}
+
+
+static void starfive_jh7110_aon_parse_pin_config(struct starfive_pinctrl *ipctl,
+ unsigned int *pins_id, struct starfive_pin *pin_data,
+ const __be32 *list_p,
+ struct device_node *np)
+{
+ const struct starfive_pinctrl_soc_info *info = ipctl->info;
+ struct starfive_pin_reg *pin_reg;
+ const __be32 *list = list_p;
+ const __be32 *list_din;
+ int size;
+ int size_din;
+ int pin_size;
+ u32 value;
+ int i;
+
+ pin_size = 4;
+ *pins_id = be32_to_cpu(*list);
+ pin_reg = &ipctl->pin_regs[*pins_id];
+ pin_data->pin = *pins_id;
+
+ if(pin_data->pin > PAD_GMAC0_TXC){
+ dev_err(ipctl->dev,"err pin num\n");
+ return;
+ }
+
+ if(pin_data->pin < PAD_GMAC0_MDC){
+ pin_reg->io_conf_reg = (pin_data->pin * GPO_PDA_CFG_OFFSET) \
+ + AON_GPO_PDA_0_5_CFG_BASE_REG;
+ }
+
+ if (!of_property_read_u32(np, "sf,pin-ioconfig", &value)) {
+ pin_data->pin_config.io_config = value;
+ }
+
+
+ list = of_get_property(np, "sf,pinmux", &size);
+ if (list) {
+ pin_reg->func_sel_reg = be32_to_cpu(*list++);
+ pin_reg->func_sel_shift = be32_to_cpu(*list++);
+ pin_reg->func_sel_mask = be32_to_cpu(*list++);
+ pin_data->pin_config.pinmux_func = be32_to_cpu(*list++);
+ }
+
+ list = of_get_property(np, "sf,pin-syscon", &size);
+ if (list) {
+ pin_reg->syscon_reg = be32_to_cpu(*list++);
+ pin_data->pin_config.syscon = be32_to_cpu(*list++);
+ }
+
+ if((pin_data->pin >= PAD_RGPIO0) && (pin_data->pin <= PAD_RGPIO3)){
+ pin_data->pin_config.gpio_num = pin_data->pin;
+ pin_reg->gpo_dout_reg = info->dout_reg_base;
+ pin_reg->gpo_doen_reg = info->doen_reg_base;
+
+ if (!of_property_read_u32(np, "sf,pin-gpio-dout", &value)) {
+ pin_data->pin_config.gpio_dout = value;
+ }
+
+
+ if (!of_property_read_u32(np, "sf,pin-gpio-doen", &value)) {
+ pin_data->pin_config.gpio_doen = value;
+ }
+
+
+ list_din = of_get_property(np, "sf,pin-gpio-din", &size_din);
+ if (list_din) {
+ if (!size_din || size_din % pin_size) {
+ dev_err(ipctl->dev,
+ "Invalid sf,pin-gpio-din property in node\n");
+ return;
+ }
+
+ pin_data->pin_config.gpio_din_num = size_din / pin_size;
+ pin_data->pin_config.gpio_din_reg = devm_kcalloc(ipctl->dev,
+ pin_data->pin_config.gpio_din_num, sizeof(s32),
+ GFP_KERNEL);
+
+ for(i = 0; i < pin_data->pin_config.gpio_din_num; i++){
+ value = be32_to_cpu(*list_din++);
+ pin_data->pin_config.gpio_din_reg[i] = value;
+ }
+ }
+ }
+
+ return;
+}
+
+
+static const struct starfive_pinctrl_soc_info starfive_jh7110_aon_pinctrl_info = {
+ .pins = starfive_jh7110_aon_pinctrl_pads,
+ .npins = ARRAY_SIZE(starfive_jh7110_aon_pinctrl_pads),
+ .flags = 1,
+ .dout_reg_base = AON_GPO_DOUT_CFG_BASE_REG,
+ .doen_reg_base = AON_GPO_DOEN_CFG_BASE_REG,
+ .din_reg_base = AON_GPI_DIN_CFG_BASE_REG,
+ .starfive_pinconf_get = starfive_jh7110_pinconf_get,
+ .starfive_pinconf_set = starfive_jh7110_pinconf_set,
+ .starfive_pmx_set_one_pin_mux = starfive_jh7110_aon_pmx_set_one_pin_mux,
+ .starfive_pinctrl_parse_pin = starfive_jh7110_aon_parse_pin_config,
+};
+
+
+static const struct of_device_id starfive_jh7110_pinctrl_of_match[] = {
+ { .compatible = "starfive_jh7110-sys-pinctrl", .data = &starfive_jh7110_sys_pinctrl_info, },
+ { .compatible = "starfive_jh7110-aon-pinctrl", .data = &starfive_jh7110_aon_pinctrl_info, },
+};
+
+static int starfive_jh7110_pinctrl_probe(struct platform_device *pdev)
+{
+ const struct starfive_pinctrl_soc_info *pinctrl_info;
+
+ pinctrl_info = of_device_get_match_data(&pdev->dev);
+ if (!pinctrl_info)
+ return -ENODEV;
+
+
+ return starfive_pinctrl_probe(pdev, pinctrl_info);
+}
+
+static struct platform_driver starfive_jh7110_pinctrl_driver = {
+ .driver = {
+ .name = "starfive_jh7110-pinctrl",
+ .of_match_table = of_match_ptr(starfive_jh7110_pinctrl_of_match),
+ },
+ .probe = starfive_jh7110_pinctrl_probe,
+};
+
+static int __init starfive_jh7110_pinctrl_init(void)
+{
+ return platform_driver_register(&starfive_jh7110_pinctrl_driver);
+}
+arch_initcall(starfive_jh7110_pinctrl_init);
--- /dev/null
+/**
+ ******************************************************************************
+ * @file pinctrl-starfive.c
+ * @author StarFive Technology
+ * @version V1.0
+ * @date 11/30/2021
+ * @brief
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 20120 Shanghai StarFive Technology Co., Ltd. </center></h2>
+ */
+
+#include <linux/gpio/driver.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+
+
+#include "../core.h"
+#include "../pinconf.h"
+#include "../pinmux.h"
+#include "pinctrl-starfive.h"
+
+
+static inline const struct group_desc *starfive_pinctrl_find_group_by_name(
+ struct pinctrl_dev *pctldev,
+ const char *name)
+{
+ const struct group_desc *grp = NULL;
+ int i,j;
+ int pinnum;
+
+ for (i = 0; i < pctldev->num_groups; i++) {
+ grp = pinctrl_generic_get_group(pctldev, i);
+ if (grp && !strcmp(grp->name, name))
+ break;
+ }
+
+ return grp;
+}
+
+static void starfive_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+ unsigned offset)
+{
+ seq_printf(s, "%s", dev_name(pctldev->dev));
+}
+
+static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
+ struct device_node *np,
+ struct pinctrl_map **map, unsigned *num_maps)
+{
+ struct starfive_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct starfive_pinctrl_soc_info *info = ipctl->info;
+ const struct group_desc *grp;
+ struct pinctrl_map *new_map;
+ struct device_node *parent;
+ struct starfive_pin *pin;
+ int map_num = 1;
+ int i, j;
+
+ /*
+ * first find the group of this node and check if we need create
+ * config maps for pins
+ */
+ grp = starfive_pinctrl_find_group_by_name(pctldev, np->name);
+ if (!grp) {
+ dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np);
+ return -EINVAL;
+ }
+
+ map_num = grp->num_pins + 1;
+ new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
+ GFP_KERNEL);
+ if (!new_map)
+ return -ENOMEM;
+
+ *map = new_map;
+ *num_maps = map_num;
+
+ /* create mux map */
+ parent = of_get_parent(np);
+ if (!parent) {
+ kfree(new_map);
+ return -EINVAL;
+ }
+ new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
+ new_map[0].data.mux.function = parent->name;
+ new_map[0].data.mux.group = np->name;
+ of_node_put(parent);
+
+ /* create config map */
+ new_map++;
+ for (i = j = 0; i < grp->num_pins; i++) {
+ pin = &((struct starfive_pin *)(grp->data))[i];
+
+ new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
+ new_map[j].data.configs.group_or_pin =
+ pin_get_name(pctldev, pin->pin);
+ new_map[j].data.configs.configs =
+ &pin->pin_config.io_config;
+ new_map[j].data.configs.num_configs = 1;
+ j++;
+ }
+
+ return 0;
+}
+
+static void starfive_dt_free_map(struct pinctrl_dev *pctldev,
+ struct pinctrl_map *map, unsigned num_maps)
+{
+ kfree(map);
+}
+
+static const struct pinctrl_ops starfive_pctrl_ops = {
+ .get_groups_count = pinctrl_generic_get_group_count,
+ .get_group_name = pinctrl_generic_get_group_name,
+ .get_group_pins = pinctrl_generic_get_group_pins,
+ .pin_dbg_show = starfive_pin_dbg_show,
+ .dt_node_to_map = starfive_dt_node_to_map,
+ .dt_free_map = starfive_dt_free_map,
+};
+
+
+static int starfive_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
+ unsigned group)
+{
+ struct starfive_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct starfive_pinctrl_soc_info *info = ipctl->info;
+ struct function_desc *func;
+ struct group_desc *grp;
+ struct starfive_pin *pin;
+ unsigned int npins;
+ int i, err;
+
+ grp = pinctrl_generic_get_group(pctldev, group);
+ if (!grp)
+ return -EINVAL;
+
+ func = pinmux_generic_get_function(pctldev, selector);
+ if (!func)
+ return -EINVAL;
+
+ npins = grp->num_pins;
+
+ dev_dbg(ipctl->dev, "enable function %s group %s\n",
+ func->name, grp->name);
+
+ for (i = 0; i < npins; i++) {
+ pin = &((struct starfive_pin *)(grp->data))[i];
+ if(info->starfive_pmx_set_one_pin_mux){
+ err = info->starfive_pmx_set_one_pin_mux(ipctl, pin);
+ if (err)
+ return err;
+ }
+ }
+
+ return 0;
+}
+
+struct pinmux_ops starfive_pmx_ops = {
+ .get_functions_count = pinmux_generic_get_function_count,
+ .get_function_name = pinmux_generic_get_function_name,
+ .get_function_groups = pinmux_generic_get_function_groups,
+ .set_mux = starfive_pmx_set,
+};
+
+
+static int starfive_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *config)
+{
+ struct starfive_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct starfive_pinctrl_soc_info *info = ipctl->info;
+
+ if(info->starfive_pinconf_get)
+ return info->starfive_pinconf_get(pctldev, pin_id, config);
+
+ return 0;
+}
+
+static int starfive_pinconf_set(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs)
+{
+ struct starfive_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct starfive_pinctrl_soc_info *info = ipctl->info;
+
+
+ if(info->starfive_pinconf_set)
+ return info->starfive_pinconf_set(pctldev, pin_id,
+ configs, num_configs);
+ return 0;
+}
+
+static void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned pin_id)
+{
+ struct starfive_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
+ const struct starfive_pinctrl_soc_info *info = ipctl->info;
+ const struct starfive_pin_reg *pin_reg;
+ unsigned long config;
+ int ret;
+
+ pin_reg = &ipctl->pin_regs[pin_id];
+ if (pin_reg->io_conf_reg == -1) {
+ seq_puts(s, "N/A");
+ return;
+ }
+
+ ret = starfive_pinconf_get(pctldev, pin_id, &config);
+ if (ret)
+ return;
+ seq_printf(s, "0x%lx", config);
+}
+
+static void starfive_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned group)
+{
+ struct group_desc *grp;
+ unsigned long config;
+ const char *name;
+ int i, ret;
+
+ if (group >= pctldev->num_groups)
+ return;
+
+ seq_puts(s, "\n");
+ grp = pinctrl_generic_get_group(pctldev, group);
+ if (!grp)
+ return;
+
+ for (i = 0; i < grp->num_pins; i++) {
+ struct starfive_pin *pin = &((struct starfive_pin *)(grp->data))[i];
+
+ name = pin_get_name(pctldev, pin->pin);
+ ret = starfive_pinconf_get(pctldev, pin->pin, &config);
+ if (ret)
+ return;
+ seq_printf(s, " %s: 0x%lx\n", name, config);
+ }
+}
+
+static const struct pinconf_ops starfive_pinconf_ops = {
+ .pin_config_get = starfive_pinconf_get,
+ .pin_config_set = starfive_pinconf_set,
+ .pin_config_dbg_show = starfive_pinconf_dbg_show,
+ .pin_config_group_dbg_show = starfive_pinconf_group_dbg_show,
+};
+
+
+static void starfive_pinctrl_parse_pin_config(struct starfive_pinctrl *ipctl,
+ unsigned int *pins_id, struct starfive_pin *pin_data,
+ const __be32 *list_p,
+ struct device_node *np)
+{
+ const struct starfive_pinctrl_soc_info *info = ipctl->info;
+ struct starfive_pin_reg *pin_reg;
+ const __be32 *list = list_p;
+ const __be32 *list_din;
+ int size_din;
+ int psize, pin_size;
+ u32 value;
+ int i;
+
+ *pins_id = be32_to_cpu(*list++);
+ pin_data->pin = *pins_id;
+
+ pin_reg = &ipctl->pin_regs[*pins_id];
+ pin_reg->io_conf_reg = *pins_id;
+
+ if (!of_property_read_u32(np, "sf,pin-ioconfig", &value)) {
+ pin_data->pin_config.io_config = value;
+ }
+
+ if (!of_property_read_u32(np, "sf,pinmux", &value)) {
+ pin_data->pin_config.pinmux_func = value & PINMUX_GPIO_FUNC_MASK;
+
+ if(pin_data->pin_config.pinmux_func == PINMUX_GPIO_FUNC){
+ pin_data->pin_config.gpio_num = value & PINMUX_GPIO_NUM_MASK;
+
+ if (!of_property_read_u32(np, "sf,pin-gpio-dout", &value)) {
+ pin_data->pin_config.gpio_dout = value;
+ pin_reg->gpo_dout_reg = info->dout_reg_base + \
+ (pin_data->pin_config.gpio_num * info->dout_reg_offset);
+ }
+
+ if (!of_property_read_u32(np, "sf,pin-gpio-doen", &value)) {
+ pin_data->pin_config.gpio_doen = value;
+ pin_reg->gpo_doen_reg = info->doen_reg_base + \
+ (pin_data->pin_config.gpio_num * info->doen_reg_offset);
+ }
+
+ list_din = of_get_property(np, "sf,pin-gpio-din", &size_din);
+ if (list_din) {
+ if (!size_din || size_din % pin_size) {
+ dev_err(ipctl->dev,
+ "Invalid sf,pin-gpio-din or pins property in node %pOF\n", np);
+ return;
+ }
+
+ pin_data->pin_config.gpio_din_num = size_din / pin_size;
+ pin_data->pin_config.gpio_din_reg = devm_kcalloc(ipctl->dev,
+ pin_data->pin_config.gpio_din_num, sizeof(s32),
+ GFP_KERNEL);
+
+ for(i = 0; i < pin_data->pin_config.gpio_din_num; i++){
+ value = be32_to_cpu(*list_din++);
+ pin_data->pin_config.gpio_din_reg[i] = info->din_reg_base + \
+ value*info->din_reg_offset;
+ }
+ }
+ }
+ }
+ return;
+}
+
+
+static int starfive_pinctrl_parse_groups(struct device_node *np,
+ struct group_desc *grp,
+ struct starfive_pinctrl *ipctl,
+ u32 index)
+{
+ const struct starfive_pinctrl_soc_info *info = ipctl->info;
+ struct starfive_pin *pin_data;
+ struct device_node *child;
+ int *pins_id;
+ int psize, pin_size;
+ int size = 0;
+ int offset = 0;
+ const __be32 *list;
+ int j, child_num_pins;
+
+ pin_size = STARFIVE_PINS_SIZE;
+
+ /* Initialise group */
+ grp->name = np->name;
+
+ for_each_child_of_node(np, child) {
+ list = of_get_property(child, "sf,pins", &psize);
+ if (!list) {
+ dev_err(ipctl->dev,
+ "no sf,pins and pins property in node %pOF\n", np);
+ return -EINVAL;
+ }
+ size += psize;
+ }
+
+ if (!size || size % pin_size) {
+ dev_err(ipctl->dev,
+ "Invalid sf,pins or pins property in node %pOF\n", np);
+ return -EINVAL;
+ }
+
+ grp->num_pins = size / pin_size;
+ grp->data = devm_kcalloc(ipctl->dev,
+ grp->num_pins, sizeof(struct starfive_pin),
+ GFP_KERNEL);
+ grp->pins = devm_kcalloc(ipctl->dev,
+ grp->num_pins, sizeof(int),
+ GFP_KERNEL);
+ if (!grp->pins || !grp->data)
+ return -ENOMEM;
+
+ for_each_child_of_node(np, child) {
+ list = of_get_property(child, "sf,pins", &psize);
+ if (!list) {
+ dev_err(ipctl->dev,
+ "no sf,pins and pins property in node %pOF\n", np);
+ return -EINVAL;
+ }
+
+ child_num_pins = psize / pin_size;
+ printk(KERN_ERR "%s L.%d child_num_pins = %d ", __func__, __LINE__,child_num_pins);
+
+ for (j = 0; j < child_num_pins; j++) {
+
+ printk(KERN_ERR "j = %d offset = %d j + offset = %d", j, offset, j + offset);
+
+ pin_data = &((struct starfive_pin *)(grp->data))[j + offset];
+ pins_id = &(grp->pins)[j + offset];
+
+ if (info->flags & STARFIVE_USE_SCU)
+ info->starfive_pinctrl_parse_pin(ipctl, pins_id,
+ pin_data, list, child);
+ else
+ starfive_pinctrl_parse_pin_config(ipctl, pins_id,
+ pin_data, list, child);
+ *list++;
+ }
+ offset += j;
+ }
+
+ return 0;
+}
+
+static int starfive_pinctrl_parse_functions(struct device_node *np,
+ struct starfive_pinctrl *ipctl,
+ u32 index)
+{
+ struct pinctrl_dev *pctl = ipctl->pctl;
+ struct device_node *child;
+ struct function_desc *func;
+ struct group_desc *grp;
+ u32 i = 0;
+
+ func = pinmux_generic_get_function(pctl, index);
+ if (!func)
+ return -EINVAL;
+
+ /* Initialise function */
+ func->name = np->name;
+ func->num_group_names = of_get_child_count(np);
+ if (func->num_group_names == 0) {
+ dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
+ return -EINVAL;
+ }
+ func->group_names = devm_kcalloc(ipctl->dev, func->num_group_names,
+ sizeof(char *), GFP_KERNEL);
+ if (!func->group_names)
+ return -ENOMEM;
+
+ for_each_child_of_node(np, child) {
+ func->group_names[i] = child->name;
+ grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc),
+ GFP_KERNEL);
+ if (!grp) {
+ of_node_put(child);
+ return -ENOMEM;
+ }
+
+ mutex_lock(&ipctl->mutex);
+ radix_tree_insert(&pctl->pin_group_tree,
+ ipctl->group_index++, grp);
+ mutex_unlock(&ipctl->mutex);
+
+ starfive_pinctrl_parse_groups(child, grp, ipctl, i++);
+ }
+
+ return 0;
+}
+
+static int starfive_pinctrl_probe_dt(struct platform_device *pdev,
+ struct starfive_pinctrl *ipctl)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device_node *child;
+ struct pinctrl_dev *pctl = ipctl->pctl;
+ u32 nfuncs = 1;
+ u32 i = 0;
+ int ret;
+
+ if (!np)
+ return -ENODEV;
+
+ for (i = 0; i < nfuncs; i++) {
+ struct function_desc *function;
+
+ function = devm_kzalloc(&pdev->dev, sizeof(*function),
+ GFP_KERNEL);
+ if (!function)
+ return -ENOMEM;
+
+ mutex_lock(&ipctl->mutex);
+ radix_tree_insert(&pctl->pin_function_tree, i, function);
+ mutex_unlock(&ipctl->mutex);
+ }
+
+ pctl->num_functions = nfuncs;
+ ipctl->group_index = 0;
+ pctl->num_groups = of_get_child_count(np);
+ starfive_pinctrl_parse_functions(np, ipctl, 0);
+
+ return 0;
+}
+
+int starfive_pinctrl_probe(struct platform_device *pdev,
+ const struct starfive_pinctrl_soc_info *info)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *dev_np = pdev->dev.of_node;
+ struct pinctrl_desc *starfive_pinctrl_desc;
+ struct device_node *np;
+ struct starfive_pinctrl *ipctl;
+ struct pinctrl_pin_desc *pins;
+ int ret, i,irq;
+ u32 value;
+
+
+ if (!info || !info->pins || !info->npins) {
+ dev_err(&pdev->dev, "wrong pinctrl info\n");
+ return -EINVAL;
+ }
+
+ /* Create state holders etc for this driver */
+ ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
+ if (!ipctl)
+ return -ENOMEM;
+
+ ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins,
+ sizeof(*ipctl->pin_regs),
+ GFP_KERNEL);
+ if (!ipctl->pin_regs)
+ return -ENOMEM;
+
+ for (i = 0; i < info->npins; i++) {
+ ipctl->pin_regs[i].io_conf_reg = -1;
+ ipctl->pin_regs[i].gpo_dout_reg = -1;
+ ipctl->pin_regs[i].gpo_doen_reg = -1;
+ ipctl->pin_regs[i].func_sel_reg = -1;
+ ipctl->pin_regs[i].syscon_reg = -1;
+ }
+
+ ipctl->padctl_base = devm_platform_ioremap_resource_byname(pdev, "padctl");
+ if (IS_ERR(ipctl->padctl_base))
+ return PTR_ERR(ipctl->padctl_base);
+
+ ipctl->gpio_base = devm_platform_ioremap_resource_byname(pdev, "gpio");
+ if (IS_ERR(ipctl->gpio_base))
+ {
+ dev_err(&pdev->dev,
+ "[dts]no gpio base config\n");
+ }
+
+ if (info->starfive_iopad_sel_func) {
+ ret = info->starfive_iopad_sel_func(ipctl,value);
+ if (ret)
+ return ret;
+ }
+
+ starfive_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*starfive_pinctrl_desc),
+ GFP_KERNEL);
+ if (!starfive_pinctrl_desc)
+ return -ENOMEM;
+
+ raw_spin_lock_init(&ipctl->lock);
+
+ starfive_pinctrl_desc->name = dev_name(&pdev->dev);
+ starfive_pinctrl_desc->pins = info->pins;
+ starfive_pinctrl_desc->npins = info->npins;
+ starfive_pinctrl_desc->pctlops = &starfive_pctrl_ops;
+ starfive_pinctrl_desc->pmxops = &starfive_pmx_ops;
+ starfive_pinctrl_desc->confops = &starfive_pinconf_ops;
+ starfive_pinctrl_desc->owner = THIS_MODULE;
+
+ mutex_init(&ipctl->mutex);
+
+ ipctl->info = info;
+ ipctl->dev = &pdev->dev;
+ platform_set_drvdata(pdev, ipctl);
+ ipctl->gc.parent = dev;
+ ret = devm_pinctrl_register_and_init(&pdev->dev,
+ starfive_pinctrl_desc, ipctl,
+ &ipctl->pctl);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "could not register starfive pinctrl driver\n");
+ return ret;
+ }
+
+ ret = starfive_pinctrl_probe_dt(pdev, ipctl);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "fail to probe dt properties\n");
+ return ret;
+ }
+
+ ret = pinctrl_enable(ipctl->pctl);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "pin controller failed to start\n");
+ return ret;
+ }
+
+ if(info->starfive_gpio_register){
+ ret = info->starfive_gpio_register(pdev,ipctl);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "starfive_gpio_register failed to register\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(starfive_pinctrl_probe);
+
+static int __maybe_unused starfive_pinctrl_suspend(struct device *dev)
+{
+ struct starfive_pinctrl *ipctl = dev_get_drvdata(dev);
+
+ return pinctrl_force_sleep(ipctl->pctl);
+}
+
+static int __maybe_unused starfive_pinctrl_resume(struct device *dev)
+{
+ struct starfive_pinctrl *ipctl = dev_get_drvdata(dev);
+
+ return pinctrl_force_default(ipctl->pctl);
+}
+
+const struct dev_pm_ops starfive_pinctrl_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(starfive_pinctrl_suspend,
+ starfive_pinctrl_resume)
+};
+EXPORT_SYMBOL_GPL(starfive_pinctrl_pm_ops);
+MODULE_AUTHOR("jenny.zhang <jenny.zhang@starfivetech.com>");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+/**
+ ******************************************************************************
+ * @file pinctrl-starfive.h
+ * @author StarFive Technology
+ * @version V1.0
+ * @date 11/30/2021
+ * @brief
+ ******************************************************************************
+ * @copy
+ *
+ * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>© COPYRIGHT 20120 Shanghai StarFive Technology Co., Ltd. </center></h2>
+ */
+
+#ifndef __DRIVERS_PINCTRL_STARFIVE_H
+#define __DRIVERS_PINCTRL_STARFIVE_H
+
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinmux.h>
+
+#define MAX_GPIO 64
+
+/************vic7100 reg**************/
+#define STARFIVE_PINS_SIZE 4
+//pinmux
+#define PINMUX_GPIO_NUM_MASK 0xFF
+#define PINMUX_GPIO_FUNC_MASK 0xF00
+#define PINMUX_GPIO_FUNC 0x100
+/************vic7100 reg**************/
+
+#define STARFIVE_USE_SCU BIT(0)
+
+struct platform_device;
+
+extern struct pinmux_ops starfive_pmx_ops;
+extern const struct dev_pm_ops starfive_pinctrl_pm_ops;
+
+struct starfive_pin_config {
+ unsigned long io_config;
+ u32 pinmux_func;
+ u32 gpio_num;
+ u32 gpio_dout;
+ u32 gpio_doen;
+ u32 gpio_din_num;
+ s32 *gpio_din_reg;
+ s32 syscon;
+};
+
+struct starfive_pin {
+ unsigned int pin;
+ struct starfive_pin_config pin_config;
+};
+
+struct starfive_pin_reg {
+ s32 io_conf_reg;
+ s32 gpo_dout_reg;
+ s32 gpo_doen_reg;
+ s32 func_sel_reg;
+ s32 func_sel_shift;
+ s32 func_sel_mask;
+ s32 syscon_reg;
+};
+
+struct starfive_iopad_sel_func_inf {
+ unsigned int padctl_gpio_base;
+ unsigned int padctl_gpio0;
+};
+
+
+struct starfive_pinctrl {
+ struct device *dev;
+ struct pinctrl_dev *pctl;
+ void __iomem *padctl_base;
+ void __iomem *gpio_base;
+ unsigned int padctl_gpio_base;
+ unsigned int padctl_gpio0;
+ const struct starfive_pinctrl_soc_info *info;
+ struct starfive_pin_reg *pin_regs;
+ unsigned int group_index;
+
+ struct mutex mutex;
+ raw_spinlock_t lock;
+
+ struct gpio_chip gc;
+ struct pinctrl_gpio_range gpios;
+ unsigned long enabled;
+ unsigned trigger[MAX_GPIO];
+};
+
+
+struct starfive_pinctrl_soc_info {
+ const struct pinctrl_pin_desc *pins;
+ unsigned int npins;
+ unsigned int flags;
+
+ /*gpio dout/doen/din register*/
+ unsigned int dout_reg_base;
+ unsigned int dout_reg_offset;
+ unsigned int doen_reg_base;
+ unsigned int doen_reg_offset;
+ unsigned int din_reg_base;
+ unsigned int din_reg_offset;
+
+ /* sel-function */
+ int (*starfive_iopad_sel_func)(struct starfive_pinctrl *ipctl,
+ unsigned int func_id);
+ /* generic pinconf */
+ int (*starfive_pinconf_get)(struct pinctrl_dev *pctldev, unsigned int pin_id,
+ unsigned long *config);
+ int (*starfive_pinconf_set)(struct pinctrl_dev *pctldev,
+ unsigned pin_id, unsigned long *configs,
+ unsigned num_configs);
+
+ int (*starfive_pmx_set_one_pin_mux)(struct starfive_pinctrl *ipctl,
+ struct starfive_pin *pin);
+ int (*starfive_gpio_register)(struct platform_device *pdev,
+ struct starfive_pinctrl *ipctl);
+ void (*starfive_pinctrl_parse_pin)(struct starfive_pinctrl *ipctl,
+ unsigned int *pins_id, struct starfive_pin *pin_data,
+ const __be32 *list_p,
+ struct device_node *np);
+};
+
+
+#define STARFIVE_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
+
+int starfive_pinctrl_probe(struct platform_device *pdev,
+ const struct starfive_pinctrl_soc_info *info);
+
+#endif /* __DRIVERS_PINCTRL_STARFIVE_H */
--- /dev/null
+#ifndef _DT_BINDINGS_PINCTRL_STARFIVE_H
+#define _DT_BINDINGS_PINCTRL_STARFIVE_H
+
+/************************aon_iomux***************************/
+//aon_iomux pin
+#define PAD_TESTEN 0
+#define PAD_RGPIO0 1
+#define PAD_RGPIO1 2
+#define PAD_RGPIO2 3
+#define PAD_RGPIO3 4
+#define PAD_RSTN 5
+#define PAD_GMAC0_MDC 6
+#define PAD_GMAC0_MDIO 7
+#define PAD_GMAC0_RXD0 8
+#define PAD_GMAC0_RXD1 9
+#define PAD_GMAC0_RXD2 10
+#define PAD_GMAC0_RXD3 11
+#define PAD_GMAC0_RXDV 12
+#define PAD_GMAC0_RXC 13
+#define PAD_GMAC0_TXD0 14
+#define PAD_GMAC0_TXD1 15
+#define PAD_GMAC0_TXD2 16
+#define PAD_GMAC0_TXD3 17
+#define PAD_GMAC0_TXEN 18
+#define PAD_GMAC0_TXC 19
+
+//<fmux_idx.h>
+//aon_iomux dout
+#define GPO_AON_IOMUX_U0_AON_CRG_CLK_32K_OUT 2
+#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_4 3
+#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_5 4
+#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_6 5
+#define GPO_AON_IOMUX_U0_PWM_8CH_PTC_PWM_7 6
+#define GPO_AON_IOMUX_U0_SYS_CRG_CLK_GCLK0 7
+#define GPO_AON_IOMUX_U0_SYS_CRG_CLK_GCLK1 8
+#define GPO_AON_IOMUX_U0_SYS_CRG_CLK_GCLK2 9
+//aon_iomux doen
+#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_4 2
+#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_5 3
+#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_6 4
+#define GPEN_AON_IOMUX_U0_PWM_8CH_PTC_OE_N_7 5
+//aon_iomux gin
+#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_0 0
+#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_1 1
+#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_2 2
+#define GPI_AON_IOMUX_U0_PMU_IO_EVENT_STUB_GPIO_WAKEUP_3 3
+
+
+//===============================GPIO_OUT_SELECT=======================================
+// gpio_out config:
+// every define below is a couple of signal and signal idx
+// use macros in corresponding syscfg_macro.h and idx defined below to config gpio_out
+//e.g. SET_AON_IOMUX_GPO[gpio_num]_DOUT_CFG([signal])
+//e.g. SET_AON_IOMUX_GPO0_DOUT_CFG(__LOW)
+//=====================================================================================
+#define __LOW 0
+#define __HIGH 1
+#define U0_AON_CRG_CLK_32K_OUT 2
+#define U0_PWM_8CH_PTC_PWM_4 3
+#define U0_PWM_8CH_PTC_PWM_5 4
+#define U0_PWM_8CH_PTC_PWM_6 5
+#define U0_PWM_8CH_PTC_PWM_7 6
+#define U0_SYS_CRG_CLK_GCLK0 7
+#define U0_SYS_CRG_CLK_GCLK1 8
+#define U0_SYS_CRG_CLK_GCLK2 9
+
+//===============================GPIO_OEN_SELECT=======================================
+// gpio_oen config:
+// every define below is a couple of signal and signal idx
+// use macros in corresponding syscfg_macro.h and idx defined below to config gpio_oen
+//e.g. SET_AON_IOMUX_GPO[gpio_num]_DOEN_CFG([signal])
+//e.g. SET_AON_IOMUX_GPO0_DOEN_CFG(__LOW)
+//=====================================================================================
+#define __LOW 0
+#define __HIGH 1
+#define U0_PWM_8CH_PTC_OE_N_4 2
+#define U0_PWM_8CH_PTC_OE_N_5 3
+#define U0_PWM_8CH_PTC_OE_N_6 4
+#define U0_PWM_8CH_PTC_OE_N_7 5
+
+
+//aon_iomux gmac0 syscon
+#define AON_IOMUX_CFG__SAIF__SYSCFG_88_ADDR (0x58U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_92_ADDR (0x5cU)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_96_ADDR (0x60U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_100_ADDR (0x64U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_104_ADDR (0x68U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_108_ADDR (0x6cU)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_112_ADDR (0x70U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_116_ADDR (0x74U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_120_ADDR (0x78U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_124_ADDR (0x7cU)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_128_ADDR (0x80U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_132_ADDR (0x84U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_136_ADDR (0x88U)
+#define AON_IOMUX_CFG__SAIF__SYSCFG_140_ADDR (0x8cU)
+
+#define PADCFG_PAD_GMAC0_MDC_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_88_ADDR
+#define PADCFG_PAD_GMAC0_MDIO_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_92_ADDR
+#define PADCFG_PAD_GMAC0_RXD0_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_96_ADDR
+#define PADCFG_PAD_GMAC0_RXD1_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_100_ADDR
+#define PADCFG_PAD_GMAC0_RXD2_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_104_ADDR
+#define PADCFG_PAD_GMAC0_RXD3_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_108_ADDR
+#define PADCFG_PAD_GMAC0_RXDV_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_112_ADDR
+#define PADCFG_PAD_GMAC0_RXC_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_116_ADDR
+#define PADCFG_PAD_GMAC0_TXD0_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_120_ADDR
+#define PADCFG_PAD_GMAC0_TXD1_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_124_ADDR
+#define PADCFG_PAD_GMAC0_TXD2_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_128_ADDR
+#define PADCFG_PAD_GMAC0_TXD3_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_132_ADDR
+#define PADCFG_PAD_GMAC0_TXEN_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_136_ADDR
+#define PADCFG_PAD_GMAC0_TXC_SYSCON AON_IOMUX_CFG__SAIF__SYSCFG_140_ADDR
+
+//aon_iomux func sel
+#define AON_IOMUX_CFGSAIF__SYSCFG_144_ADDR (0x90U)
+#define PAD_GMAC0_RXC_FUNC_SEL_SHIFT 0x0U
+#define PAD_GMAC0_RXC_FUNC_SEL_MASK 0x3U
+
+#define PAD_GMAC0_RXC_FUNC_SEL AON_IOMUX_CFGSAIF__SYSCFG_144_ADDR PAD_GMAC0_RXC_FUNC_SEL_SHIFT PAD_GMAC0_RXC_FUNC_SEL_MASK
+/************************aon_iomux***************************/
+
+/************************sys_iomux***************************/
+//sys_iomux pin
+#define PAD_GPIO0 0
+#define PAD_GPIO1 1
+#define PAD_GPIO2 2
+#define PAD_GPIO3 3
+#define PAD_GPIO4 4
+#define PAD_GPIO5 5
+#define PAD_GPIO6 6
+#define PAD_GPIO7 7
+#define PAD_GPIO8 8
+#define PAD_GPIO9 9
+#define PAD_GPIO10 10
+#define PAD_GPIO11 11
+#define PAD_GPIO12 12
+#define PAD_GPIO13 13
+#define PAD_GPIO14 14
+#define PAD_GPIO15 15
+#define PAD_GPIO16 16
+#define PAD_GPIO17 17
+#define PAD_GPIO18 18
+#define PAD_GPIO19 19
+#define PAD_GPIO20 20
+#define PAD_GPIO21 21
+#define PAD_GPIO22 22
+#define PAD_GPIO23 23
+#define PAD_GPIO24 24
+#define PAD_GPIO25 25
+#define PAD_GPIO26 26
+#define PAD_GPIO27 27
+#define PAD_GPIO28 28
+#define PAD_GPIO29 29
+#define PAD_GPIO30 30
+#define PAD_GPIO31 31
+#define PAD_GPIO32 32
+#define PAD_GPIO33 33
+#define PAD_GPIO34 34
+#define PAD_GPIO35 35
+#define PAD_GPIO36 36
+#define PAD_GPIO37 37
+#define PAD_GPIO38 38
+#define PAD_GPIO39 39
+#define PAD_GPIO40 40
+#define PAD_GPIO41 41
+#define PAD_GPIO42 42
+#define PAD_GPIO43 43
+#define PAD_GPIO44 44
+#define PAD_GPIO45 45
+#define PAD_GPIO46 46
+#define PAD_GPIO47 47
+#define PAD_GPIO48 48
+#define PAD_GPIO49 49
+#define PAD_GPIO50 50
+#define PAD_GPIO51 51
+#define PAD_GPIO52 52
+#define PAD_GPIO53 53
+#define PAD_GPIO54 54
+#define PAD_GPIO55 55
+#define PAD_GPIO56 56
+#define PAD_GPIO57 57
+#define PAD_GPIO58 58
+#define PAD_GPIO59 59
+#define PAD_GPIO60 60
+#define PAD_GPIO61 61
+#define PAD_GPIO62 62
+#define PAD_GPIO63 63
+#define PAD_SD0_CLK 64
+#define PAD_SD0_CMD 65
+#define PAD_SD0_DATA0 66
+#define PAD_SD0_DATA1 67
+#define PAD_SD0_DATA2 68
+#define PAD_SD0_DATA3 69
+#define PAD_SD0_DATA4 70
+#define PAD_SD0_DATA5 71
+#define PAD_SD0_DATA6 72
+#define PAD_SD0_DATA7 73
+#define PAD_SD0_STRB 74
+#define PAD_GMAC1_MDC 75
+#define PAD_GMAC1_MDIO 76
+#define PAD_GMAC1_RXD0 77
+#define PAD_GMAC1_RXD1 78
+#define PAD_GMAC1_RXD2 79
+#define PAD_GMAC1_RXD3 80
+#define PAD_GMAC1_RXDV 81
+#define PAD_GMAC1_RXC 82
+#define PAD_GMAC1_TXD0 83
+#define PAD_GMAC1_TXD1 84
+#define PAD_GMAC1_TXD2 85
+#define PAD_GMAC1_TXD3 86
+#define PAD_GMAC1_TXEN 87
+#define PAD_GMAC1_TXC 88
+#define PAD_QSPI_SCLK 89
+#define PAD_QSPI_CSn0 90
+#define PAD_QSPI_DATA0 91
+#define PAD_QSPI_DATA1 92
+#define PAD_QSPI_DATA2 93
+#define PAD_QSPI_DATA3 94
+
+
+//<fmux_idx.h>
+//oen and out idx is for chosen, in idx is for reg offset
+#define GPO_SYS_IOMUX_U0_WAVE511_O_UART_TXSOUT 2
+#define GPO_SYS_IOMUX_U0_CAN_CTRL_STBY 3
+#define GPO_SYS_IOMUX_U0_CAN_CTRL_TST_NEXT_BIT 4
+#define GPO_SYS_IOMUX_U0_CAN_CTRL_TST_SAMPLE_POINT 5
+#define GPO_SYS_IOMUX_U0_CAN_CTRL_TXD 6
+#define GPO_SYS_IOMUX_U0_CDN_USB_DRIVE_VBUS_IO 7
+#define GPO_SYS_IOMUX_U0_CDNS_QSPI_CSN1 8
+#define GPO_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFO 9
+#define GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OUT 10
+#define GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OUT 11
+#define GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OUT 12
+#define GPO_SYS_IOMUX_U0_DSKIT_WDT_WDOGRES 13
+#define GPO_SYS_IOMUX_U0_DW_I2C_IC_CLK_OUT_A 14
+#define GPO_SYS_IOMUX_U0_DW_I2C_IC_DATA_OUT_A 15
+#define GPO_SYS_IOMUX_U0_DW_SDIO_BACK_END_POWER 16
+#define GPO_SYS_IOMUX_U0_DW_SDIO_CARD_POWER_EN 17
+#define GPO_SYS_IOMUX_U0_DW_SDIO_CCMD_OD_PULLUP_EN_N 18
+#define GPO_SYS_IOMUX_U0_DW_SDIO_RST_N 19
+#define GPO_SYS_IOMUX_U0_DW_UART_SOUT 20
+#define GPO_SYS_IOMUX_U0_HIFI4_JTDO 21
+#define GPO_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO 22
+#define GPO_SYS_IOMUX_U0_PDM_4MIC_DMIC_MCLK 23
+#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_0 24
+#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_1 25
+#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_2 26
+#define GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_3 27
+#define GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_LEFT_OUTPUT 28
+#define GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_RIGHT_OUTPUT 29
+#define GPO_SYS_IOMUX_U0_SSP_SPI_SSPCLKOUT 30
+#define GPO_SYS_IOMUX_U0_SSP_SPI_SSPFSSOUT 31
+#define GPO_SYS_IOMUX_U0_SSP_SPI_SSPTXD 32
+#define GPO_SYS_IOMUX_U0_SYS_CRG_CLK_GMAC_PHY 33
+#define GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_MST 34
+#define GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_MST 35
+#define GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_MST 36
+#define GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_MST 37
+#define GPO_SYS_IOMUX_U0_SYS_CRG_MCLK_OUT 38
+#define GPO_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_MST 39
+#define GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCOUT 40
+#define GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_TXD 41
+#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_0 42
+#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_1 43
+#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_2 44
+#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_3 45
+#define GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TREF 46
+#define GPO_SYS_IOMUX_U1_CAN_CTRL_STBY 47
+#define GPO_SYS_IOMUX_U1_CAN_CTRL_TST_NEXT_BIT 48
+#define GPO_SYS_IOMUX_U1_CAN_CTRL_TST_SAMPLE_POINT 49
+#define GPO_SYS_IOMUX_U1_CAN_CTRL_TXD 50
+#define GPO_SYS_IOMUX_U1_DW_I2C_IC_CLK_OUT_A 51
+#define GPO_SYS_IOMUX_U1_DW_I2C_IC_DATA_OUT_A 52
+#define GPO_SYS_IOMUX_U1_DW_SDIO_BACK_END_POWER 53
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CARD_POWER_EN 54
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CCLK_OUT 55
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OD_PULLUP_EN_N 56
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT 57
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_0 58
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_1 59
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_2 60
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_3 61
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_4 62
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_5 63
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_6 64
+#define GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_7 65
+#define GPO_SYS_IOMUX_U1_DW_SDIO_RST_N 66
+#define GPO_SYS_IOMUX_U1_DW_UART_RTS_N 67
+#define GPO_SYS_IOMUX_U1_DW_UART_SOUT 68
+#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO0 69
+#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO1 70
+#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO2 71
+#define GPO_SYS_IOMUX_U1_I2STX_4CH_SDO3 72
+#define GPO_SYS_IOMUX_U1_SSP_SPI_SSPCLKOUT 73
+#define GPO_SYS_IOMUX_U1_SSP_SPI_SSPFSSOUT 74
+#define GPO_SYS_IOMUX_U1_SSP_SPI_SSPTXD 75
+#define GPO_SYS_IOMUX_U2_DW_I2C_IC_CLK_OUT_A 76
+#define GPO_SYS_IOMUX_U2_DW_I2C_IC_DATA_OUT_A 77
+#define GPO_SYS_IOMUX_U2_DW_UART_RTS_N 78
+#define GPO_SYS_IOMUX_U2_DW_UART_SOUT 79
+#define GPO_SYS_IOMUX_U2_SSP_SPI_SSPCLKOUT 80
+#define GPO_SYS_IOMUX_U2_SSP_SPI_SSPFSSOUT 81
+#define GPO_SYS_IOMUX_U2_SSP_SPI_SSPTXD 82
+#define GPO_SYS_IOMUX_U3_DW_I2C_IC_CLK_OUT_A 83
+#define GPO_SYS_IOMUX_U3_DW_I2C_IC_DATA_OUT_A 84
+#define GPO_SYS_IOMUX_U3_DW_UART_SOUT 85
+#define GPO_SYS_IOMUX_U3_SSP_SPI_SSPCLKOUT 86
+#define GPO_SYS_IOMUX_U3_SSP_SPI_SSPFSSOUT 87
+#define GPO_SYS_IOMUX_U3_SSP_SPI_SSPTXD 88
+#define GPO_SYS_IOMUX_U4_DW_I2C_IC_CLK_OUT_A 89
+#define GPO_SYS_IOMUX_U4_DW_I2C_IC_DATA_OUT_A 90
+#define GPO_SYS_IOMUX_U4_DW_UART_RTS_N 91
+#define GPO_SYS_IOMUX_U4_DW_UART_SOUT 92
+#define GPO_SYS_IOMUX_U4_SSP_SPI_SSPCLKOUT 93
+#define GPO_SYS_IOMUX_U4_SSP_SPI_SSPFSSOUT 94
+#define GPO_SYS_IOMUX_U4_SSP_SPI_SSPTXD 95
+#define GPO_SYS_IOMUX_U5_DW_I2C_IC_CLK_OUT_A 96
+#define GPO_SYS_IOMUX_U5_DW_I2C_IC_DATA_OUT_A 97
+#define GPO_SYS_IOMUX_U5_DW_UART_RTS_N 98
+#define GPO_SYS_IOMUX_U5_DW_UART_SOUT 99
+#define GPO_SYS_IOMUX_U5_SSP_SPI_SSPCLKOUT 100
+#define GPO_SYS_IOMUX_U5_SSP_SPI_SSPFSSOUT 101
+#define GPO_SYS_IOMUX_U5_SSP_SPI_SSPTXD 102
+#define GPO_SYS_IOMUX_U6_DW_I2C_IC_CLK_OUT_A 103
+#define GPO_SYS_IOMUX_U6_DW_I2C_IC_DATA_OUT_A 104
+#define GPO_SYS_IOMUX_U6_SSP_SPI_SSPCLKOUT 105
+#define GPO_SYS_IOMUX_U6_SSP_SPI_SSPFSSOUT 106
+#define GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD 107
+
+#define GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OEN 2
+#define GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OEN 3
+#define GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OEN 4
+#define GPEN_SYS_IOMUX_U0_DW_I2C_IC_CLK_OE 5
+#define GPEN_SYS_IOMUX_U0_DW_I2C_IC_DATA_OE 6
+#define GPEN_SYS_IOMUX_U0_HIFI4_JTDOEN 7
+#define GPEN_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO_OE 8
+#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_0 9
+#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_1 10
+#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_2 11
+#define GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_3 12
+#define GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPCTLOE 13
+#define GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPOE 14
+#define GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_SYNCOE 15
+#define GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_TXDOE 16
+#define GPEN_SYS_IOMUX_U1_DW_I2C_IC_CLK_OE 17
+#define GPEN_SYS_IOMUX_U1_DW_I2C_IC_DATA_OE 18
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT_EN 19
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_0 20
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_1 21
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_2 22
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_3 23
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_4 24
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_5 25
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_6 26
+#define GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_7 27
+#define GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPCTLOE 28
+#define GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPOE 29
+#define GPEN_SYS_IOMUX_U2_DW_I2C_IC_CLK_OE 30
+#define GPEN_SYS_IOMUX_U2_DW_I2C_IC_DATA_OE 31
+#define GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPCTLOE 32
+#define GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPOE 33
+#define GPEN_SYS_IOMUX_U3_DW_I2C_IC_CLK_OE 34
+#define GPEN_SYS_IOMUX_U3_DW_I2C_IC_DATA_OE 35
+#define GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPCTLOE 36
+#define GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPOE 37
+#define GPEN_SYS_IOMUX_U4_DW_I2C_IC_CLK_OE 38
+#define GPEN_SYS_IOMUX_U4_DW_I2C_IC_DATA_OE 39
+#define GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPCTLOE 40
+#define GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPOE 41
+#define GPEN_SYS_IOMUX_U5_DW_I2C_IC_CLK_OE 42
+#define GPEN_SYS_IOMUX_U5_DW_I2C_IC_DATA_OE 43
+#define GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPCTLOE 44
+#define GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPOE 45
+#define GPEN_SYS_IOMUX_U6_DW_I2C_IC_CLK_OE 46
+#define GPEN_SYS_IOMUX_U6_DW_I2C_IC_DATA_OE 47
+#define GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPCTLOE 48
+#define GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE 49
+
+#define GPI_SYS_IOMUX_U0_WAVE511_I_UART_RXSIN 0
+#define GPI_SYS_IOMUX_U0_CAN_CTRL_RXD 1
+#define GPI_SYS_IOMUX_U0_CDN_USB_OVERCURRENT_N_IO 2
+#define GPI_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFI 3
+#define GPI_SYS_IOMUX_U0_CLKRST_SRC_BYPASS_JTAG_TRSTN 4
+#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN 5
+#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN 6
+#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN 7
+#define GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD 8
+#define GPI_SYS_IOMUX_U0_DW_I2C_IC_CLK_IN_A 9
+#define GPI_SYS_IOMUX_U0_DW_I2C_IC_DATA_IN_A 10
+#define GPI_SYS_IOMUX_U0_DW_SDIO_CARD_DETECT_N 11
+#define GPI_SYS_IOMUX_U0_DW_SDIO_CARD_INT_N 12
+#define GPI_SYS_IOMUX_U0_DW_SDIO_CARD_WRITE_PRT 13
+#define GPI_SYS_IOMUX_U0_DW_UART_SIN 14
+#define GPI_SYS_IOMUX_U0_HIFI4_JTCK 15
+#define GPI_SYS_IOMUX_U0_HIFI4_JTDI 16
+#define GPI_SYS_IOMUX_U0_HIFI4_JTMS 17
+#define GPI_SYS_IOMUX_U0_HIFI4_JTRSTN 18
+#define GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDI 19
+#define GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TMS 20
+#define GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC0_DIN 21
+#define GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC1_DIN 22
+#define GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0 23
+#define GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1 24
+#define GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2 25
+#define GPI_SYS_IOMUX_U0_SSP_SPI_SSPCLKIN 26
+#define GPI_SYS_IOMUX_U0_SSP_SPI_SSPFSSIN 27
+#define GPI_SYS_IOMUX_U0_SSP_SPI_SSPRXD 28
+#define GPI_SYS_IOMUX_U0_SYS_CRG_CLK_JTAG_TCK 29
+#define GPI_SYS_IOMUX_U0_SYS_CRG_EXT_MCLK 30
+#define GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_SLV 31
+#define GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_SLV 32
+#define GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_SLV 33
+#define GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_SLV 34
+#define GPI_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_SLV 35
+#define GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_RXD 36
+#define GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCIN 37
+#define GPI_SYS_IOMUX_U1_CAN_CTRL_RXD 38
+#define GPI_SYS_IOMUX_U1_DW_I2C_IC_CLK_IN_A 39
+#define GPI_SYS_IOMUX_U1_DW_I2C_IC_DATA_IN_A 40
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CARD_DETECT_N 41
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CARD_INT_N 42
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CARD_WRITE_PRT 43
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CCMD_IN 44
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_0 45
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_1 46
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_2 47
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_3 48
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_4 49
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_5 50
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_6 51
+#define GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_7 52
+#define GPI_SYS_IOMUX_U1_DW_SDIO_DATA_STROBE 53
+#define GPI_SYS_IOMUX_U1_DW_UART_CTS_N 54
+#define GPI_SYS_IOMUX_U1_DW_UART_SIN 55
+#define GPI_SYS_IOMUX_U1_SSP_SPI_SSPCLKIN 56
+#define GPI_SYS_IOMUX_U1_SSP_SPI_SSPFSSIN 57
+#define GPI_SYS_IOMUX_U1_SSP_SPI_SSPRXD 58
+#define GPI_SYS_IOMUX_U2_DW_I2C_IC_CLK_IN_A 59
+#define GPI_SYS_IOMUX_U2_DW_I2C_IC_DATA_IN_A 60
+#define GPI_SYS_IOMUX_U2_DW_UART_CTS_N 61
+#define GPI_SYS_IOMUX_U2_DW_UART_SIN 62
+#define GPI_SYS_IOMUX_U2_SSP_SPI_SSPCLKIN 63
+#define GPI_SYS_IOMUX_U2_SSP_SPI_SSPFSSIN 64
+#define GPI_SYS_IOMUX_U2_SSP_SPI_SSPRXD 65
+#define GPI_SYS_IOMUX_U3_DW_I2C_IC_CLK_IN_A 66
+#define GPI_SYS_IOMUX_U3_DW_I2C_IC_DATA_IN_A 67
+#define GPI_SYS_IOMUX_U3_DW_UART_SIN 68
+#define GPI_SYS_IOMUX_U3_SSP_SPI_SSPCLKIN 69
+#define GPI_SYS_IOMUX_U3_SSP_SPI_SSPFSSIN 70
+#define GPI_SYS_IOMUX_U3_SSP_SPI_SSPRXD 71
+#define GPI_SYS_IOMUX_U4_DW_I2C_IC_CLK_IN_A 72
+#define GPI_SYS_IOMUX_U4_DW_I2C_IC_DATA_IN_A 73
+#define GPI_SYS_IOMUX_U4_DW_UART_CTS_N 74
+#define GPI_SYS_IOMUX_U4_DW_UART_SIN 75
+#define GPI_SYS_IOMUX_U4_SSP_SPI_SSPCLKIN 76
+#define GPI_SYS_IOMUX_U4_SSP_SPI_SSPFSSIN 77
+#define GPI_SYS_IOMUX_U4_SSP_SPI_SSPRXD 78
+#define GPI_SYS_IOMUX_U5_DW_I2C_IC_CLK_IN_A 79
+#define GPI_SYS_IOMUX_U5_DW_I2C_IC_DATA_IN_A 80
+#define GPI_SYS_IOMUX_U5_DW_UART_CTS_N 81
+#define GPI_SYS_IOMUX_U5_DW_UART_SIN 82
+#define GPI_SYS_IOMUX_U5_SSP_SPI_SSPCLKIN 83
+#define GPI_SYS_IOMUX_U5_SSP_SPI_SSPFSSIN 84
+#define GPI_SYS_IOMUX_U5_SSP_SPI_SSPRXD 85
+#define GPI_SYS_IOMUX_U6_DW_I2C_IC_CLK_IN_A 86
+#define GPI_SYS_IOMUX_U6_DW_I2C_IC_DATA_IN_A 87
+#define GPI_SYS_IOMUX_U6_SSP_SPI_SSPCLKIN 88
+#define GPI_SYS_IOMUX_U6_SSP_SPI_SSPFSSIN 89
+#define GPI_SYS_IOMUX_U6_SSP_SPI_SSPRXD 90
+
+
+
+//gpo(n)_dout signal pool
+#define GPO_LOW 0
+#define GPO_HIGH 1
+#define GPO_CAN0_CTRL_STBY GPO_SYS_IOMUX_U0_CAN_CTRL_STBY
+#define GPO_CAN0_CTRL_TST_NEXT_BIT GPO_SYS_IOMUX_U0_CAN_CTRL_TST_NEXT_BIT
+#define GPO_CAN0_CTRL_TST_SAMPLE_POINT GPO_SYS_IOMUX_U0_CAN_CTRL_TST_SAMPLE_POINT
+#define GPO_CAN0_CTRL_TXD GPO_SYS_IOMUX_U0_CAN_CTRL_TXD
+#define GPO_CAN1_CTRL_STBY GPO_SYS_IOMUX_U1_CAN_CTRL_STBY
+#define GPO_CAN1_CTRL_TST_NEXT_BIT GPO_SYS_IOMUX_U1_CAN_CTRL_TST_NEXT_BIT
+#define GPO_CAN1_CTRL_TST_SAMPLE_POINT GPO_SYS_IOMUX_U1_CAN_CTRL_TST_SAMPLE_POINT
+#define GPO_CAN1_CTRL_TXD GPO_SYS_IOMUX_U1_CAN_CTRL_TXD
+#define GPO_CRG0_MCLK_OUT GPO_SYS_IOMUX_U0_SYS_CRG_MCLK_OUT
+#define GPO_GMAC0_CLK_PHY GPO_SYS_IOMUX_U0_SYS_CRG_CLK_GMAC_PHY
+#define GPO_HDMI0_CEC_SDA_OUT GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OUT
+#define GPO_HDMI0_DDC_SCL_OUT GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OUT
+#define GPO_HDMI0_DDC_SDA_OUT GPO_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OUT
+#define GPO_I2C0_IC_CLK_OUT_A GPO_SYS_IOMUX_U0_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C0_IC_DATA_OUT_A GPO_SYS_IOMUX_U0_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C1_IC_CLK_OUT_A GPO_SYS_IOMUX_U1_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C1_IC_DATA_OUT_A GPO_SYS_IOMUX_U1_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C2_IC_CLK_OUT_A GPO_SYS_IOMUX_U2_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C2_IC_DATA_OUT_A GPO_SYS_IOMUX_U2_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C3_IC_CLK_OUT_A GPO_SYS_IOMUX_U3_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C3_IC_DATA_OUT_A GPO_SYS_IOMUX_U3_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C4_IC_CLK_OUT_A GPO_SYS_IOMUX_U4_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C4_IC_DATA_OUT_A GPO_SYS_IOMUX_U4_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C5_IC_CLK_OUT_A GPO_SYS_IOMUX_U5_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C5_IC_DATA_OUT_A GPO_SYS_IOMUX_U5_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2C6_IC_CLK_OUT_A GPO_SYS_IOMUX_U6_DW_I2C_IC_CLK_OUT_A
+#define GPO_I2C6_IC_DATA_OUT_A GPO_SYS_IOMUX_U6_DW_I2C_IC_DATA_OUT_A
+#define GPO_I2SRX0_BCLK_MST GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_MST
+#define GPO_I2SRX0_LRCK_MST GPO_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_MST
+#define GPO_I2STX_4CH1_SDO0 GPO_SYS_IOMUX_U1_I2STX_4CH_SDO0
+#define GPO_I2STX_4CH1_SDO1 GPO_SYS_IOMUX_U1_I2STX_4CH_SDO1
+#define GPO_I2STX_4CH1_SDO2 GPO_SYS_IOMUX_U1_I2STX_4CH_SDO2
+#define GPO_I2STX_4CH1_SDO3 GPO_SYS_IOMUX_U1_I2STX_4CH_SDO3
+#define GPO_I2STX0_BCLK_MST GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_MST
+#define GPO_I2STX0_LRCK_MST GPO_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_MST
+#define GPO_JTAG_CPU_CERTIFICATION_TDO GPO_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO
+#define GPO_JTAG_DSP_TDO GPO_SYS_IOMUX_U0_HIFI4_JTDO
+#define GPO_PDM_4MIC0_DMIC_MCLK GPO_SYS_IOMUX_U0_PDM_4MIC_DMIC_MCLK
+#define GPO_PTC0_PWM_0 GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_0
+#define GPO_PTC0_PWM_1 GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_1
+#define GPO_PTC0_PWM_2 GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_2
+#define GPO_PTC0_PWM_3 GPO_SYS_IOMUX_U0_PWM_8CH_PTC_PWM_3
+#define GPO_PWMDAC0_LEFT_OUTPUT GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_LEFT_OUTPUT
+#define GPO_PWMDAC0_RIGHT_OUTPUT GPO_SYS_IOMUX_U0_PWMDAC_PWMDAC_RIGHT_OUTPUT
+#define GPO_QSPI0_CSN1 GPO_SYS_IOMUX_U0_CDNS_QSPI_CSN1
+#define GPO_SDIO0_BACK_END_POWER GPO_SYS_IOMUX_U0_DW_SDIO_BACK_END_POWER
+#define GPO_SDIO0_CARD_POWER_EN GPO_SYS_IOMUX_U0_DW_SDIO_CARD_POWER_EN
+#define GPO_SDIO0_CCMD_OD_PULLUP_EN_N GPO_SYS_IOMUX_U0_DW_SDIO_CCMD_OD_PULLUP_EN_N
+#define GPO_SDIO0_RST_N GPO_SYS_IOMUX_U0_DW_SDIO_RST_N
+#define GPO_SDIO1_BACK_END_POWER GPO_SYS_IOMUX_U1_DW_SDIO_BACK_END_POWER
+#define GPO_SDIO1_CARD_POWER_EN GPO_SYS_IOMUX_U1_DW_SDIO_CARD_POWER_EN
+#define GPO_SDIO1_CCLK_OUT GPO_SYS_IOMUX_U1_DW_SDIO_CCLK_OUT
+#define GPO_SDIO1_CCMD_OD_PULLUP_EN_N GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OD_PULLUP_EN_N
+#define GPO_SDIO1_CCMD_OUT GPO_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT
+#define GPO_SDIO1_CDATA_OUT_0 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_0
+#define GPO_SDIO1_CDATA_OUT_1 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_1
+#define GPO_SDIO1_CDATA_OUT_2 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_2
+#define GPO_SDIO1_CDATA_OUT_3 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_3
+#define GPO_SDIO1_CDATA_OUT_4 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_4
+#define GPO_SDIO1_CDATA_OUT_5 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_5
+#define GPO_SDIO1_CDATA_OUT_6 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_6
+#define GPO_SDIO1_CDATA_OUT_7 GPO_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_7
+#define GPO_SDIO1_RST_N GPO_SYS_IOMUX_U1_DW_SDIO_RST_N
+#define GPO_SPDIF0_SPDIFO GPO_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFO
+#define GPO_SPI0_SSPCLKOUT GPO_SYS_IOMUX_U0_SSP_SPI_SSPCLKOUT
+#define GPO_SPI0_SSPFSSOUT GPO_SYS_IOMUX_U0_SSP_SPI_SSPFSSOUT
+#define GPO_SPI0_SSPTXD GPO_SYS_IOMUX_U0_SSP_SPI_SSPTXD
+#define GPO_SPI1_SSPCLKOUT GPO_SYS_IOMUX_U1_SSP_SPI_SSPCLKOUT
+#define GPO_SPI1_SSPFSSOUT GPO_SYS_IOMUX_U1_SSP_SPI_SSPFSSOUT
+#define GPO_SPI1_SSPTXD GPO_SYS_IOMUX_U1_SSP_SPI_SSPTXD
+#define GPO_SPI2_SSPCLKOUT GPO_SYS_IOMUX_U2_SSP_SPI_SSPCLKOUT
+#define GPO_SPI2_SSPFSSOUT GPO_SYS_IOMUX_U2_SSP_SPI_SSPFSSOUT
+#define GPO_SPI2_SSPTXD GPO_SYS_IOMUX_U2_SSP_SPI_SSPTXD
+#define GPO_SPI3_SSPCLKOUT GPO_SYS_IOMUX_U3_SSP_SPI_SSPCLKOUT
+#define GPO_SPI3_SSPFSSOUT GPO_SYS_IOMUX_U3_SSP_SPI_SSPFSSOUT
+#define GPO_SPI3_SSPTXD GPO_SYS_IOMUX_U3_SSP_SPI_SSPTXD
+#define GPO_SPI4_SSPCLKOUT GPO_SYS_IOMUX_U4_SSP_SPI_SSPCLKOUT
+#define GPO_SPI4_SSPFSSOUT GPO_SYS_IOMUX_U4_SSP_SPI_SSPFSSOUT
+#define GPO_SPI4_SSPTXD GPO_SYS_IOMUX_U4_SSP_SPI_SSPTXD
+#define GPO_SPI5_SSPCLKOUT GPO_SYS_IOMUX_U5_SSP_SPI_SSPCLKOUT
+#define GPO_SPI5_SSPFSSOUT GPO_SYS_IOMUX_U5_SSP_SPI_SSPFSSOUT
+#define GPO_SPI5_SSPTXD GPO_SYS_IOMUX_U5_SSP_SPI_SSPTXD
+#define GPO_SPI6_SSPCLKOUT GPO_SYS_IOMUX_U6_SSP_SPI_SSPCLKOUT
+#define GPO_SPI6_SSPFSSOUT GPO_SYS_IOMUX_U6_SSP_SPI_SSPFSSOUT
+#define GPO_SPI6_SSPTXD GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD
+#define GPO_TDM0_CLK_MST GPO_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_MST
+#define GPO_TDM0_PCM_SYNCOUT GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCOUT
+#define GPO_TDM0_PCM_TXD GPO_SYS_IOMUX_U0_TDM16SLOT_PCM_TXD
+#define GPO_U7MC_TRACE0_TDATA_0 GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_0
+#define GPO_U7MC_TRACE0_TDATA_1 GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_1
+#define GPO_U7MC_TRACE0_TDATA_2 GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_2
+#define GPO_U7MC_TRACE0_TDATA_3 GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TDATA_3
+#define GPO_U7MC_TRACE0_TREF GPO_SYS_IOMUX_U0_U7MC_SFT7110_TRACE_COM_PIB_TREF
+#define GPO_UART0_SOUT GPO_SYS_IOMUX_U0_DW_UART_SOUT
+#define GPO_UART1_RTS_N GPO_SYS_IOMUX_U1_DW_UART_RTS_N
+#define GPO_UART1_SOUT GPO_SYS_IOMUX_U1_DW_UART_SOUT
+#define GPO_UART2_RTS_N GPO_SYS_IOMUX_U2_DW_UART_RTS_N
+#define GPO_UART2_SOUT GPO_SYS_IOMUX_U2_DW_UART_SOUT
+#define GPO_UART3_SOUT GPO_SYS_IOMUX_U3_DW_UART_SOUT
+#define GPO_UART4_RTS_N GPO_SYS_IOMUX_U4_DW_UART_RTS_N
+#define GPO_UART4_SOUT GPO_SYS_IOMUX_U4_DW_UART_SOUT
+#define GPO_UART5_RTS_N GPO_SYS_IOMUX_U5_DW_UART_RTS_N
+#define GPO_UART5_SOUT GPO_SYS_IOMUX_U5_DW_UART_SOUT
+#define GPO_USB0_DRIVE_VBUS_IO GPO_SYS_IOMUX_U0_CDN_USB_DRIVE_VBUS_IO
+#define GPO_WAVE511_0_O_UART_TXSOUT GPO_SYS_IOMUX_U0_WAVE511_O_UART_TXSOUT
+#define GPO_WDT0_WDOGRES GPO_SYS_IOMUX_U0_DSKIT_WDT_WDOGRES
+#define GPO_NONE GPO_SYS_IOMUX_U6_SSP_SPI_SSPTXD + 1
+
+
+//gpo(n)_doen signal pool
+#define OEN_LOW 0
+#define OEN_HIGH 1
+#define OEN_HDMI0_CEC_SDA_OEN GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_OEN
+#define OEN_HDMI0_DDC_SCL_OEN GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_OEN
+#define OEN_HDMI0_DDC_SDA_OEN GPEN_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_OEN
+#define OEN_I2C0_IC_CLK_OE GPEN_SYS_IOMUX_U0_DW_I2C_IC_CLK_OE
+#define OEN_I2C0_IC_DATA_OE GPEN_SYS_IOMUX_U0_DW_I2C_IC_DATA_OE
+#define OEN_I2C1_IC_CLK_OE GPEN_SYS_IOMUX_U1_DW_I2C_IC_CLK_OE
+#define OEN_I2C1_IC_DATA_OE GPEN_SYS_IOMUX_U1_DW_I2C_IC_DATA_OE
+#define OEN_I2C2_IC_CLK_OE GPEN_SYS_IOMUX_U2_DW_I2C_IC_CLK_OE
+#define OEN_I2C2_IC_DATA_OE GPEN_SYS_IOMUX_U2_DW_I2C_IC_DATA_OE
+#define OEN_I2C3_IC_CLK_OE GPEN_SYS_IOMUX_U3_DW_I2C_IC_CLK_OE
+#define OEN_I2C3_IC_DATA_OE GPEN_SYS_IOMUX_U3_DW_I2C_IC_DATA_OE
+#define OEN_I2C4_IC_CLK_OE GPEN_SYS_IOMUX_U4_DW_I2C_IC_CLK_OE
+#define OEN_I2C4_IC_DATA_OE GPEN_SYS_IOMUX_U4_DW_I2C_IC_DATA_OE
+#define OEN_I2C5_IC_CLK_OE GPEN_SYS_IOMUX_U5_DW_I2C_IC_CLK_OE
+#define OEN_I2C5_IC_DATA_OE GPEN_SYS_IOMUX_U5_DW_I2C_IC_DATA_OE
+#define OEN_I2C6_IC_CLK_OE GPEN_SYS_IOMUX_U6_DW_I2C_IC_CLK_OE
+#define OEN_I2C6_IC_DATA_OE GPEN_SYS_IOMUX_U6_DW_I2C_IC_DATA_OE
+#define OEN_JTAG_CPU_CERTIFICATION_TDO_OE GPEN_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDO_OE
+#define OEN_JTAG_DSP_TDO_OEN GPEN_SYS_IOMUX_U0_HIFI4_JTDOEN
+#define OEN_PTC0_PWM_0_OE_N GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_0
+#define OEN_PTC0_PWM_1_OE_N GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_1
+#define OEN_PTC0_PWM_2_OE_N GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_2
+#define OEN_PTC0_PWM_3_OE_N GPEN_SYS_IOMUX_U0_PWM_8CH_PTC_OE_N_3
+#define OEN_SDIO1_CCMD_OUT_EN GPEN_SYS_IOMUX_U1_DW_SDIO_CCMD_OUT_EN
+#define OEN_SDIO1_CDATA_OUT_EN_0 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_0
+#define OEN_SDIO1_CDATA_OUT_EN_1 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_1
+#define OEN_SDIO1_CDATA_OUT_EN_2 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_2
+#define OEN_SDIO1_CDATA_OUT_EN_3 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_3
+#define OEN_SDIO1_CDATA_OUT_EN_4 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_4
+#define OEN_SDIO1_CDATA_OUT_EN_5 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_5
+#define OEN_SDIO1_CDATA_OUT_EN_6 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_6
+#define OEN_SDIO1_CDATA_OUT_EN_7 GPEN_SYS_IOMUX_U1_DW_SDIO_CDATA_OUT_EN_7
+#define OEN_SPI0_NSSPCTLOE GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPCTLOE
+#define OEN_SPI0_NSSPOE GPEN_SYS_IOMUX_U0_SSP_SPI_NSSPOE
+#define OEN_SPI1_NSSPCTLOE GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPCTLOE
+#define OEN_SPI1_NSSPOE GPEN_SYS_IOMUX_U1_SSP_SPI_NSSPOE
+#define OEN_SPI2_NSSPCTLOE GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPCTLOE
+#define OEN_SPI2_NSSPOE GPEN_SYS_IOMUX_U2_SSP_SPI_NSSPOE
+#define OEN_SPI3_NSSPCTLOE GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPCTLOE
+#define OEN_SPI3_NSSPOE GPEN_SYS_IOMUX_U3_SSP_SPI_NSSPOE
+#define OEN_SPI4_NSSPCTLOE GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPCTLOE
+#define OEN_SPI4_NSSPOE GPEN_SYS_IOMUX_U4_SSP_SPI_NSSPOE
+#define OEN_SPI5_NSSPCTLOE GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPCTLOE
+#define OEN_SPI5_NSSPOE GPEN_SYS_IOMUX_U5_SSP_SPI_NSSPOE
+#define OEN_SPI6_NSSPCTLOE GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPCTLOE
+#define OEN_SPI6_NSSPOE GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE
+#define OEN_TDM0_NPCM_SYNCOE GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_SYNCOE
+#define OEN_TDM0_NPCM_TXDOE GPEN_SYS_IOMUX_U0_TDM16SLOT_NPCM_TXDOE
+#define OEN_NONE GPEN_SYS_IOMUX_U6_SSP_SPI_NSSPOE + 1
+
+//sys_iomux gpi din
+#define GPI_CAN0_CTRL_RXD GPI_SYS_IOMUX_U0_CAN_CTRL_RXD
+#define GPI_CAN1_CTRL_RXD GPI_SYS_IOMUX_U1_CAN_CTRL_RXD
+#define GPI_CRG0_EXT_MCLK GPI_SYS_IOMUX_U0_SYS_CRG_EXT_MCLK
+#define GPI_HDMI0_CEC_SDA_IN GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_CEC_SDA_IN
+#define GPI_HDMI0_DDC_SCL_IN GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SCL_IN
+#define GPI_HDMI0_DDC_SDA_IN GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_DDC_SDA_IN
+#define GPI_HDMI0_HPD GPI_SYS_IOMUX_U0_DOM_VOUT_TOP_U0_HDMI_TX_PIN_HPD
+#define GPI_I2C0_IC_CLK_IN_A GPI_SYS_IOMUX_U0_DW_I2C_IC_CLK_IN_A
+#define GPI_I2C0_IC_DATA_IN_A GPI_SYS_IOMUX_U0_DW_I2C_IC_DATA_IN_A
+#define GPI_I2C1_IC_CLK_IN_A GPI_SYS_IOMUX_U1_DW_I2C_IC_CLK_IN_A
+#define GPI_I2C1_IC_DATA_IN_A GPI_SYS_IOMUX_U1_DW_I2C_IC_DATA_IN_A
+#define GPI_I2C2_IC_CLK_IN_A GPI_SYS_IOMUX_U2_DW_I2C_IC_CLK_IN_A
+#define GPI_I2C2_IC_DATA_IN_A GPI_SYS_IOMUX_U2_DW_I2C_IC_DATA_IN_A
+#define GPI_I2C3_IC_CLK_IN_A GPI_SYS_IOMUX_U3_DW_I2C_IC_CLK_IN_A
+#define GPI_I2C3_IC_DATA_IN_A GPI_SYS_IOMUX_U3_DW_I2C_IC_DATA_IN_A
+#define GPI_I2C4_IC_CLK_IN_A GPI_SYS_IOMUX_U4_DW_I2C_IC_CLK_IN_A
+#define GPI_I2C4_IC_DATA_IN_A GPI_SYS_IOMUX_U4_DW_I2C_IC_DATA_IN_A
+#define GPI_I2C5_IC_CLK_IN_A GPI_SYS_IOMUX_U5_DW_I2C_IC_CLK_IN_A
+#define GPI_I2C5_IC_DATA_IN_A GPI_SYS_IOMUX_U5_DW_I2C_IC_DATA_IN_A
+#define GPI_I2C6_IC_CLK_IN_A GPI_SYS_IOMUX_U6_DW_I2C_IC_CLK_IN_A
+#define GPI_I2C6_IC_DATA_IN_A GPI_SYS_IOMUX_U6_DW_I2C_IC_DATA_IN_A
+#define GPI_I2SRX0_BCLK_SLV GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_BCLK_SLV
+#define GPI_I2SRX0_EXT_SDIN0 GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN0
+#define GPI_I2SRX0_EXT_SDIN1 GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN1
+#define GPI_I2SRX0_EXT_SDIN2 GPI_SYS_IOMUX_U0_SAIF_AUDIO_SDIN_MUX_I2SRX_EXT_SDIN2
+#define GPI_I2SRX0_LRCK_SLV GPI_SYS_IOMUX_U0_SYS_CRG_I2SRX_LRCK_SLV
+#define GPI_I2STX0_BCLK_SLV GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_BCLK_SLV
+#define GPI_I2STX0_LRCK_SLV GPI_SYS_IOMUX_U0_SYS_CRG_I2STX_LRCK_SLV
+#define GPI_JTAG_CPU_CERTIFICATION_BYPASS_TRSTN GPI_SYS_IOMUX_U0_CLKRST_SRC_BYPASS_JTAG_TRSTN
+#define GPI_JTAG_CPU_CERTIFICATION_TCK GPI_SYS_IOMUX_U0_SYS_CRG_CLK_JTAG_TCK
+#define GPI_JTAG_CPU_CERTIFICATION_TDI GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TDI
+#define GPI_JTAG_CPU_CERTIFICATION_TMS GPI_SYS_IOMUX_U0_JTAG_CERTIFICATION_TMS
+#define GPI_JTAG_DSP_TCK GPI_SYS_IOMUX_U0_HIFI4_JTCK
+#define GPI_JTAG_DSP_TDI GPI_SYS_IOMUX_U0_HIFI4_JTDI
+#define GPI_JTAG_DSP_TMS GPI_SYS_IOMUX_U0_HIFI4_JTMS
+#define GPI_JTAG_DSP_TRST_N GPI_SYS_IOMUX_U0_HIFI4_JTRSTN
+#define GPI_PDM_4MIC0_DMIC0_DIN GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC0_DIN
+#define GPI_PDM_4MIC0_DMIC1_DIN GPI_SYS_IOMUX_U0_PDM_4MIC_DMIC1_DIN
+#define GPI_SDIO0_CARD_DETECT_N GPI_SYS_IOMUX_U0_DW_SDIO_CARD_DETECT_N
+#define GPI_SDIO0_CARD_INT_N GPI_SYS_IOMUX_U0_DW_SDIO_CARD_INT_N
+#define GPI_SDIO0_CARD_WRITE_PRT GPI_SYS_IOMUX_U0_DW_SDIO_CARD_WRITE_PRT
+#define GPI_SDIO1_CARD_DETECT_N GPI_SYS_IOMUX_U1_DW_SDIO_CARD_DETECT_N
+#define GPI_SDIO1_CARD_INT_N GPI_SYS_IOMUX_U1_DW_SDIO_CARD_INT_N
+#define GPI_SDIO1_CARD_WRITE_PRT GPI_SYS_IOMUX_U1_DW_SDIO_CARD_WRITE_PRT
+#define GPI_SDIO1_CCMD_IN GPI_SYS_IOMUX_U1_DW_SDIO_CCMD_IN
+#define GPI_SDIO1_CDATA_IN_0 GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_0
+#define GPI_SDIO1_CDATA_IN_1 GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_1
+#define GPI_SDIO1_CDATA_IN_2 GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_2
+#define GPI_SDIO1_CDATA_IN_3 GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_3
+#define GPI_SDIO1_CDATA_IN_4 GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_4
+#define GPI_SDIO1_CDATA_IN_5 GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_5
+#define GPI_SDIO1_CDATA_IN_6 GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_6
+#define GPI_SDIO1_CDATA_IN_7 GPI_SYS_IOMUX_U1_DW_SDIO_CDATA_IN_7
+#define GPI_SDIO1_DATA_STROBE GPI_SYS_IOMUX_U1_DW_SDIO_DATA_STROBE
+#define GPI_SPDIF0_SPDIFI GPI_SYS_IOMUX_U0_CDNS_SPDIF_SPDIFI
+#define GPI_SPI0_SSPCLKIN GPI_SYS_IOMUX_U0_SSP_SPI_SSPCLKIN
+#define GPI_SPI0_SSPFSSIN GPI_SYS_IOMUX_U0_SSP_SPI_SSPFSSIN
+#define GPI_SPI0_SSPRXD GPI_SYS_IOMUX_U0_SSP_SPI_SSPRXD
+#define GPI_SPI1_SSPCLKIN GPI_SYS_IOMUX_U1_SSP_SPI_SSPCLKIN
+#define GPI_SPI1_SSPFSSIN GPI_SYS_IOMUX_U1_SSP_SPI_SSPFSSIN
+#define GPI_SPI1_SSPRXD GPI_SYS_IOMUX_U1_SSP_SPI_SSPRXD
+#define GPI_SPI2_SSPCLKIN GPI_SYS_IOMUX_U2_SSP_SPI_SSPCLKIN
+#define GPI_SPI2_SSPFSSIN GPI_SYS_IOMUX_U2_SSP_SPI_SSPFSSIN
+#define GPI_SPI2_SSPRXD GPI_SYS_IOMUX_U2_SSP_SPI_SSPRXD
+#define GPI_SPI3_SSPCLKIN GPI_SYS_IOMUX_U3_SSP_SPI_SSPCLKIN
+#define GPI_SPI3_SSPFSSIN GPI_SYS_IOMUX_U3_SSP_SPI_SSPFSSIN
+#define GPI_SPI3_SSPRXD GPI_SYS_IOMUX_U3_SSP_SPI_SSPRXD
+#define GPI_SPI4_SSPCLKIN GPI_SYS_IOMUX_U4_SSP_SPI_SSPCLKIN
+#define GPI_SPI4_SSPFSSIN GPI_SYS_IOMUX_U4_SSP_SPI_SSPFSSIN
+#define GPI_SPI4_SSPRXD GPI_SYS_IOMUX_U4_SSP_SPI_SSPRXD
+#define GPI_SPI5_SSPCLKIN GPI_SYS_IOMUX_U5_SSP_SPI_SSPCLKIN
+#define GPI_SPI5_SSPFSSIN GPI_SYS_IOMUX_U5_SSP_SPI_SSPFSSIN
+#define GPI_SPI5_SSPRXD GPI_SYS_IOMUX_U5_SSP_SPI_SSPRXD
+#define GPI_SPI6_SSPCLKIN GPI_SYS_IOMUX_U6_SSP_SPI_SSPCLKIN
+#define GPI_SPI6_SSPFSSIN GPI_SYS_IOMUX_U6_SSP_SPI_SSPFSSIN
+#define GPI_SPI6_SSPRXD GPI_SYS_IOMUX_U6_SSP_SPI_SSPRXD
+#define GPI_TDM0_CLK_SLV GPI_SYS_IOMUX_U0_SYS_CRG_TDM_CLK_SLV
+#define GPI_TDM0_PCM_RXD GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_RXD
+#define GPI_TDM0_PCM_SYNCIN GPI_SYS_IOMUX_U0_TDM16SLOT_PCM_SYNCIN
+#define GPI_UART0_SIN GPI_SYS_IOMUX_U0_DW_UART_SIN
+#define GPI_UART1_CTS_N GPI_SYS_IOMUX_U1_DW_UART_CTS_N
+#define GPI_UART1_SIN GPI_SYS_IOMUX_U1_DW_UART_SIN
+#define GPI_UART2_CTS_N GPI_SYS_IOMUX_U2_DW_UART_CTS_N
+#define GPI_UART2_SIN GPI_SYS_IOMUX_U2_DW_UART_SIN
+#define GPI_UART3_SIN GPI_SYS_IOMUX_U3_DW_UART_SIN
+#define GPI_UART4_CTS_N GPI_SYS_IOMUX_U4_DW_UART_CTS_N
+#define GPI_UART4_SIN GPI_SYS_IOMUX_U4_DW_UART_SIN
+#define GPI_UART5_CTS_N GPI_SYS_IOMUX_U5_DW_UART_CTS_N
+#define GPI_UART5_SIN GPI_SYS_IOMUX_U5_DW_UART_SIN
+#define GPI_USB0_OVERCURRENT_N_IO GPI_SYS_IOMUX_U0_CDN_USB_OVERCURRENT_N_IO
+#define GPI_WAVE511_0_I_UART_RXSIN GPI_SYS_IOMUX_U0_WAVE511_I_UART_RXSIN
+#define GPI_NONE GPI_SYS_IOMUX_U6_SSP_SPI_SSPRXD
+
+//sys_iomux syscon
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_588_ADDR (0x24cU)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_592_ADDR (0x250U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_596_ADDR (0x254U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_600_ADDR (0x258U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_604_ADDR (0x25cU)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_608_ADDR (0x260U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_612_ADDR (0x264U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_616_ADDR (0x268U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_620_ADDR (0x26cU)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_624_ADDR (0x270U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_628_ADDR (0x274U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_632_ADDR (0x278U)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_636_ADDR (0x27cU)
+#define SYS_IOMUX_CFG__SAIF__SYSCFG_640_ADDR (0x280U)
+
+#define PADCFG_PAD_GMAC1_MDC_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_588_ADDR
+#define PADCFG_PAD_GMAC1_MDIO_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_592_ADDR
+#define PADCFG_PAD_GMAC1_RXD0_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_596_ADDR
+#define PADCFG_PAD_GMAC1_RXD1_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_600_ADDR
+#define PADCFG_PAD_GMAC1_RXD2_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_604_ADDR
+#define PADCFG_PAD_GMAC1_RXD3_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_608_ADDR
+#define PADCFG_PAD_GMAC1_RXDV_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_612_ADDR
+#define PADCFG_PAD_GMAC1_RXC_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_616_ADDR
+#define PADCFG_PAD_GMAC1_TXD0_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_620_ADDR
+#define PADCFG_PAD_GMAC1_TXD1_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_624_ADDR
+#define PADCFG_PAD_GMAC1_TXD2_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_628_ADDR
+#define PADCFG_PAD_GMAC1_TXD3_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_632_ADDR
+#define PADCFG_PAD_GMAC1_TXEN_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_636_ADDR
+#define PADCFG_PAD_GMAC1_TXC_SYSCON SYS_IOMUX_CFG__SAIF__SYSCFG_640_ADDR
+
+
+//sys_iomux func sel setting
+#define SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR (0x29cU)
+#define PAD_GMAC1_RXC_FUNC_SEL_WIDTH 0x2U
+#define PAD_GMAC1_RXC_FUNC_SEL_SHIFT 0x0U
+#define PAD_GMAC1_RXC_FUNC_SEL_MASK 0x3U
+#define PAD_GPIO10_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO10_FUNC_SEL_SHIFT 0x2U
+#define PAD_GPIO10_FUNC_SEL_MASK 0x1CU
+#define PAD_GPIO11_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO11_FUNC_SEL_SHIFT 0x5U
+#define PAD_GPIO11_FUNC_SEL_MASK 0xE0U
+#define PAD_GPIO12_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO12_FUNC_SEL_SHIFT 0x8U
+#define PAD_GPIO12_FUNC_SEL_MASK 0x700U
+#define PAD_GPIO13_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO13_FUNC_SEL_SHIFT 0xBU
+#define PAD_GPIO13_FUNC_SEL_MASK 0x3800U
+#define PAD_GPIO14_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO14_FUNC_SEL_SHIFT 0xEU
+#define PAD_GPIO14_FUNC_SEL_MASK 0x1C000U
+#define PAD_GPIO15_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO15_FUNC_SEL_SHIFT 0x11U
+#define PAD_GPIO15_FUNC_SEL_MASK 0xE0000U
+#define PAD_GPIO16_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO16_FUNC_SEL_SHIFT 0x14U
+#define PAD_GPIO16_FUNC_SEL_MASK 0x700000U
+#define PAD_GPIO17_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO17_FUNC_SEL_SHIFT 0x17U
+#define PAD_GPIO17_FUNC_SEL_MASK 0x3800000U
+#define PAD_GPIO18_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO18_FUNC_SEL_SHIFT 0x1AU
+#define PAD_GPIO18_FUNC_SEL_MASK 0x1C000000U
+#define PAD_GPIO19_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO19_FUNC_SEL_SHIFT 0x1DU
+#define PAD_GPIO19_FUNC_SEL_MASK 0xE0000000U
+#define SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR (0x2a0U)
+#define PAD_GPIO20_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO20_FUNC_SEL_SHIFT 0x0U
+#define PAD_GPIO20_FUNC_SEL_MASK 0x7U
+#define PAD_GPIO21_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO21_FUNC_SEL_SHIFT 0x3U
+#define PAD_GPIO21_FUNC_SEL_MASK 0x38U
+#define PAD_GPIO22_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO22_FUNC_SEL_SHIFT 0x6U
+#define PAD_GPIO22_FUNC_SEL_MASK 0x1C0U
+#define PAD_GPIO23_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO23_FUNC_SEL_SHIFT 0x9U
+#define PAD_GPIO23_FUNC_SEL_MASK 0xE00U
+#define PAD_GPIO24_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO24_FUNC_SEL_SHIFT 0xCU
+#define PAD_GPIO24_FUNC_SEL_MASK 0x7000U
+#define PAD_GPIO25_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO25_FUNC_SEL_SHIFT 0xFU
+#define PAD_GPIO25_FUNC_SEL_MASK 0x38000U
+#define PAD_GPIO26_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO26_FUNC_SEL_SHIFT 0x12U
+#define PAD_GPIO26_FUNC_SEL_MASK 0x1C0000U
+#define PAD_GPIO27_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO27_FUNC_SEL_SHIFT 0x15U
+#define PAD_GPIO27_FUNC_SEL_MASK 0xE00000U
+#define PAD_GPIO28_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO28_FUNC_SEL_SHIFT 0x18U
+#define PAD_GPIO28_FUNC_SEL_MASK 0x7000000U
+#define PAD_GPIO29_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO29_FUNC_SEL_SHIFT 0x1BU
+#define PAD_GPIO29_FUNC_SEL_MASK 0x38000000U
+#define SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR (0x2a4U)
+#define PAD_GPIO30_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO30_FUNC_SEL_SHIFT 0x0U
+#define PAD_GPIO30_FUNC_SEL_MASK 0x7U
+#define PAD_GPIO31_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO31_FUNC_SEL_SHIFT 0x3U
+#define PAD_GPIO31_FUNC_SEL_MASK 0x38U
+#define PAD_GPIO32_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO32_FUNC_SEL_SHIFT 0x6U
+#define PAD_GPIO32_FUNC_SEL_MASK 0x1C0U
+#define PAD_GPIO33_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO33_FUNC_SEL_SHIFT 0x9U
+#define PAD_GPIO33_FUNC_SEL_MASK 0xE00U
+#define PAD_GPIO34_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO34_FUNC_SEL_SHIFT 0xCU
+#define PAD_GPIO34_FUNC_SEL_MASK 0x7000U
+#define PAD_GPIO35_FUNC_SEL_WIDTH 0x2U
+#define PAD_GPIO35_FUNC_SEL_SHIFT 0xFU
+#define PAD_GPIO35_FUNC_SEL_MASK 0x18000U
+#define PAD_GPIO36_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO36_FUNC_SEL_SHIFT 0x11U
+#define PAD_GPIO36_FUNC_SEL_MASK 0xE0000U
+#define PAD_GPIO37_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO37_FUNC_SEL_SHIFT 0x14U
+#define PAD_GPIO37_FUNC_SEL_MASK 0x700000U
+#define PAD_GPIO38_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO38_FUNC_SEL_SHIFT 0x17U
+#define PAD_GPIO38_FUNC_SEL_MASK 0x3800000U
+#define PAD_GPIO39_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO39_FUNC_SEL_SHIFT 0x1AU
+#define PAD_GPIO39_FUNC_SEL_MASK 0x1C000000U
+#define PAD_GPIO40_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO40_FUNC_SEL_SHIFT 0x1DU
+#define PAD_GPIO40_FUNC_SEL_MASK 0xE0000000U
+#define SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR (0x2a8U)
+#define PAD_GPIO41_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO41_FUNC_SEL_SHIFT 0x0U
+#define PAD_GPIO41_FUNC_SEL_MASK 0x7U
+#define PAD_GPIO42_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO42_FUNC_SEL_SHIFT 0x3U
+#define PAD_GPIO42_FUNC_SEL_MASK 0x38U
+#define PAD_GPIO43_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO43_FUNC_SEL_SHIFT 0x6U
+#define PAD_GPIO43_FUNC_SEL_MASK 0x1C0U
+#define PAD_GPIO44_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO44_FUNC_SEL_SHIFT 0x9U
+#define PAD_GPIO44_FUNC_SEL_MASK 0xE00U
+#define PAD_GPIO45_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO45_FUNC_SEL_SHIFT 0xCU
+#define PAD_GPIO45_FUNC_SEL_MASK 0x7000U
+#define PAD_GPIO46_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO46_FUNC_SEL_SHIFT 0xFU
+#define PAD_GPIO46_FUNC_SEL_MASK 0x38000U
+#define PAD_GPIO47_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO47_FUNC_SEL_SHIFT 0x12U
+#define PAD_GPIO47_FUNC_SEL_MASK 0x1C0000U
+#define PAD_GPIO48_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO48_FUNC_SEL_SHIFT 0x15U
+#define PAD_GPIO48_FUNC_SEL_MASK 0xE00000U
+#define PAD_GPIO49_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO49_FUNC_SEL_SHIFT 0x18U
+#define PAD_GPIO49_FUNC_SEL_MASK 0x7000000U
+#define PAD_GPIO50_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO50_FUNC_SEL_SHIFT 0x1BU
+#define PAD_GPIO50_FUNC_SEL_MASK 0x38000000U
+#define PAD_GPIO51_FUNC_SEL_WIDTH 0x2U
+#define PAD_GPIO51_FUNC_SEL_SHIFT 0x1EU
+#define PAD_GPIO51_FUNC_SEL_MASK 0xC0000000U
+#define SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR (0x2acU)
+#define PAD_GPIO52_FUNC_SEL_WIDTH 0x2U
+#define PAD_GPIO52_FUNC_SEL_SHIFT 0x0U
+#define PAD_GPIO52_FUNC_SEL_MASK 0x3U
+#define PAD_GPIO53_FUNC_SEL_WIDTH 0x2U
+#define PAD_GPIO53_FUNC_SEL_SHIFT 0x2U
+#define PAD_GPIO53_FUNC_SEL_MASK 0xCU
+#define PAD_GPIO54_FUNC_SEL_WIDTH 0x2U
+#define PAD_GPIO54_FUNC_SEL_SHIFT 0x4U
+#define PAD_GPIO54_FUNC_SEL_MASK 0x30U
+#define PAD_GPIO55_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO55_FUNC_SEL_SHIFT 0x6U
+#define PAD_GPIO55_FUNC_SEL_MASK 0x1C0U
+#define PAD_GPIO56_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO56_FUNC_SEL_SHIFT 0x9U
+#define PAD_GPIO56_FUNC_SEL_MASK 0xE00U
+#define PAD_GPIO57_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO57_FUNC_SEL_SHIFT 0xCU
+#define PAD_GPIO57_FUNC_SEL_MASK 0x7000U
+#define PAD_GPIO58_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO58_FUNC_SEL_SHIFT 0xFU
+#define PAD_GPIO58_FUNC_SEL_MASK 0x38000U
+#define PAD_GPIO59_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO59_FUNC_SEL_SHIFT 0x12U
+#define PAD_GPIO59_FUNC_SEL_MASK 0x1C0000U
+#define PAD_GPIO60_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO60_FUNC_SEL_SHIFT 0x15U
+#define PAD_GPIO60_FUNC_SEL_MASK 0xE00000U
+#define PAD_GPIO61_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO61_FUNC_SEL_SHIFT 0x18U
+#define PAD_GPIO61_FUNC_SEL_MASK 0x7000000U
+#define PAD_GPIO62_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO62_FUNC_SEL_SHIFT 0x1BU
+#define PAD_GPIO62_FUNC_SEL_MASK 0x38000000U
+#define PAD_GPIO63_FUNC_SEL_WIDTH 0x2U
+#define PAD_GPIO63_FUNC_SEL_SHIFT 0x1EU
+#define PAD_GPIO63_FUNC_SEL_MASK 0xC0000000U
+#define SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR (0x2b0U)
+#define PAD_GPIO6_FUNC_SEL_WIDTH 0x2U
+#define PAD_GPIO6_FUNC_SEL_SHIFT 0x0U
+#define PAD_GPIO6_FUNC_SEL_MASK 0x3U
+#define PAD_GPIO7_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO7_FUNC_SEL_SHIFT 0x2U
+#define PAD_GPIO7_FUNC_SEL_MASK 0x1CU
+#define PAD_GPIO8_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO8_FUNC_SEL_SHIFT 0x5U
+#define PAD_GPIO8_FUNC_SEL_MASK 0xE0U
+#define PAD_GPIO9_FUNC_SEL_WIDTH 0x3U
+#define PAD_GPIO9_FUNC_SEL_SHIFT 0x8U
+#define PAD_GPIO9_FUNC_SEL_MASK 0x700U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_WIDTH 0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_SHIFT 0xBU
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_MASK 0x3800U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_WIDTH 0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_SHIFT 0xEU
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_MASK 0x1C000U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_WIDTH 0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_SHIFT 0x11U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_MASK 0xE0000U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_WIDTH 0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_SHIFT 0x14U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_MASK 0x700000U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_WIDTH 0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_SHIFT 0x17U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_MASK 0x3800000U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_WIDTH 0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_SHIFT 0x1AU
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_MASK 0x1C000000U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_WIDTH 0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_SHIFT 0x1DU
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_MASK 0xE0000000U
+#define SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR (0x2b4U)
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_WIDTH 0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_SHIFT 0x0U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_MASK 0x7U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_WIDTH 0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_SHIFT 0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_MASK 0x38U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_WIDTH 0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_SHIFT 0x6U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_MASK 0x1C0U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_WIDTH 0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_SHIFT 0x9U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_MASK 0xE00U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_WIDTH 0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_SHIFT 0xCU
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_MASK 0x7000U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_WIDTH 0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_SHIFT 0xFU
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_MASK 0x38000U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_WIDTH 0x3U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_SHIFT 0x12U
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_MASK 0x1C0000U
+#define U0_SYS_CRG_DVP_CLK_FUNC_SEL_WIDTH 0x3U
+#define U0_SYS_CRG_DVP_CLK_FUNC_SEL_SHIFT 0x15U
+#define U0_SYS_CRG_DVP_CLK_FUNC_SEL_MASK 0xE00000U
+
+#define PAD_GMAC1_RXC_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GMAC1_RXC_FUNC_SEL_SHIFT PAD_GMAC1_RXC_FUNC_SEL_MASK
+#define PAD_GPIO10_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO10_FUNC_SEL_SHIFT PAD_GPIO10_FUNC_SEL_MASK
+#define PAD_GPIO11_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO11_FUNC_SEL_SHIFT PAD_GPIO11_FUNC_SEL_MASK
+#define PAD_GPIO12_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO12_FUNC_SEL_SHIFT PAD_GPIO12_FUNC_SEL_MASK
+#define PAD_GPIO13_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO13_FUNC_SEL_SHIFT PAD_GPIO13_FUNC_SEL_MASK
+#define PAD_GPIO14_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO14_FUNC_SEL_SHIFT PAD_GPIO14_FUNC_SEL_MASK
+#define PAD_GPIO15_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO15_FUNC_SEL_SHIFT PAD_GPIO15_FUNC_SEL_MASK
+#define PAD_GPIO16_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO16_FUNC_SEL_SHIFT PAD_GPIO16_FUNC_SEL_MASK
+#define PAD_GPIO17_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO17_FUNC_SEL_SHIFT PAD_GPIO17_FUNC_SEL_MASK
+#define PAD_GPIO18_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO18_FUNC_SEL_SHIFT PAD_GPIO18_FUNC_SEL_MASK
+#define PAD_GPIO19_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_668_ADDR PAD_GPIO19_FUNC_SEL_SHIFT PAD_GPIO19_FUNC_SEL_MASK
+#define PAD_GPIO20_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO20_FUNC_SEL_SHIFT PAD_GPIO20_FUNC_SEL_MASK
+#define PAD_GPIO21_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO21_FUNC_SEL_SHIFT PAD_GPIO21_FUNC_SEL_MASK
+#define PAD_GPIO22_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO22_FUNC_SEL_SHIFT PAD_GPIO22_FUNC_SEL_MASK
+#define PAD_GPIO23_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO23_FUNC_SEL_SHIFT PAD_GPIO23_FUNC_SEL_MASK
+#define PAD_GPIO24_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO24_FUNC_SEL_SHIFT PAD_GPIO24_FUNC_SEL_MASK
+#define PAD_GPIO25_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO25_FUNC_SEL_SHIFT PAD_GPIO25_FUNC_SEL_MASK
+#define PAD_GPIO26_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO26_FUNC_SEL_SHIFT PAD_GPIO26_FUNC_SEL_MASK
+#define PAD_GPIO27_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO27_FUNC_SEL_SHIFT PAD_GPIO27_FUNC_SEL_MASK
+#define PAD_GPIO28_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO28_FUNC_SEL_SHIFT PAD_GPIO28_FUNC_SEL_MASK
+#define PAD_GPIO29_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_672_ADDR PAD_GPIO29_FUNC_SEL_SHIFT PAD_GPIO29_FUNC_SEL_MASK
+#define PAD_GPIO30_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO30_FUNC_SEL_SHIFT PAD_GPIO30_FUNC_SEL_MASK
+#define PAD_GPIO31_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO31_FUNC_SEL_SHIFT PAD_GPIO31_FUNC_SEL_MASK
+#define PAD_GPIO32_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO32_FUNC_SEL_SHIFT PAD_GPIO32_FUNC_SEL_MASK
+#define PAD_GPIO33_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO33_FUNC_SEL_SHIFT PAD_GPIO33_FUNC_SEL_MASK
+#define PAD_GPIO34_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO34_FUNC_SEL_SHIFT PAD_GPIO34_FUNC_SEL_MASK
+#define PAD_GPIO35_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO35_FUNC_SEL_SHIFT PAD_GPIO35_FUNC_SEL_MASK
+#define PAD_GPIO36_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO36_FUNC_SEL_SHIFT PAD_GPIO36_FUNC_SEL_MASK
+#define PAD_GPIO37_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO37_FUNC_SEL_SHIFT PAD_GPIO37_FUNC_SEL_MASK
+#define PAD_GPIO38_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO38_FUNC_SEL_SHIFT PAD_GPIO38_FUNC_SEL_MASK
+#define PAD_GPIO39_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO39_FUNC_SEL_SHIFT PAD_GPIO39_FUNC_SEL_MASK
+#define PAD_GPIO40_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_676_ADDR PAD_GPIO40_FUNC_SEL_SHIFT PAD_GPIO40_FUNC_SEL_MASK
+#define PAD_GPIO41_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO41_FUNC_SEL_SHIFT PAD_GPIO41_FUNC_SEL_MASK
+#define PAD_GPIO42_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO42_FUNC_SEL_SHIFT PAD_GPIO42_FUNC_SEL_MASK
+#define PAD_GPIO43_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO43_FUNC_SEL_SHIFT PAD_GPIO43_FUNC_SEL_MASK
+#define PAD_GPIO44_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO44_FUNC_SEL_SHIFT PAD_GPIO44_FUNC_SEL_MASK
+#define PAD_GPIO45_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO45_FUNC_SEL_SHIFT PAD_GPIO45_FUNC_SEL_MASK
+#define PAD_GPIO46_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO46_FUNC_SEL_SHIFT PAD_GPIO46_FUNC_SEL_MASK
+#define PAD_GPIO47_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO47_FUNC_SEL_SHIFT PAD_GPIO47_FUNC_SEL_MASK
+#define PAD_GPIO48_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO48_FUNC_SEL_SHIFT PAD_GPIO48_FUNC_SEL_MASK
+#define PAD_GPIO49_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO49_FUNC_SEL_SHIFT PAD_GPIO49_FUNC_SEL_MASK
+#define PAD_GPIO50_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO50_FUNC_SEL_SHIFT PAD_GPIO50_FUNC_SEL_MASK
+#define PAD_GPIO51_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_680_ADDR PAD_GPIO51_FUNC_SEL_SHIFT PAD_GPIO51_FUNC_SEL_MASK
+#define PAD_GPIO52_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO52_FUNC_SEL_SHIFT PAD_GPIO52_FUNC_SEL_MASK
+#define PAD_GPIO53_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO53_FUNC_SEL_SHIFT PAD_GPIO53_FUNC_SEL_MASK
+#define PAD_GPIO54_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO54_FUNC_SEL_SHIFT PAD_GPIO54_FUNC_SEL_MASK
+#define PAD_GPIO55_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO55_FUNC_SEL_SHIFT PAD_GPIO55_FUNC_SEL_MASK
+#define PAD_GPIO56_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO56_FUNC_SEL_SHIFT PAD_GPIO56_FUNC_SEL_MASK
+#define PAD_GPIO57_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO57_FUNC_SEL_SHIFT PAD_GPIO57_FUNC_SEL_MASK
+#define PAD_GPIO58_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO58_FUNC_SEL_SHIFT PAD_GPIO58_FUNC_SEL_MASK
+#define PAD_GPIO59_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO59_FUNC_SEL_SHIFT PAD_GPIO59_FUNC_SEL_MASK
+#define PAD_GPIO60_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO60_FUNC_SEL_SHIFT PAD_GPIO60_FUNC_SEL_MASK
+#define PAD_GPIO61_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO61_FUNC_SEL_SHIFT PAD_GPIO61_FUNC_SEL_MASK
+#define PAD_GPIO62_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO62_FUNC_SEL_SHIFT PAD_GPIO62_FUNC_SEL_MASK
+#define PAD_GPIO63_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_684_ADDR PAD_GPIO63_FUNC_SEL_SHIFT PAD_GPIO63_FUNC_SEL_MASK
+#define PAD_GPIO6_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR PAD_GPIO6_FUNC_SEL_SHIFT PAD_GPIO6_FUNC_SEL_MASK
+#define PAD_GPIO7_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR PAD_GPIO7_FUNC_SEL_SHIFT PAD_GPIO7_FUNC_SEL_MASK
+#define PAD_GPIO8_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR PAD_GPIO8_FUNC_SEL_SHIFT PAD_GPIO8_FUNC_SEL_MASK
+#define PAD_GPIO9_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR PAD_GPIO9_FUNC_SEL_SHIFT PAD_GPIO9_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C0_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C10_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C11_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C1_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C2_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C3_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_688_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C4_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C5_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C6_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C7_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C8_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_DATA_C9_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_HVALID_C_FUNC_SEL_MASK
+#define U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_SHIFT U0_DOM_ISP_TOP_U0_VIN_DVP_VVALID_C_FUNC_SEL_MASK
+#define U0_SYS_CRG_DVP_CLK_FUNC_SEL SYS_IOMUX_CFGSAIF__SYSCFG_692_ADDR U0_SYS_CRG_DVP_CLK_FUNC_SEL_SHIFT U0_SYS_CRG_DVP_CLK_FUNC_SEL_MASK
+/************************sys_iomux***************************/
+//aon ioconfig
+
+// POS[0]
+#define TESTEN_POS(data) ((data << 0x0U) & 0x1U)
+
+// SMT[0] POS[1]
+#define RSTN_SMT(data) ((data << 0x0U) & 0x1U)
+#define RSTN_POS(data) ((data << 0x1U) & 0x2U)
+
+// DS[1:0]
+#define OSC_DS(data) ((data << 0x0U) & 0x3U)
+
+//sys ioconfig
+// IE[0] DS[2:1] PU[3] PD[4] SLEW[5] SMT[6] POS[7]
+#define GPIO_IE(data) ((data << 0x0U) & 0x1U)
+#define GPIO_DS(data) ((data << 0x1U) & 0x6U)
+#define GPIO_PU(data) ((data << 0x3U) & 0x8U)
+#define GPIO_PD(data) ((data << 0x4U) & 0x7U)
+#define GPIO_SLEW(data) ((data << 0x5U) & 0x20U)
+#define GPIO_SMT(data) ((data << 0x6U) & 0x40U)
+#define GPIO_POS(data) ((data << 0x7U) & 0x80U)
+
+#define IO(config) ((config) & 0xFF)
+#define DOUT(dout) ((dout) & 0xFF)
+#define DOEN(doen) ((doen) & 0xFF)
+#define DIN(din_reg) ((din_reg) & 0xFF)
+
+#endif
projects / platform / kernel / linux-starfive.git / commitdiff