+2019-12-27 Richard Sandiford <richard.sandiford@arm.com>
+
+ * tree-vect-loop.c (vectorizable_reduction): Check whether the
+ target supports the required VEC_COND_EXPR operation before
+ allowing the fallback handling of masked fold-left reductions.
+
2019-12-24 Jiufu Guo <guojiufu@linux.ibm.com>
* config/rs6000/rs6000.c (rs6000_option_override_internal): Enable
+2019-12-27 Richard Sandiford <richard.sandiford@arm.com>
+
+ * gcc.target/aarch64/sve/mixed_size_10.c: New test.
+
2019-12-26 Jakub Jelinek <jakub@redhat.com>
PR c++/92438
--- /dev/null
+/* { dg-options "-O3 -msve-vector-bits=256 -fno-tree-loop-distribution" } */
+
+float
+f (float *restrict x, double *restrict y)
+{
+ float res = 0.0;
+ for (int i = 0; i < 100; ++i)
+ {
+ res += x[i];
+ y[i] += y[i - 4] * 11;
+ }
+ return res;
+}
" conditional operation is available.\n");
LOOP_VINFO_CAN_FULLY_MASK_P (loop_vinfo) = false;
}
+ else if (reduction_type == FOLD_LEFT_REDUCTION
+ && reduc_fn == IFN_LAST
+ && !expand_vec_cond_expr_p (vectype_in,
+ truth_type_for (vectype_in),
+ SSA_NAME))
+ {
+ if (dump_enabled_p ())
+ dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,
+ "can't use a fully-masked loop because no"
+ " conditional operation is available.\n");
+ LOOP_VINFO_CAN_FULLY_MASK_P (loop_vinfo) = false;
+ }
else
vect_record_loop_mask (loop_vinfo, masks, ncopies * vec_num,
vectype_in, NULL);