goto cleanup;
}
- if (dev->dev_info.high_va_offset && dev->dev_info.high_va_max) {
- start = dev->dev_info.high_va_offset;
- max = dev->dev_info.high_va_max;
- } else {
- start = dev->dev_info.virtual_address_offset;
- max = dev->dev_info.virtual_address_max;
- }
-
- max = MIN2(max, (start & ~0xffffffffULL) + 0x100000000ULL);
+ start = dev->dev_info.virtual_address_offset;
+ max = MIN2(dev->dev_info.virtual_address_max, 0x100000000ULL);
amdgpu_vamgr_init(&dev->vamgr_32, start, max,
dev->dev_info.virtual_address_alignment);
dev->address32_hi = start >> 32;
start = max;
- if (dev->dev_info.high_va_offset && dev->dev_info.high_va_max)
- max = dev->dev_info.high_va_max;
- else
- max = dev->dev_info.virtual_address_max;
+ max = MAX2(dev->dev_info.virtual_address_max, 0x100000000ULL);
amdgpu_vamgr_init(&dev->vamgr, start, max,
dev->dev_info.virtual_address_alignment);
+ start = dev->dev_info.high_va_offset;
+ max = MIN2(dev->dev_info.high_va_max, (start & ~0xffffffffULL) +
+ 0x100000000ULL);
+ amdgpu_vamgr_init(&dev->vamgr_high_32, start, max,
+ dev->dev_info.virtual_address_alignment);
+
+ start = max;
+ max = MAX2(dev->dev_info.high_va_max, (start & ~0xffffffffULL) +
+ 0x100000000ULL);
+ amdgpu_vamgr_init(&dev->vamgr_high, start, max,
+ dev->dev_info.virtual_address_alignment);
+
amdgpu_parse_asic_ids(dev);
*major_version = dev->major_version;
pthread_mutex_t bo_table_mutex;
struct drm_amdgpu_info_device dev_info;
struct amdgpu_gpu_info info;
- /** The global VA manager for the whole virtual address space */
+ /** The VA manager for the lower virtual address space */
struct amdgpu_bo_va_mgr vamgr;
/** The VA manager for the 32bit address space */
struct amdgpu_bo_va_mgr vamgr_32;
+ /** The VA manager for the high virtual address space */
+ struct amdgpu_bo_va_mgr vamgr_high;
+ /** The VA manager for the 32bit high address space */
+ struct amdgpu_bo_va_mgr vamgr_high_32;
};
struct amdgpu_bo {