KVM: x86/mmu: Ignore CR0 and CR4 bits in nested EPT MMU role

Do not incorporate CR0/CR4 bits into the role for the nested EPT MMU, as
EPT behavior is not influenced by CR0/CR4.  Note, this is the guest_mmu,
(L1's EPT), not nested_mmu (L2's IA32 paging); the nested_mmu does need
CR0/CR4, and is initialized in a separate flow.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20210622175739.3610207-23-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
index 28bfe18..52e4055 100644 (file)
--- a/arch/x86/kvm/mmu/mmu.c
+++ b/arch/x86/kvm/mmu/mmu.c
@@ -4767,8 +4767,10 @@ kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
        role.base.guest_mode = true;
        role.base.access = ACC_ALL;
 
-       role.ext = kvm_calc_mmu_role_ext(vcpu);
+       /* EPT, and thus nested EPT, does not consume CR0, CR4, nor EFER. */
+       role.ext.word = 0;
        role.ext.execonly = execonly;
+       role.ext.valid = 1;
 
        return role;
 }