radv_pipeline_emit_multisample_state(struct radeon_cmdbuf *ctx_cs,
const struct radv_graphics_pipeline *pipeline)
{
- const struct radv_physical_device *pdevice = pipeline->base.device->physical_device;
const struct radv_multisample_state *ms = &pipeline->ms;
radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
-
- /* The exclusion bits can be set to improve rasterization efficiency
- * if no sample lies on the pixel boundary (-8 sample offset). It's
- * currently always TRUE because the driver doesn't support 16 samples.
- */
- bool exclusion = pdevice->rad_info.gfx_level >= GFX7;
- radeon_set_context_reg(
- ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
- S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) | S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
}
static void
radeon_set_uconfig_reg(cs, R_031114_SPI_GS_THROTTLE_CNTL2, 0x1544D);
}
+ /* The exclusion bits can be set to improve rasterization efficiency if no sample lies on the
+ * pixel boundary (-8 sample offset). It's currently always TRUE because the driver doesn't
+ * support 16 samples.
+ */
+ bool exclusion = physical_device->rad_info.gfx_level >= GFX7;
+ radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
+ S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
+ S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
+
si_emit_compute(device, cs);
}