phy: qcom: qmp-combo: reuse register layouts for some more registers

Use register layout for TX_HIGHZ_DRVR_EN and TX_TRANSCEIVER_BIAS_EN
registers. This will allow us to unify qmp_v[456]_configure_dp_phy()
functions in the next commit.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230621153317.1025914-5-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 8dd00a1..a2db4ce 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -116,6 +116,8 @@ enum qphy_reg_layout {
        QPHY_TX_TX_POL_INV,
        QPHY_TX_TX_DRV_LVL,
        QPHY_TX_TX_EMP_POST1_LVL,
+       QPHY_TX_HIGHZ_DRVR_EN,
+       QPHY_TX_TRANSCEIVER_BIAS_EN,
 
        /* Keep last to ensure regs_layout arrays are properly initialized */
        QPHY_LAYOUT_SIZE
@@ -138,6 +140,8 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
        [QPHY_TX_TX_POL_INV]            = QSERDES_V3_TX_TX_POL_INV,
        [QPHY_TX_TX_DRV_LVL]            = QSERDES_V3_TX_TX_DRV_LVL,
        [QPHY_TX_TX_EMP_POST1_LVL]      = QSERDES_V3_TX_TX_EMP_POST1_LVL,
+       [QPHY_TX_HIGHZ_DRVR_EN]         = QSERDES_V3_TX_HIGHZ_DRVR_EN,
+       [QPHY_TX_TRANSCEIVER_BIAS_EN]   = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN,
 };
 
 static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
@@ -159,6 +163,8 @@ static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
        [QPHY_TX_TX_POL_INV]            = QSERDES_V4_TX_TX_POL_INV,
        [QPHY_TX_TX_DRV_LVL]            = QSERDES_V4_TX_TX_DRV_LVL,
        [QPHY_TX_TX_EMP_POST1_LVL]      = QSERDES_V4_TX_TX_EMP_POST1_LVL,
+       [QPHY_TX_HIGHZ_DRVR_EN]         = QSERDES_V4_TX_HIGHZ_DRVR_EN,
+       [QPHY_TX_TRANSCEIVER_BIAS_EN]   = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN,
 };
 
 static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
@@ -180,6 +186,8 @@ static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
        [QPHY_TX_TX_POL_INV]            = QSERDES_V5_5NM_TX_TX_POL_INV,
        [QPHY_TX_TX_DRV_LVL]            = QSERDES_V5_5NM_TX_TX_DRV_LVL,
        [QPHY_TX_TX_EMP_POST1_LVL]      = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL,
+       [QPHY_TX_HIGHZ_DRVR_EN]         = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN,
+       [QPHY_TX_TRANSCEIVER_BIAS_EN]   = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN,
 };
 
 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
@@ -201,6 +209,8 @@ static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
        [QPHY_TX_TX_POL_INV]            = QSERDES_V6_TX_TX_POL_INV,
        [QPHY_TX_TX_DRV_LVL]            = QSERDES_V6_TX_TX_DRV_LVL,
        [QPHY_TX_TX_EMP_POST1_LVL]      = QSERDES_V6_TX_TX_EMP_POST1_LVL,
+       [QPHY_TX_HIGHZ_DRVR_EN]         = QSERDES_V6_TX_HIGHZ_DRVR_EN,
+       [QPHY_TX_TRANSCEIVER_BIAS_EN]   = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN,
 };
 
 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
@@ -2346,10 +2356,10 @@ static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp)
                drvr1_en = 0x10;
        }
 
-       writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-       writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-       writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-       writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
+       writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
+       writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
+       writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
+       writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
 
        writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
        udelay(2000);
@@ -2406,10 +2416,10 @@ static int qmp_v5_configure_dp_phy(struct qmp_combo *qmp)
                drvr1_en = 0x10;
        }
 
-       writel(drvr0_en, qmp->dp_tx + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN);
-       writel(bias0_en, qmp->dp_tx + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN);
-       writel(drvr1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN);
-       writel(bias1_en, qmp->dp_tx2 + QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN);
+       writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
+       writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
+       writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
+       writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
 
        writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
        udelay(2000);
@@ -2464,10 +2474,10 @@ static int qmp_v6_configure_dp_phy(struct qmp_combo *qmp)
                drvr1_en = 0x10;
        }
 
-       writel(drvr0_en, qmp->dp_tx + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-       writel(bias0_en, qmp->dp_tx + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
-       writel(drvr1_en, qmp->dp_tx2 + QSERDES_V4_TX_HIGHZ_DRVR_EN);
-       writel(bias1_en, qmp->dp_tx2 + QSERDES_V4_TX_TRANSCEIVER_BIAS_EN);
+       writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
+       writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
+       writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
+       writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
 
        writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
        udelay(2000);

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
index b4810c4..8883e1d 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6.h
@@ -17,6 +17,8 @@
 #define QSERDES_V6_TX_RES_CODE_LANE_RX                         0x38
 #define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX                  0x3c
 #define QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX                  0x40
+#define QSERDES_V6_TX_TRANSCEIVER_BIAS_EN                      0x54
+#define QSERDES_V6_TX_HIGHZ_DRVR_EN                            0x58
 #define QSERDES_V6_TX_TX_POL_INV                               0x5c
 #define QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN               0x60
 #define QSERDES_V6_TX_BIST_PATTERN7                            0x7c