drm/radeon: re-enable selective GPUVM flushing

Now that the PFP and ME synchronization is fixed, we
can enable this again reliably.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>

diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c
index 832ef32..088ffdc 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_vm.c
+++ b/drivers/gpu/drm/radeon/radeon_vm.c
@@ -238,9 +238,7 @@ void radeon_vm_flush(struct radeon_device *rdev,
        uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory);
 
        /* if we can't remember our last VM flush then flush now! */
-       /* XXX figure out why we have to flush all the time before CIK */
-       if (rdev->family < CHIP_BONAIRE ||
-           !vm->last_flush || pd_addr != vm->pd_gpu_addr) {
+       if (!vm->last_flush || pd_addr != vm->pd_gpu_addr) {
                trace_radeon_vm_flush(pd_addr, ring, vm->id);
                vm->pd_gpu_addr = pd_addr;
                radeon_ring_vm_flush(rdev, ring, vm);