2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210861.
2014-05-23 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/predicates.md (aarch64_call_insn_operand): New
predicate.
* config/aarch64/constraints.md ("Ucs", "Usf"): New constraints.
* config/aarch64/aarch64.md (*sibcall_insn, *sibcall_value_insn):
Adjust for tailcalling through registers.
* config/aarch64/aarch64.h (enum reg_class): New caller save
register class.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
* config/aarch64/aarch64.c (aarch64_function_ok_for_sibcall):
Allow tailcalling without decls.
gcc/testsuite
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210861.
2014-05-23 Jiong Wang <jiong.wang@arm.com>
* gcc.target/aarch64/tail_indirect_call_1.c: New.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212695
138bc75d-0d04-0410-961f-
82ee72b054a4
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
+ Backport from trunk r210861.
+ 2014-05-23 Jiong Wang <jiong.wang@arm.com>
+
+ * config/aarch64/predicates.md (aarch64_call_insn_operand): New
+ predicate.
+ * config/aarch64/constraints.md ("Ucs", "Usf"): New constraints.
+ * config/aarch64/aarch64.md (*sibcall_insn, *sibcall_value_insn):
+ Adjust for tailcalling through registers.
+ * config/aarch64/aarch64.h (enum reg_class): New caller save
+ register class.
+ (REG_CLASS_NAMES): Likewise.
+ (REG_CLASS_CONTENTS): Likewise.
+ * config/aarch64/aarch64.c (aarch64_function_ok_for_sibcall):
+ Allow tailcalling without decls.
+
+2014-07-16 Yvan Roux <yvan.roux@linaro.org>
+
Backport from trunk r211314.
2014-06-06 James Greenhalgh <james.greenhalgh@arm.com>
}
static bool
-aarch64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
+aarch64_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
+ tree exp ATTRIBUTE_UNUSED)
{
- /* Indirect calls are not currently supported. */
- if (decl == NULL)
- return false;
-
- /* Cannot tail-call to long-calls, since these are outside of the
- range of a branch instruction (we could handle this if we added
- support for indirect tail-calls. */
- if (aarch64_decl_is_long_call_p (decl))
- return false;
-
+ /* Currently, always true. */
return true;
}
{
switch (regclass)
{
+ case CALLER_SAVE_REGS:
case CORE_REGS:
case POINTER_REGS:
case GENERAL_REGS:
enum reg_class
{
NO_REGS,
+ CALLER_SAVE_REGS,
CORE_REGS,
GENERAL_REGS,
STACK_REG,
#define REG_CLASS_NAMES \
{ \
"NO_REGS", \
+ "CALLER_SAVE_REGS", \
"CORE_REGS", \
"GENERAL_REGS", \
"STACK_REG", \
#define REG_CLASS_CONTENTS \
{ \
{ 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
+ { 0x0007ffff, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \
{ 0x7fffffff, 0x00000000, 0x00000003 }, /* CORE_REGS */ \
{ 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \
{ 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \
(use (match_operand 2 "" ""))])]
""
{
+ if (!REG_P (XEXP (operands[0], 0))
+ && (GET_CODE (XEXP (operands[0], 0)) != SYMBOL_REF))
+ XEXP (operands[0], 0) = force_reg (Pmode, XEXP (operands[0], 0));
+
if (operands[2] == NULL_RTX)
operands[2] = const0_rtx;
}
(use (match_operand 3 "" ""))])]
""
{
+ if (!REG_P (XEXP (operands[1], 0))
+ && (GET_CODE (XEXP (operands[1], 0)) != SYMBOL_REF))
+ XEXP (operands[1], 0) = force_reg (Pmode, XEXP (operands[1], 0));
+
if (operands[3] == NULL_RTX)
operands[3] = const0_rtx;
}
)
(define_insn "*sibcall_insn"
- [(call (mem:DI (match_operand:DI 0 "" "X"))
+ [(call (mem:DI (match_operand:DI 0 "aarch64_call_insn_operand" "Ucs, Usf"))
(match_operand 1 "" ""))
(return)
(use (match_operand 2 "" ""))]
- "GET_CODE (operands[0]) == SYMBOL_REF"
- "b\\t%a0"
- [(set_attr "type" "branch")]
-
+ "SIBLING_CALL_P (insn)"
+ "@
+ br\\t%0
+ b\\t%a0"
+ [(set_attr "type" "branch, branch")]
)
(define_insn "*sibcall_value_insn"
[(set (match_operand 0 "" "")
- (call (mem:DI (match_operand 1 "" "X"))
+ (call (mem:DI (match_operand 1 "aarch64_call_insn_operand" "Ucs, Usf"))
(match_operand 2 "" "")))
(return)
(use (match_operand 3 "" ""))]
- "GET_CODE (operands[1]) == SYMBOL_REF"
- "b\\t%a1"
- [(set_attr "type" "branch")]
+ "SIBLING_CALL_P (insn)"
+ "@
+ br\\t%1
+ b\\t%a1"
+ [(set_attr "type" "branch, branch")]
)
;; Call subroutine returning any type.
(define_register_constraint "k" "STACK_REG"
"@internal The stack register.")
+(define_register_constraint "Ucs" "CALLER_SAVE_REGS"
+ "@internal The caller save registers.")
+
(define_register_constraint "w" "FP_REGS"
"Floating point and SIMD vector registers.")
(and (match_code "const_int")
(match_test "(unsigned HOST_WIDE_INT) ival < 64")))
+(define_constraint "Usf"
+ "@internal Usf is a symbol reference."
+ (match_code "symbol_ref"))
+
(define_constraint "UsM"
"@internal
A constraint that matches the immediate constant -1."
&& GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
)
+(define_predicate "aarch64_call_insn_operand"
+ (ior (match_code "symbol_ref")
+ (match_operand 0 "register_operand")))
+
(define_predicate "aarch64_simd_register"
(and (match_code "reg")
(ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
+ Backport from trunk r210861.
+ 2014-05-23 Jiong Wang <jiong.wang@arm.com>
+
+ * gcc.target/aarch64/tail_indirect_call_1.c: New.
+
+2014-07-16 Yvan Roux <yvan.roux@linaro.org>
+
Backport from trunk r211314.
2014-06-06 James Greenhalgh <james.greenhalgh@arm.com>
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+typedef void FP (int);
+
+/* { dg-final { scan-assembler "br" } } */
+/* { dg-final { scan-assembler-not "blr" } } */
+void
+f1 (FP fp, int n)
+{
+ (fp) (n);
+}
+
+void
+f2 (int n, FP fp)
+{
+ (fp) (n);
+}