Merge branch 'omap4' into for-next
authorTony Lindgren <tony@atomide.com>
Thu, 28 May 2009 22:45:14 +0000 (15:45 -0700)
committerTony Lindgren <tony@atomide.com>
Thu, 28 May 2009 22:45:14 +0000 (15:45 -0700)
1  2 
arch/arm/mach-omap2/Makefile
arch/arm/mach-omap2/serial.c
arch/arm/plat-omap/Kconfig
arch/arm/plat-omap/clock.c
arch/arm/plat-omap/common.c
arch/arm/plat-omap/include/mach/clock.h
arch/arm/plat-omap/include/mach/common.h
arch/arm/plat-omap/include/mach/control.h
arch/arm/plat-omap/include/mach/irqs.h
arch/arm/plat-omap/include/mach/serial.h
arch/arm/plat-omap/sram.c

@@@ -60,8 -58,13 +60,11 @@@ obj-$(CONFIG_MACH_NOKIA_RX51)               += board
  obj-$(CONFIG_MACH_OMAP_ZOOM2)         += board-zoom2.o \
                                           mmc-twl4030.o \
                                           board-zoom-debugboard.o
+ obj-$(CONFIG_MACH_OMAP_4430SDP)               += board-4430sdp.o
  # Platform specific device init code
 -ifeq ($(CONFIG_USB_MUSB_SOC),y)
  obj-y                                 += usb-musb.o
 -endif
  
  onenand-$(CONFIG_MTD_ONENAND_OMAP2)   := gpmc-onenand.o
  obj-y                                 += $(onenand-m) $(onenand-y)
@@@ -6,10 -6,11 +6,13 @@@
   * Copyright (C) 2005-2008 Nokia Corporation
   * Author: Paul Mundt <paul.mundt@nokia.com>
   *
 + * Major rework for PM support by Kevin Hilman
 + *
   * Based off of arch/arm/mach-omap/omap1/serial.c
   *
+  * Copyright (C) 2009 Texas Instruments
+  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
+  *
   * This file is subject to the terms and conditions of the GNU General Public
   * License. See the file "COPYING" in the main directory of this archive
   * for more details.
Simple merge
Simple merge
Simple merge
  #define OMAP2_PBIASLITEPWRDNZ0                (1 << 1)
  #define OMAP2_PBIASLITEVMODE0         (1 << 0)
  
 +/* CONTROL_IVA2_BOOTMOD bits */
 +#define OMAP3_IVA2_BOOTMOD_SHIFT      0
 +#define OMAP3_IVA2_BOOTMOD_MASK               (0xf << 0)
 +#define OMAP3_IVA2_BOOTMOD_IDLE               (0x1 << 0)
 +
 +/* CONTROL_PADCONF_X bits */
 +#define OMAP3_PADCONF_WAKEUPEVENT0    (1 << 15)
 +#define OMAP3_PADCONF_WAKEUPENABLE0   (1 << 14)
 +
  #ifndef __ASSEMBLY__
- #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+ #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+               defined(CONFIG_ARCH_OMAP4)
  extern void __iomem *omap_ctrl_base_get(void);
  extern u8 omap_ctrl_readb(u16 offset);
  extern u16 omap_ctrl_readw(u16 offset);
@@@ -201,17 -214,14 +214,23 @@@ void __init omap_map_sram(void
                base = OMAP3_SRAM_PA;
                base = ROUND_DOWN(base, PAGE_SIZE);
                omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 +
 +              /*
 +               * SRAM must be marked as non-cached on OMAP3 since the
 +               * CORE DPLL M2 divider change code (in SRAM) runs with the
 +               * SDRAM controller disabled, and if it is marked cached,
 +               * the ARM may attempt to write cache lines back to SDRAM
 +               * which will cause the system to hang.
 +               */
 +              omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
        }
  
+       if (cpu_is_omap44xx()) {
+               omap_sram_io_desc[0].virtual = OMAP4_SRAM_VA;
+               base = OMAP4_SRAM_PA;
+               base = ROUND_DOWN(base, PAGE_SIZE);
+               omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
+       }
        omap_sram_io_desc[0].length = 1024 * 1024;      /* Use section desc */
        iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));