hdmitx: add the arbitration between hdcp22 and EMP [1/1]

PD#SWPL-5618

Problem:
Need to optimize the arbitration between hdcp22 and EMP

Solution:
Add the arbitration between hdcp22 and EMP

Verify:
TM2/T962E2/AB311

Change-Id: Ib910ac40754e744e36ee1349de5b2c55e2a011eb
Signed-off-by: Zongdong Jiao <zongdong.jiao@amlogic.com>

diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
index 7bf3202..7f78c60 100644 (file)
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
+++ b/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c
@@ -564,6 +564,11 @@ static void hdmi_hwi_init(struct hdmitx_dev *hdev)
        hdmitx_set_reg_bits(HDMITX_TOP_CLK_CNTL, 1, 6, 1);
        /* Enable tmds_clk to HDCP2.2 IP */
        hdmitx_set_reg_bits(HDMITX_TOP_CLK_CNTL, 1, 5, 1);
+       /* Enable axi_clk */
+       hdmitx_set_reg_bits(HDMITX_TOP_CLK_CNTL, 1, 13, 1);
+       /* Enable axi_async_req_en_emp & axi_async_req_en_esm */
+       hdmitx_set_reg_bits(HDMITX_TOP_AXI_ASYNC_CNTL0, 1, 0, 1);
+       hdmitx_set_reg_bits(HDMITX_TOP_AXI_ASYNC_CNTL0, 1, 16, 1);
 
        hdmitx_hpd_hw_op(HPD_INIT_DISABLE_PULLUP);
        hdmitx_hpd_hw_op(HPD_INIT_SET_FILTER);
@@ -4178,7 +4183,7 @@ static void hdmitx_debug(struct hdmitx_dev *hdev, const char *buf)
                pr_info("topo: %d\n", hdmitx_hdcp_opr(0xe));
                return;
        } else if (strncmp(tmpbuf, "dumphdmireg", 11) == 0) {
-               unsigned char reg_val = 0;
+               unsigned int reg_val = 0;
                unsigned int reg_adr = 0;
 
 #define DUMP_HDMITX_SECTION(a, b) \
@@ -4203,8 +4208,10 @@ static void hdmitx_debug(struct hdmitx_dev *hdev, const char *buf)
                        HDMITX_TOP_SEC_SCRATCH);
                DUMP_HDMITX_SECTION(HDMITX_DWC_DESIGN_ID,
                        HDMITX_DWC_A_KSVMEMCTRL);
+#if 0
                DUMP_HDMITX_HDCP_SECTION(HDMITX_DWC_HDCP_BSTATUS_0,
                        HDMITX_DWC_HDCP_REVOC_LIST_END);
+#endif
                DUMP_HDMITX_HDCP_SECTION(HDMITX_DWC_HDCPREG_BKSV0,
                        HDMITX_DWC_HDCPREG_BKSV4);
                DUMP_HDMITX_SECTION(HDMITX_DWC_HDCPREG_ANCONF,
@@ -4793,6 +4800,7 @@ static int hdmitx_cntl_ddc(struct hdmitx_dev *hdev, unsigned int cmd,
                break;
        case DDC_HDCP_MUX_INIT:
                if (argv == 2) {
+                       hd_write_reg(P_HHI_HDCP22_CLK_CNTL, 0x01000100);
                        hdmitx_ddc_hw_op(DDC_MUX_DDC);
                        hdmitx_set_reg_bits(HDMITX_DWC_MC_CLKDIS, 1, 6, 1);
                        udelay(5);