x86: minnowmax: Add access to GPIOs E0, E1, E2
authorSimon Glass <sjg@chromium.org>
Sat, 22 Aug 2015 21:58:53 +0000 (15:58 -0600)
committerSimon Glass <sjg@chromium.org>
Wed, 26 Aug 2015 14:54:14 +0000 (07:54 -0700)
These GPIOs are accessible on the pin header. Add pinctrl settings for them
so that we they can be adjusted using the 'gpio' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
arch/x86/dts/minnowmax.dts

index f4e0a35..a8ecf0d 100644 (file)
                compatible = "intel,x86-pinctrl";
                io-base = <0x4c>;
 
+               /* GPIO E0 */
+               soc_gpio_s5_0@0 {
+                       gpio-offset = <0x80 0>;
+                       pad-offset = <0x1d0>;
+                       mode-gpio;
+                       output-value = <0>;
+                       direction = <PIN_OUTPUT>;
+               };
+
+               /* GPIO E1 */
+               soc_gpio_s5_1@0 {
+                       gpio-offset = <0x80 1>;
+                       pad-offset = <0x210>;
+                       mode-gpio;
+                       output-value = <0>;
+                       direction = <PIN_OUTPUT>;
+               };
+
+               /* GPIO E2 */
+               soc_gpio_s5_2@0 {
+                       gpio-offset = <0x80 2>;
+                       pad-offset = <0x1e0>;
+                       mode-gpio;
+                       output-value = <0>;
+                       direction = <PIN_OUTPUT>;
+               };
+
                pin_usb_host_en0@0 {
                        gpio-offset = <0x80 8>;
                        pad-offset = <0x260>;