MIPS: Remove unused R5432_CP0_INTERRUPT_WAR

R5432_CP0_INTERRUPT_WAR is defined as 0 for every system we support, and
so the workaround is never used. Remove the dead code.

Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org

diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 35c80be92207beef97ebc536b31ae93d4f0a133a..2421411b76368dadab91e1e2e67c5f2bc30ec17f 100644 (file)
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -12,7 +12,6 @@
 #define R4600_V1_INDEX_ICACHEOP_WAR    0
 #define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
-#define R5432_CP0_INTERRUPT_WAR                0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index a1bc2e71f98327cef9f2d593d6b05e6a4521f371..f0f4a35d08708602cdece953c3b100540d4a6e46 100644 (file)
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -11,7 +11,6 @@
 #define R4600_V1_INDEX_ICACHEOP_WAR    0
 #define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
-#define R5432_CP0_INTERRUPT_WAR                0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index fba640517f4faed88047cb74303ff819fd17dc34..b48eb4ac362d5214a10c521d657c4486dfda0416 100644 (file)
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -15,7 +15,6 @@
 #define R4600_V1_INDEX_ICACHEOP_WAR    1
 #define R4600_V1_HIT_CACHEOP_WAR       1
 #define R4600_V2_HIT_CACHEOP_WAR       1
-#define R5432_CP0_INTERRUPT_WAR                0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index 4ee0e4bdf4fb3b80ef7bc01d271475e19d63dc77..ef3efce0094aa6e01f2de47f89405ef693490a8a 100644 (file)
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -11,7 +11,6 @@
 #define R4600_V1_INDEX_ICACHEOP_WAR    0
 #define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
-#define R5432_CP0_INTERRUPT_WAR                0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index 4821c7b7a38cca660f35067bdcfa8e117bfefb8a..61cd67354829072db4d6f107517c3b454b28c5f1 100644 (file)
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -11,7 +11,6 @@
 #define R4600_V1_INDEX_ICACHEOP_WAR    0
 #define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
-#define R5432_CP0_INTERRUPT_WAR                0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index 9807ecda5a88a96ec34eb5e1023fc89dc52a51c4..e77b9d1b6c969eeb811ceb970fc4905a2a27bca7 100644 (file)
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -11,7 +11,6 @@
 #define R4600_V1_INDEX_ICACHEOP_WAR    0
 #define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
-#define R5432_CP0_INTERRUPT_WAR                0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index d068fc411f4787b92299211208a7ac1bde961922..d62d2ffe515ed70e159e56fdecfce5f9389a50cb 100644 (file)
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -11,7 +11,6 @@
 #define R4600_V1_INDEX_ICACHEOP_WAR    0
 #define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
-#define R5432_CP0_INTERRUPT_WAR                0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       1

diff --git a/arch/mips/include/asm/mach-pmcs-msp71xx/war.h b/arch/mips/include/asm/mach-pmcs-msp71xx/war.h
index a60bf9dd14aeceeb89be9c8dd6a57e1c557f187a..31c546f58bb5689ebf6dd119746eef5f8ec50677 100644 (file)
--- a/arch/mips/include/asm/mach-pmcs-msp71xx/war.h
+++ b/arch/mips/include/asm/mach-pmcs-msp71xx/war.h
@@ -11,7 +11,6 @@
 #define R4600_V1_INDEX_ICACHEOP_WAR    0
 #define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
-#define R5432_CP0_INTERRUPT_WAR                0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 1bfd489a3708147a24c8aa09fc6dd7d98e67e1e4..af430d26f7137916586643b8d683e7f965ef3cbf 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -11,7 +11,6 @@
 #define R4600_V1_INDEX_ICACHEOP_WAR    0
 #define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
-#define R5432_CP0_INTERRUPT_WAR                0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       1

diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index a3dde98549bb0ba29f54b7575eae0cdd9fa46607..eca16d167c2f4bfc7e751014d0460c1b284c12c6 100644 (file)
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -15,7 +15,6 @@
 #define R4600_V1_INDEX_ICACHEOP_WAR    0
 #define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       1
-#define R5432_CP0_INTERRUPT_WAR                0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 520f8fc2c8067c7e3b77cd7cd03bd39a83586c11..4755b611680709f2ecba7d84e41c08a2dc9340b7 100644 (file)
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -11,7 +11,6 @@
 #define R4600_V1_INDEX_ICACHEOP_WAR    0
 #define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
-#define R5432_CP0_INTERRUPT_WAR                0
 
 #if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
 

diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index a8e2c586a18c6330ed81fed778f7ca1f06cab021..445abb4eb76975d5a3d6df23d932d1b0b9223a96 100644 (file)
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -11,7 +11,6 @@
 #define R4600_V1_INDEX_ICACHEOP_WAR    0
 #define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
-#define R5432_CP0_INTERRUPT_WAR                0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0
 #define MIPS4K_ICACHE_REFILL_WAR       0

diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 9344e247a6c8c93a92a4c0bf829485f0fb24aa77..1eedd596a06441e319bd7deb95d61f0279253db6 100644 (file)
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -128,19 +128,6 @@
 #error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
 #endif
 
-/*
- * When an interrupt happens on a CP0 register read instruction, CPU may
- * lock up or read corrupted values of CP0 registers after it enters
- * the exception handler.
- *
- * This workaround makes sure that we read a "safe" CP0 register as the
- * first thing in the exception handler, which breaks one of the
- * pre-conditions for this problem.
- */
-#ifndef R5432_CP0_INTERRUPT_WAR
-#error Check setting of R5432_CP0_INTERRUPT_WAR for your platform
-#endif
-
 /*
  * Workaround for the Sibyte M3 errata the text of which can be found at
  *

diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 398b905b027d953feb91a71babdbc125ee79a987..efde27c9941469b37c0c5344f4c8249b28840791 100644 (file)
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -32,9 +32,6 @@
 NESTED(except_vec3_generic, 0, sp)
        .set    push
        .set    noat
-#if R5432_CP0_INTERRUPT_WAR
-       mfc0    k0, CP0_INDEX
-#endif
        mfc0    k1, CP0_CAUSE
        andi    k1, k1, 0x7c
 #ifdef CONFIG_64BIT