SH4: Convert immediate loads to TCG

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5098 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-sh4/op.c b/target-sh4/op.c
index 21b8287de6bff0e6107472f12a6ed95339048d3e..a37ff720471c073b7f0453f525ce99820833256a 100644 (file)
--- a/target-sh4/op.c
+++ b/target-sh4/op.c
@@ -37,18 +37,6 @@ static inline void cond_t(int cond)
        clr_t();
 }
 
-void OPPROTO op_movl_imm_T0(void)
-{
-    T0 = (uint32_t) PARAM1;
-    RETURN();
-}
-
-void OPPROTO op_movl_imm_T1(void)
-{
-    T1 = (uint32_t) PARAM1;
-    RETURN();
-}
-
 void OPPROTO op_cmp_eq_imm_T0(void)
 {
     cond_t((int32_t) T0 == (int32_t) PARAM1);

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index c00f6574936c7315191326bdbc17b9d6a34667aa..9c1cb165c11c6c26e21d1ee56ba6d4293278d7c4 100644 (file)
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -337,12 +337,12 @@ void _decode_opc(DisasContext * ctx)
        gen_op_movl_imm_rN(B7_0s, REG(B11_8));
        return;
     case 0x9000:               /* mov.w @(disp,PC),Rn */
-       gen_op_movl_imm_T0(ctx->pc + 4 + B7_0 * 2);
+       tcg_gen_movi_tl(cpu_T[0], ctx->pc + 4 + B7_0 * 2);
        gen_op_ldw_T0_T0(ctx);
        gen_op_movl_T0_rN(REG(B11_8));
        return;
     case 0xd000:               /* mov.l @(disp,PC),Rn */
-       gen_op_movl_imm_T0((ctx->pc + 4 + B7_0 * 4) & ~3);
+       tcg_gen_movi_tl(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3);
        gen_op_ldl_T0_T0(ctx);
        gen_op_movl_T0_rN(REG(B11_8));
        return;
@@ -1181,14 +1181,14 @@ void _decode_opc(DisasContext * ctx)
        break;
     case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
        if (!(ctx->fpscr & FPSCR_PR)) {
-           gen_op_movl_imm_T0(0);
+           tcg_gen_movi_tl(cpu_T[0], 0);
            gen_op_fmov_T0_frN(FREG(B11_8));
            return;
        }
        break;
     case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
        if (!(ctx->fpscr & FPSCR_PR)) {
-           gen_op_movl_imm_T0(0x3f800000);
+           tcg_gen_movi_tl(cpu_T[0], 0x3f800000);
            gen_op_fmov_T0_frN(FREG(B11_8));
            return;
        }