Port
c8e4d57d3b3036a05902f5b916cb5d853a57393c
Original commit message:
They are content with a dummy vector, as MISSES won't result in
changing the real vector/slot at all.
R=mvstanton@chromium.org, michael_dawson@ca.ibm.com, dstence@us.ibm.com
BUG=
Review URL: https://codereview.chromium.org/
1085913003
Cr-Commit-Position: refs/heads/master@{#27850}
DCHECK(ToRegister(instr->object()).is(LoadDescriptor::ReceiverRegister()));
DCHECK(ToRegister(instr->key()).is(LoadDescriptor::NameRegister()));
- if (FLAG_vector_ics) {
+ if (instr->hydrogen()->HasVectorAndSlot()) {
EmitVectorLoadICRegisters<LLoadKeyedGeneric>(instr);
}