dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly

The bits of BWC, DAHTS and SAHTS in the DMA mode register must be cleared
before a new value can be or-ed in.

Signed-off-by: Thomas Breitung <thomas.breitung@izt-labs.de>
Signed-off-by: Wolfgang Ocker <weo@reccoware.de>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c
index 51c75bf..3b8b752 100644 (file)
--- a/drivers/dma/fsldma.c
+++ b/drivers/dma/fsldma.c
@@ -269,6 +269,7 @@ static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
        case 2:
        case 4:
        case 8:
+               mode &= ~FSL_DMA_MR_SAHTS_MASK;
                mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
                break;
        }
@@ -301,6 +302,7 @@ static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
        case 2:
        case 4:
        case 8:
+               mode &= ~FSL_DMA_MR_DAHTS_MASK;
                mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
                break;
        }
@@ -327,7 +329,8 @@ static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
        BUG_ON(size > 1024);
 
        mode = get_mr(chan);
-       mode |= (__ilog2(size) << 24) & 0x0f000000;
+       mode &= ~FSL_DMA_MR_BWC_MASK;
+       mode |= (__ilog2(size) << 24) & FSL_DMA_MR_BWC_MASK;
 
        set_mr(chan, mode);
 }

diff --git a/drivers/dma/fsldma.h b/drivers/dma/fsldma.h
index 31bffcc..4787d48 100644 (file)
--- a/drivers/dma/fsldma.h
+++ b/drivers/dma/fsldma.h
@@ -36,6 +36,10 @@
 #define FSL_DMA_MR_DAHE                0x00002000
 #define FSL_DMA_MR_SAHE                0x00001000
 
+#define FSL_DMA_MR_SAHTS_MASK  0x0000C000
+#define FSL_DMA_MR_DAHTS_MASK  0x00030000
+#define FSL_DMA_MR_BWC_MASK    0x0f000000
+
 /*
  * Bandwidth/pause control determines how many bytes a given
  * channel is allowed to transfer before the DMA engine pauses