arm64: dts: qcom: sm8350: Add cpufreq node

Add cpufreq node and reference it for the CPUs.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210216111703.1838663-1-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 8670c1c1ab5dec9936ed26267bb06f07f06f1bd9..2c02f451379b9d9efa566125e6c6a3721e1e4650 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -44,6 +44,7 @@
                        reg = <0x0 0x0>;
                        enable-method = "psci";
                        next-level-cache = <&L2_0>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_0: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -59,6 +60,7 @@
                        reg = <0x0 0x100>;
                        enable-method = "psci";
                        next-level-cache = <&L2_100>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_100: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -71,6 +73,7 @@
                        reg = <0x0 0x200>;
                        enable-method = "psci";
                        next-level-cache = <&L2_200>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_200: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -83,6 +86,7 @@
                        reg = <0x0 0x300>;
                        enable-method = "psci";
                        next-level-cache = <&L2_300>;
+                       qcom,freq-domain = <&cpufreq_hw 0>;
                        L2_300: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -95,6 +99,7 @@
                        reg = <0x0 0x400>;
                        enable-method = "psci";
                        next-level-cache = <&L2_400>;
+                       qcom,freq-domain = <&cpufreq_hw 1>;
                        L2_400: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -107,6 +112,7 @@
                        reg = <0x0 0x500>;
                        enable-method = "psci";
                        next-level-cache = <&L2_500>;
+                       qcom,freq-domain = <&cpufreq_hw 1>;
                        L2_500: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -120,6 +126,7 @@
                        reg = <0x0 0x600>;
                        enable-method = "psci";
                        next-level-cache = <&L2_600>;
+                       qcom,freq-domain = <&cpufreq_hw 1>;
                        L2_600: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -132,6 +139,7 @@
                        reg = <0x0 0x700>;
                        enable-method = "psci";
                        next-level-cache = <&L2_700>;
+                       qcom,freq-domain = <&cpufreq_hw 2>;
                        L2_700: l2-cache {
                              compatible = "cache";
                              next-level-cache = <&L3_0>;
@@ -788,6 +796,19 @@
                        };
                };
 
+               cpufreq_hw: cpufreq@18591000 {
+                       compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
+                       reg = <0 0x18591000 0 0x1000>,
+                             <0 0x18592000 0 0x1000>,
+                             <0 0x18593000 0 0x1000>;
+                       reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+                       clock-names = "xo", "alternate";
+
+                       #freq-domain-cells = <1>;
+               };
+
                ufs_mem_hc: ufshc@1d84000 {
                        compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
                                     "jedec,ufs-2.0";