GlobalISel: Verify memory size for load/store

llvm-svn: 352578

diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index fb15c17..761c4e6 100644 (file)
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1004,6 +1004,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
   case TargetOpcode::G_STORE:
   case TargetOpcode::G_ZEXTLOAD:
   case TargetOpcode::G_SEXTLOAD: {
+    LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
     LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
     if (!PtrTy.isPointer())
       report("Generic memory instruction must access a pointer", MI);
@@ -1014,13 +1015,17 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
       report("Generic instruction accessing memory must have one mem operand",
              MI);
     } else {
+      const MachineMemOperand &MMO = **MI->memoperands_begin();
       if (MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
           MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
-        const MachineMemOperand &MMO = **MI->memoperands_begin();
-        LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
-        if (MMO.getSize() * 8 >= DstTy.getSizeInBits()) {
+        if (MMO.getSize() * 8 >= ValTy.getSizeInBits())
           report("Generic extload must have a narrower memory type", MI);
-        }
+      } else if (MI->getOpcode() == TargetOpcode::G_LOAD) {
+        if (MMO.getSize() > (ValTy.getSizeInBits() + 7) / 8)
+          report("load memory size cannot exceed result size", MI);
+      } else if (MI->getOpcode() == TargetOpcode::G_STORE) {
+        if ((ValTy.getSizeInBits() + 7) / 8 < MMO.getSize())
+          report("store memory size cannot exceed value size", MI);
       }
     }
 

diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir
new file mode 100644 (file)
index 0000000..7b08c11
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir
@@ -0,0 +1,63 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=i386-linux-gnu   -run-pass=legalizer %s -o - | FileCheck --check-prefix=X32 %s
+
+---
+name:            test_memop_s8tos32
+alignment:       4
+legalized:       false
+regBankSelected: false
+body:             |
+  bb.0:
+    ; X32-LABEL: name: test_memop_s8tos32
+    ; X32: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+    ; X32: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
+    ; X32: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
+    ; X32: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[DEF]](p0) :: (load 2)
+    ; X32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4)
+    ; X32: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load 4)
+    ; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+    ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY [[LOAD]](s8)
+    ; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY]], [[C]]
+    ; X32: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
+    ; X32: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store 1)
+    ; X32: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store 2)
+    ; X32: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store 4)
+    ; X32: G_STORE [[LOAD4]](p0), [[DEF]](p0) :: (store 4)
+    %0:_(p0) = IMPLICIT_DEF
+    %9:_(s1) = G_LOAD %0 :: (load 1)
+    %1:_(s8) = G_LOAD %0 :: (load 1)
+    %2:_(s16) = G_LOAD %0 :: (load 2)
+    %3:_(s32) = G_LOAD %0 :: (load 4)
+    %4:_(p0) = G_LOAD %0 :: (load 4)
+
+    G_STORE %9, %0 :: (store 1)
+    G_STORE %1, %0 :: (store 1)
+    G_STORE %2, %0 :: (store 2)
+    G_STORE %3, %0 :: (store 4)
+    G_STORE %4, %0 :: (store 4)
+...
+---
+name:            test_memop_s64
+alignment:       4
+legalized:       false
+regBankSelected: false
+liveins:
+body:             |
+  bb.0:
+
+    ; X32-LABEL: name: test_memop_s64
+    ; X32: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+    ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4, align 8)
+    ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C]](s32)
+    ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p0) :: (load 4)
+    ; X32: G_STORE [[LOAD]](s32), [[DEF]](p0) :: (store 4, align 8)
+    ; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C1]](s32)
+    ; X32: G_STORE [[LOAD1]](s32), [[GEP1]](p0) :: (store 4)
+    %0:_(p0) = IMPLICIT_DEF
+    %1:_(s64) = G_LOAD %0 :: (load 8)
+
+    G_STORE %1, %0 :: (store 8)
+
+...

diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir
new file mode 100644 (file)
index 0000000..c7de33d
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer -o - %s | FileCheck -check-prefix=X64 %s
+
+---
+name:            test_memop_s8tos32
+alignment:       4
+legalized:       false
+regBankSelected: false
+body:             |
+  bb.0:
+    ; X64-LABEL: name: test_memop_s8tos32
+    ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+    ; X64: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
+    ; X64: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
+    ; X64: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[DEF]](p0) :: (load 2)
+    ; X64: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4)
+    ; X64: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load 4)
+    ; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
+    ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY [[LOAD]](s8)
+    ; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY]], [[C]]
+    ; X64: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
+    ; X64: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store 1)
+    ; X64: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store 2)
+    ; X64: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store 4)
+    ; X64: G_STORE [[LOAD4]](p0), [[DEF]](p0) :: (store 4)
+    %0:_(p0) = IMPLICIT_DEF
+    %9:_(s1) = G_LOAD %0(p0) :: (load 1)
+    %1:_(s8) = G_LOAD %0(p0) :: (load 1)
+    %2:_(s16) = G_LOAD %0(p0) :: (load 2)
+    %3:_(s32) = G_LOAD %0(p0) :: (load 4)
+    %4:_(p0) = G_LOAD %0(p0) :: (load 4)
+
+    G_STORE %9, %0 :: (store 1)
+    G_STORE %1, %0 :: (store 1)
+    G_STORE %2, %0 :: (store 2)
+    G_STORE %3, %0 :: (store 4)
+    G_STORE %4, %0 :: (store 4)
+...
+---
+name:            test_memop_s64
+alignment:       4
+legalized:       false
+regBankSelected: false
+liveins:
+body:             |
+  bb.0:
+
+    ; X64-LABEL: name: test_memop_s64
+    ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
+    ; X64: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[DEF]](p0) :: (load 8)
+    ; X64: G_STORE [[LOAD]](s64), [[DEF]](p0) :: (store 8)
+    %0:_(p0) = IMPLICIT_DEF
+    %1:_(s64) = G_LOAD %0 :: (load 8)
+
+    G_STORE %1, %0 :: (store 8)
+
+...

diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir
deleted file mode 100644 (file)
index 1117783..0000000
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar.mir
+++ /dev/null
@@ -1,112 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
-# RUN: llc -O0 -mtriple=i386-linux-gnu   -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
-
---- |
-  define void @test_memop_s8tos32() {
-    ret void
-  }
-
-  define void @test_memop_s64() {
-    ret void
-  }
-...
----
-name:            test_memop_s8tos32
-alignment:       4
-legalized:       false
-regBankSelected: false
-registers:
-  - { id: 0, class: _, preferred-register: '' }
-  - { id: 1, class: _, preferred-register: '' }
-  - { id: 2, class: _, preferred-register: '' }
-  - { id: 3, class: _, preferred-register: '' }
-  - { id: 4, class: _, preferred-register: '' }
-  - { id: 5, class: _, preferred-register: '' }
-  - { id: 6, class: _, preferred-register: '' }
-  - { id: 7, class: _, preferred-register: '' }
-  - { id: 8, class: _, preferred-register: '' }
-  - { id: 9, class: _, preferred-register: '' }
-  - { id: 10, class: _, preferred-register: '' }
-body:             |
-  bb.1 (%ir-block.0):
-    liveins: $rdi
-
-    ; X64-LABEL: name: test_memop_s8tos32
-    ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
-    ; X64: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
-    ; X64: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
-    ; X64: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[DEF]](p0) :: (load 2)
-    ; X64: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4)
-    ; X64: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load 8)
-    ; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
-    ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY [[LOAD]](s8)
-    ; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY]], [[C]]
-    ; X64: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
-    ; X64: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store 1)
-    ; X64: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store 2)
-    ; X64: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store 4)
-    ; X64: G_STORE [[LOAD4]](p0), [[DEF]](p0) :: (store 8)
-    ; X32-LABEL: name: test_memop_s8tos32
-    ; X32: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
-    ; X32: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
-    ; X32: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
-    ; X32: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[DEF]](p0) :: (load 2)
-    ; X32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4)
-    ; X32: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load 8)
-    ; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
-    ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY [[LOAD]](s8)
-    ; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY]], [[C]]
-    ; X32: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
-    ; X32: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store 1)
-    ; X32: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store 2)
-    ; X32: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store 4)
-    ; X32: G_STORE [[LOAD4]](p0), [[DEF]](p0) :: (store 8)
-    %0(p0) = IMPLICIT_DEF
-    %9(s1) = G_LOAD %0(p0) :: (load 1)
-    %1(s8) = G_LOAD %0(p0) :: (load 1)
-    %2(s16) = G_LOAD %0(p0) :: (load 2)
-    %3(s32) = G_LOAD %0(p0) :: (load 4)
-    %4(p0) = G_LOAD %0(p0) :: (load 8)
-
-    G_STORE %9, %0 :: (store 1)
-    G_STORE %1, %0 :: (store 1)
-    G_STORE %2, %0 :: (store 2)
-    G_STORE %3, %0 :: (store 4)
-    G_STORE %4, %0 :: (store 8)
-...
----
-name:            test_memop_s64
-alignment:       4
-legalized:       false
-regBankSelected: false
-registers:
-  - { id: 0, class: _, preferred-register: '' }
-  - { id: 1, class: _, preferred-register: '' }
-  - { id: 2, class: _, preferred-register: '' }
-liveins:
-#
-body:             |
-  bb.1 (%ir-block.0):
-    liveins: $rdi
-
-    ; X64-LABEL: name: test_memop_s64
-    ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
-    ; X64: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[DEF]](p0) :: (load 8)
-    ; X64: G_STORE [[LOAD]](s64), [[DEF]](p0) :: (store 8)
-    ; X32-LABEL: name: test_memop_s64
-    ; X32: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
-    ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4, align 8)
-    ; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-    ; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C]](s32)
-    ; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p0) :: (load 4)
-    ; X32: G_STORE [[LOAD]](s32), [[DEF]](p0) :: (store 4, align 8)
-    ; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
-    ; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C1]](s32)
-    ; X32: G_STORE [[LOAD1]](s32), [[GEP1]](p0) :: (store 4)
-    %0(p0) = IMPLICIT_DEF
-    %1(s64) = G_LOAD %0(p0) :: (load 8)
-
-    G_STORE %1, %0 :: (store 8)
-
-...

diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-trunc.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-trunc.mir
index 9a13224..091c4b7 100644 (file)
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-trunc.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-trunc.mir
@@ -24,9 +24,9 @@ body:             |
     ; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
     ; X32: G_STORE [[AND]](s8), [[DEF1]](p0) :: (store 1)
     ; X32: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
-    ; X32: G_STORE [[TRUNC1]](s8), [[DEF1]](p0) :: (store 8)
+    ; X32: G_STORE [[TRUNC1]](s8), [[DEF1]](p0) :: (store 1)
     ; X32: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
-    ; X32: G_STORE [[TRUNC2]](s16), [[DEF1]](p0) :: (store 16)
+    ; X32: G_STORE [[TRUNC2]](s16), [[DEF1]](p0) :: (store 2)
     ; X32: RET 0
     ; X64-LABEL: name: trunc_check
     ; X64: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
@@ -36,9 +36,9 @@ body:             |
     ; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[C]]
     ; X64: G_STORE [[AND]](s8), [[DEF1]](p0) :: (store 1)
     ; X64: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[DEF]](s32)
-    ; X64: G_STORE [[TRUNC1]](s8), [[DEF1]](p0) :: (store 8)
+    ; X64: G_STORE [[TRUNC1]](s8), [[DEF1]](p0) :: (store 1)
     ; X64: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[DEF]](s32)
-    ; X64: G_STORE [[TRUNC2]](s16), [[DEF1]](p0) :: (store 16)
+    ; X64: G_STORE [[TRUNC2]](s16), [[DEF1]](p0) :: (store 2)
     ; X64: RET 0
     %0(s32) = IMPLICIT_DEF
     %1(s1)  = G_TRUNC %0(s32)
@@ -46,10 +46,10 @@ body:             |
     G_STORE %1, %4 :: (store 1)
 
     %2(s8)  = G_TRUNC %0(s32)
-    G_STORE %2, %4 :: (store 8)
+    G_STORE %2, %4 :: (store 1)
 
     %3(s16) = G_TRUNC %0(s32)
-    G_STORE %3, %4 :: (store 16)
+    G_STORE %3, %4 :: (store 2)
     RET 0
 
 ...

diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir b/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir
new file mode 100644 (file)
index 0000000..d4fd6e2
--- /dev/null
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir
@@ -0,0 +1,84 @@
+# RUN: llc -mtriple=i386-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=X32ALL --check-prefix=X32
+# RUN: llc -mtriple=x86_64-linux-gnux32 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=X32ALL --check-prefix=X32ABI
+
+--- |
+
+  @g_int = global i32 0, align 4
+
+  define void @test_global_ptrv() {
+  entry:
+    store i32* @g_int, i32** undef
+    ret void
+  }
+
+  define i32 @test_global_valv() {
+  entry:
+    %0 = load i32, i32* @g_int, align 4
+    ret i32 %0
+  }
+
+...
+---
+name:            test_global_ptrv
+# CHECK-LABEL: name:  test_global_ptrv
+alignment:       4
+legalized:       true
+regBankSelected: true
+# X32:                 registers:
+# X32-NEXT:              - { id: 0, class: gr32, preferred-register: '' }
+# X32-NEXT:              - { id: 1, class: gr32, preferred-register: '' }
+#
+# X32ABI:              registers:
+# X32ABI-NEXT:           - { id: 0, class: low32_addr_access, preferred-register: '' }
+# X32ABI-NEXT:           - { id: 1, class: gr32, preferred-register: '' }
+registers:
+  - { id: 0, class: gpr, preferred-register: '' }
+  - { id: 1, class: gpr, preferred-register: '' }
+# X32:                     %0:gr32 = IMPLICIT_DEF
+# X32-NEXT:                %1:gr32 = LEA32r $noreg, 1, $noreg, @g_int, $noreg
+# X32-NEXT:                MOV32mr %0, 1, $noreg, 0, $noreg, %1 :: (store 4 into `i32** undef`)
+# X32-NEXT:                RET 0
+#
+# X32ABI:                  %0:low32_addr_access = IMPLICIT_DEF
+# X32ABI-NEXT:             %1:gr32 = LEA64_32r $noreg, 1, $noreg, @g_int, $noreg
+# X32ABI-NEXT:             MOV32mr %0, 1, $noreg, 0, $noreg, %1 :: (store 4 into `i32** undef`)
+# X32ABI-NEXT:             RET 0
+body:             |
+  bb.1.entry:
+    liveins: $rdi
+
+    %0(p0) = IMPLICIT_DEF
+    %1(p0) = G_GLOBAL_VALUE @g_int
+    G_STORE %1(p0), %0(p0) :: (store 4 into `i32** undef`)
+    RET 0
+
+...
+---
+name:            test_global_valv
+# CHECK-LABEL: name:  test_global_valv
+alignment:       4
+legalized:       true
+regBankSelected: true
+# X32ALL:              registers:
+# X32ALL-NEXT:           - { id: 0, class: gr32, preferred-register: '' }
+# X32ALL-NEXT:           - { id: 1, class: gr32, preferred-register: '' }
+registers:
+  - { id: 0, class: gpr, preferred-register: '' }
+  - { id: 1, class: gpr, preferred-register: '' }
+# X32:                     %1:gr32 = LEA32r $noreg, 1, $noreg, @g_int, $noreg
+# X32-NEXT:                %0:gr32 = MOV32rm %1, 1, $noreg, 0, $noreg :: (load 4 from @g_int)
+# X32-NEXT:                $eax = COPY %0
+# X32-NEXT:                RET 0, implicit $eax
+#
+# X32ABI:                  %1:gr32 = LEA64_32r $noreg, 1, $noreg, @g_int, $noreg
+# X32ABI-NEXT:             %0:gr32 = MOV32rm %1, 1, $noreg, 0, $noreg :: (load 4 from @g_int)
+# X32ABI-NEXT:             $eax = COPY %0
+# X32ABI-NEXT:             RET 0, implicit $eax
+body:             |
+  bb.1.entry:
+    %1(p0) = G_GLOBAL_VALUE @g_int
+    %0(s32) = G_LOAD %1(p0) :: (load 4 from @g_int)
+    $eax = COPY %0(s32)
+    RET 0, implicit $eax
+
+...

diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-GV.mir b/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir
similarity index 59%
rename from llvm/test/CodeGen/X86/GlobalISel/select-GV.mir
rename to llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir
index 33eb333..830251e 100644 (file)
--- a/llvm/test/CodeGen/X86/GlobalISel/select-GV.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir
@@ -1,7 +1,5 @@
 # RUN: llc -mtriple=x86_64-linux-gnu                          -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=X64ALL --check-prefix=X64
 # RUN: llc -mtriple=x86_64-apple-darwin -relocation-model=pic -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=X64ALL --check-prefix=X64_DARWIN_PIC
-# RUN: llc -mtriple=i386-linux-gnu                            -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=X32ALL --check-prefix=X32
-# RUN: llc -mtriple=x86_64-linux-gnux32                       -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=X32ALL --check-prefix=X32ABI
 
 --- |
 
@@ -30,13 +28,6 @@ regBankSelected: true
 # X64ALL-NEXT:           - { id: 0, class: gr64, preferred-register: '' }
 # X64ALL-NEXT:           - { id: 1, class: gr64, preferred-register: '' }
 #
-# X32:                 registers:
-# X32-NEXT:              - { id: 0, class: gr32, preferred-register: '' }
-# X32-NEXT:              - { id: 1, class: gr32, preferred-register: '' }
-#
-# X32ABI:              registers:
-# X32ABI-NEXT:           - { id: 0, class: low32_addr_access, preferred-register: '' }
-# X32ABI-NEXT:           - { id: 1, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
@@ -50,15 +41,6 @@ registers:
 # X64_DARWIN_PIC-NEXT:     MOV64mr %0, 1, $noreg, 0, $noreg, %1 :: (store 8 into `i32** undef`)
 # X64_DARWIN_PIC-NEXT:     RET 0
 #
-# X32:                     %0:gr32 = IMPLICIT_DEF
-# X32-NEXT:                %1:gr32 = LEA32r $noreg, 1, $noreg, @g_int, $noreg
-# X32-NEXT:                MOV32mr %0, 1, $noreg, 0, $noreg, %1 :: (store 8 into `i32** undef`)
-# X32-NEXT:                RET 0
-#
-# X32ABI:                  %0:low32_addr_access = IMPLICIT_DEF
-# X32ABI-NEXT:             %1:gr32 = LEA64_32r $noreg, 1, $noreg, @g_int, $noreg
-# X32ABI-NEXT:             MOV32mr %0, 1, $noreg, 0, $noreg, %1 :: (store 8 into `i32** undef`)
-# X32ABI-NEXT:             RET 0
 body:             |
   bb.1.entry:
     liveins: $rdi
@@ -79,9 +61,6 @@ regBankSelected: true
 # X64ALL-NEXT:           - { id: 0, class: gr32, preferred-register: '' }
 # X64ALL-NEXT:           - { id: 1, class: gr64, preferred-register: '' }
 #
-# X32ALL:              registers:
-# X32ALL-NEXT:           - { id: 0, class: gr32, preferred-register: '' }
-# X32ALL-NEXT:           - { id: 1, class: gr32, preferred-register: '' }
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
@@ -95,15 +74,6 @@ registers:
 # X64_DARWIN_PIC-NEXT:     $eax = COPY %0
 # X64_DARWIN_PIC-NEXT:     RET 0, implicit $eax
 #
-# X32:                     %1:gr32 = LEA32r $noreg, 1, $noreg, @g_int, $noreg
-# X32-NEXT:                %0:gr32 = MOV32rm %1, 1, $noreg, 0, $noreg :: (load 4 from @g_int)
-# X32-NEXT:                $eax = COPY %0
-# X32-NEXT:                RET 0, implicit $eax
-#
-# X32ABI:                  %1:gr32 = LEA64_32r $noreg, 1, $noreg, @g_int, $noreg
-# X32ABI-NEXT:             %0:gr32 = MOV32rm %1, 1, $noreg, 0, $noreg :: (load 4 from @g_int)
-# X32ABI-NEXT:             $eax = COPY %0
-# X32ABI-NEXT:             RET 0, implicit $eax
 body:             |
   bb.1.entry:
     %1(p0) = G_GLOBAL_VALUE @g_int

diff --git a/llvm/test/Verifier/test_g_load.mir b/llvm/test/Verifier/test_g_load.mir
index 40fa21a..4378e86 100644 (file)
--- a/llvm/test/Verifier/test_g_load.mir
+++ b/llvm/test/Verifier/test_g_load.mir
@@ -1,4 +1,4 @@
-#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+#RUN: not llc -o - -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
 # REQUIRES: global-isel, aarch64-registered-target
 
 ---
@@ -15,4 +15,9 @@ body:             |
     %0:_(s64) = G_CONSTANT i32 0
     %1:_(s32) = G_LOAD %0 :: (load 4)
 
+    %2:_(p0) = G_IMPLICIT_DEF
+
+    ; CHECK: Bad machine code: load memory size cannot exceed result size
+    %3:_(s8) = G_LOAD %2 :: (load 2)
+
 ...

diff --git a/llvm/test/Verifier/test_g_store.mir b/llvm/test/Verifier/test_g_store.mir
index 132e13c..8cf144f 100644 (file)
--- a/llvm/test/Verifier/test_g_store.mir
+++ b/llvm/test/Verifier/test_g_store.mir
@@ -16,4 +16,9 @@ body:             |
     %1:_(s32) = G_CONSTANT i32 1
     G_STORE %1, %0 :: (store 4)
 
+    %2:_(p0) = G_IMPLICIT_DEF
+    %3:_(s8) = G_IMPLICIT_DEF
+    ; CHECK: Bad machine code: store memory size cannot exceed value size
+    G_STORE %3, %2 :: (store 2)
+
 ...