arm64: dts: arm: minor whitespace cleanup around '='

The DTS code coding style expects exactly one space before and after '='
sign.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230702185315.44584-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi
index 21f1f95..34bc336 100644 (file)
--- a/arch/arm64/boot/dts/arm/corstone1000.dtsi
+++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi
@@ -43,10 +43,10 @@
                #interrupt-cells = <3>;
                #address-cells = <0>;
                interrupt-controller;
-               reg =   <0x1c010000 0x1000>,
-                       <0x1c02f000 0x2000>,
-                       <0x1c04f000 0x1000>,
-                       <0x1c06f000 0x2000>;
+               reg = <0x1c010000 0x1000>,
+                     <0x1c02f000 0x2000>,
+                     <0x1c04f000 0x1000>,
+                     <0x1c06f000 0x2000>;
                interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
                              IRQ_TYPE_LEVEL_LOW)>;
        };
@@ -77,14 +77,10 @@
 
        timer {
                compatible = "arm,armv8-timer";
-               interrupts =    <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
-                                IRQ_TYPE_LEVEL_LOW)>,
-                               <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
-                                IRQ_TYPE_LEVEL_LOW)>,
-                               <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
-                                IRQ_TYPE_LEVEL_LOW)>,
-                               <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
-                                IRQ_TYPE_LEVEL_LOW)>;
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
        };
 
        uartclk: uartclk {

diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi
index e4a3c7d..17fba3b 100644 (file)
--- a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi
+++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi
@@ -12,11 +12,11 @@
                #size-cells = <1>;
                ranges = <0x0 0x0 0x2f000000 0x100000>;
                interrupt-controller;
-               reg =   <0x0 0x2f000000 0x0 0x10000>,
-                       <0x0 0x2f100000 0x0 0x200000>,
-                       <0x0 0x2c000000 0x0 0x2000>,
-                       <0x0 0x2c010000 0x0 0x2000>,
-                       <0x0 0x2c02f000 0x0 0x2000>;
+               reg = <0x0 0x2f000000 0x0 0x10000>,
+                     <0x0 0x2f100000 0x0 0x200000>,
+                     <0x0 0x2c000000 0x0 0x2000>,
+                     <0x0 0x2c010000 0x0 0x2000>,
+                     <0x0 0x2c02f000 0x0 0x2000>;
                interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 
                its: msi-controller@2f020000 {