#include <linux/i2c-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/omap-dma.h>
-#include <plat/dmtimer.h>
#include "omap_hwmod.h"
#include "l3_2xxx.h"
#include <linux/platform_data/hsmmc-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/omap-dma.h>
-#include <plat/dmtimer.h>
#include "omap_hwmod.h"
#include "l3_2xxx.h"
#include <linux/types.h>
#include <linux/omap-dma.h>
-#include <plat/dmtimer.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include "omap_hwmod.h"
.class = &iva_hwmod_class,
};
-/* always-on timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
- .timer_capability = OMAP_TIMER_ALWON,
-};
-
-/* pwm timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_PWM,
-};
-
-/* timers with DSP interrupt dev attribute */
-static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
-};
-
/* timer1 */
-
struct omap_hwmod omap2xxx_timer1_hwmod = {
.name = "timer1",
.main_clk = "gpt1_fck",
.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer2 */
-
struct omap_hwmod omap2xxx_timer2_hwmod = {
.name = "timer2",
.main_clk = "gpt2_fck",
};
/* timer3 */
-
struct omap_hwmod omap2xxx_timer3_hwmod = {
.name = "timer3",
.main_clk = "gpt3_fck",
};
/* timer4 */
-
struct omap_hwmod omap2xxx_timer4_hwmod = {
.name = "timer4",
.main_clk = "gpt4_fck",
};
/* timer5 */
-
struct omap_hwmod omap2xxx_timer5_hwmod = {
.name = "timer5",
.main_clk = "gpt5_fck",
.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
},
},
- .dev_attr = &capability_dsp_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer6 */
-
struct omap_hwmod omap2xxx_timer6_hwmod = {
.name = "timer6",
.main_clk = "gpt6_fck",
.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
},
},
- .dev_attr = &capability_dsp_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer7 */
-
struct omap_hwmod omap2xxx_timer7_hwmod = {
.name = "timer7",
.main_clk = "gpt7_fck",
.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
},
},
- .dev_attr = &capability_dsp_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer8 */
-
struct omap_hwmod omap2xxx_timer8_hwmod = {
.name = "timer8",
.main_clk = "gpt8_fck",
.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
},
},
- .dev_attr = &capability_dsp_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer9 */
-
struct omap_hwmod omap2xxx_timer9_hwmod = {
.name = "timer9",
.main_clk = "gpt9_fck",
.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer10 */
-
struct omap_hwmod omap2xxx_timer10_hwmod = {
.name = "timer10",
.main_clk = "gpt10_fck",
.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer11 */
-
struct omap_hwmod omap2xxx_timer11_hwmod = {
.name = "timer11",
.main_clk = "gpt11_fck",
.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer12 */
-
struct omap_hwmod omap2xxx_timer12_hwmod = {
.name = "timer12",
.main_clk = "gpt12_fck",
.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
.class = &omap2xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
#include "l4_3xxx.h"
#include <linux/platform_data/asoc-ti-mcbsp.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <plat/dmtimer.h>
#include "soc.h"
#include "omap_hwmod.h"
.sysc = &omap3xxx_timer_sysc,
};
-/* secure timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
- .timer_capability = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
-};
-
-/* always-on timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
- .timer_capability = OMAP_TIMER_ALWON,
-};
-
-/* pwm timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_PWM,
-};
-
-/* timers with DSP interrupt dev attribute */
-static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
-};
-
-/* pwm timers with DSP interrupt dev attribute */
-static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
-};
-
/* timer1 */
static struct omap_hwmod omap3xxx_timer1_hwmod = {
.name = "timer1",
.idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
.idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
},
},
- .dev_attr = &capability_dsp_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
.idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
},
},
- .dev_attr = &capability_dsp_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
.idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
},
},
- .dev_attr = &capability_dsp_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
.idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
},
},
- .dev_attr = &capability_dsp_pwm_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
.idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
.idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
.idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
},
},
- .dev_attr = &capability_pwm_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
/* timer12 */
-
static struct omap_hwmod omap3xxx_timer12_hwmod = {
.name = "timer12",
.main_clk = "gpt12_fck",
.idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
},
},
- .dev_attr = &capability_secure_dev_attr,
.class = &omap3xxx_timer_hwmod_class,
.flags = HWMOD_SET_DEFAULT_CLOCKACT,
};
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <plat/dmtimer.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
.sysc = &omap44xx_timer_sysc,
};
-/* always-on timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
- .timer_capability = OMAP_TIMER_ALWON,
-};
-
-/* pwm timers dev attribute */
-static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_PWM,
-};
-
-/* timers with DSP interrupt dev attribute */
-static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
-};
-
-/* pwm timers with DSP interrupt dev attribute */
-static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
- .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
-};
-
/* timer1 */
static struct omap_hwmod omap44xx_timer1_hwmod = {
.name = "timer1",
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_alwon_dev_attr,
};
/* timer2 */
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_dsp_dev_attr,
};
/* timer6 */
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_dsp_dev_attr,
};
/* timer7 */
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_dsp_dev_attr,
};
/* timer8 */
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_dsp_pwm_dev_attr,
};
/* timer9 */
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_pwm_dev_attr,
};
/* timer10 */
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_pwm_dev_attr,
};
/* timer11 */
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_pwm_dev_attr,
};
/*
#include <linux/omap-dma.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <plat/dmtimer.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
#include <linux/omap-dma.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <plat/dmtimer.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
#include <linux/platform_data/hsmmc-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <plat/dmtimer.h>
#include "omap_hwmod_common_data.h"
#include "cm81xx.h"
.sysc = &dm816x_timer_sysc,
};
-static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
- .timer_capability = OMAP_TIMER_ALWON,
-};
-
static struct omap_hwmod dm814x_timer1_hwmod = {
.name = "timer1",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "timer1_fck",
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
.flags = HWMOD_NO_IDLEST,
};
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
};
.name = "timer2",
.clkdm_name = "alwon_l3s_clkdm",
.main_clk = "timer2_fck",
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
.flags = HWMOD_NO_IDLEST,
};
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
};
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
};
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
};
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
};
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
};
.modulemode = MODULEMODE_SWCTRL,
},
},
- .dev_attr = &capability_alwon_dev_attr,
.class = &dm816x_timer_hwmod_class,
};
*/
#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
-struct omap_timer_capability_dev_attr {
- u32 timer_capability;
-};
-
struct timer_regs {
u32 tidr;
u32 tier;