[AArch64][testsuite] PR target/70004: Remove check using undefined behaviour

	PR target/70004
	* gcc.target/aarch64/scalar_shift_1.c: (test_corners_sisd_di):
	Delete.
	(test_corners_sisd_si): Likewise.
	(main): Remove checks of the above.
	* gcc.target/aarch64/shift_wide_invalid_1.c: New test.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@233964 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c4ed4ed..76c10ed 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2016-03-04  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       PR target/70004
+       * gcc.target/aarch64/scalar_shift_1.c: (test_corners_sisd_di):
+       Delete.
+       (test_corners_sisd_si): Likewise.
+       (main): Remove checks of the above.
+       * gcc.target/aarch64/shift_wide_invalid_1.c: New test.
+
 2016-03-04  Eric Botcazou  <ebotcazou@adacore.com>
 
        * gcc.dg/Wno-frame-address.c: Skip on IA-64.

diff --git a/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c b/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c
index 8465c89..7be1b12 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/scalar_shift_1.c
@@ -181,34 +181,6 @@ test_ashift_right_int_si (Int32x1 b, Int32x1 c)
 /* { dg-final { scan-assembler "asr\tw\[0-9\]+,\ w\[0-9\]+,\ 4" } } */
 /* { dg-final { scan-assembler "asr\tw\[0-9\]+,\ w\[0-9\]+,\ w\[0-9\]+" } } */
 
-Int64x1
-test_corners_sisd_di (Int64x1 b)
-{
-  force_simd_di (b);
-  b = b >> 63;
-  force_simd_di (b);
-  b = b >> 0;
-  b += b >> 65; /* { dg-warning "right shift count >= width of type" } */
-
-  return b;
-}
-/* { dg-final { scan-assembler "sshr\td\[0-9\]+,\ d\[0-9\]+,\ 63" } } */
-
-Int32x1
-test_corners_sisd_si (Int32x1 b)
-{
-  force_simd_si (b);
-  b = b >> 31;
-  force_simd_si (b);
-  b = b >> 0;
-  b += b >> 33; /* { dg-warning "right shift count >= width of type" } */
-
-  return b;
-}
-/* { dg-final { scan-assembler "sshr\tv\[0-9\]+\.2s,\ v\[0-9\]+\.2s,\ 31" } } */
-
-
-
 #define CHECK(var,val) \
 do                     \
   {                    \
@@ -236,8 +208,6 @@ main ()
   CHECK (x, 0xffffffff21524110ull);
   x = test_ashift_right_sisd_di (x, 8);
   CHECK (x, 0xffffffffffff2152ull);
-  x = test_corners_sisd_di (x);
-  CHECK (x, 0xfffffffffffffffeull);
 
   y = test_lshift_left_sisd_si (y, 4);
   CHECK (y, 0xadbeef00);
@@ -252,8 +222,6 @@ main ()
   CHECK (y, 0xffff5241);
   y = test_ashift_right_sisd_si (y, 4);
   CHECK (y, 0xffffff52);
-  y = test_corners_sisd_si (y);
-  CHECK (y, 0xfffffffe);
 
   return 0;
 }

diff --git a/gcc/testsuite/gcc.target/aarch64/shift_wide_invalid_1.c b/gcc/testsuite/gcc.target/aarch64/shift_wide_invalid_1.c
new file mode 100644 (file)
index 0000000..6b71cb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/shift_wide_invalid_1.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O" } */
+
+/* These contain undefined behavior but may trigger edge cases in the
+   vector shift patterns.  We don't check for their generation, we only
+   care about not ICEing.  */
+
+typedef long long int Int64x1;
+typedef int Int32x1;
+
+#define force_simd_di(v) asm volatile ("mov %d0, %1.d[0]" : "=w"(v) : "w"(v) :)
+#define force_simd_si(v) asm volatile ("mov %s0, %1.s[0]" : "=w"(v) : "w"(v) :)
+
+Int64x1
+foo_di (Int64x1 b)
+{
+  force_simd_di (b);
+  b = b >> 63;
+  force_simd_di (b);
+  b = b >> 0;
+  b += b >> 65; /* { dg-warning "right shift count >= width of type" } */
+
+  return b;
+}
+
+Int32x1
+foo_si (Int32x1 b)
+{
+  force_simd_si (b);
+  b = b >> 31;
+  force_simd_si (b);
+  b = b >> 0;
+  b += b >> 33; /* { dg-warning "right shift count >= width of type" } */
+
+  return b;
+}