intel/genxml: Fix typo in CCS cache flush enable

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23958>

diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index 7268f20..1f0026c 100644 (file)
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -6540,7 +6540,7 @@
     <field name="HDC Pipeline Flush Enable" start="9" end="9" type="bool" />
     <field name="L3 Read Only Cache Invalidation Enable" start="10" end="10" type="bool" />
     <field name="Untyped Data Port Cache Flush Enable" start="11" end="11" type="bool" />
-    <field name="CCSFlushEnable" start="13" end="13" type="bool" />
+    <field name="CCS Flush Enable" start="13" end="13" type="bool" />
     <field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0" />
     <field name="3D Command Opcode" start="24" end="26" type="uint" default="2" />
     <field name="Command SubType" start="27" end="28" type="uint" default="3" />