#undef DUMPREG
}
-enum dsi_complexio_power_state {
+enum dsi_cio_power_state {
DSI_COMPLEXIO_POWER_OFF = 0x0,
DSI_COMPLEXIO_POWER_ON = 0x1,
DSI_COMPLEXIO_POWER_ULPS = 0x2,
};
-static int dsi_complexio_power(enum dsi_complexio_power_state state)
+static int dsi_cio_power(enum dsi_cio_power_state state)
{
int t = 0;
return 0;
}
-static void dsi_complexio_config(struct omap_dss_device *dssdev)
+static void dsi_set_lane_config(struct omap_dss_device *dssdev)
{
u32 r;
return ddr * 1000 * 1000 / (ddr_clk / 1000);
}
-static void dsi_complexio_timings(void)
+static void dsi_cio_timings(void)
{
u32 r;
u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
dsi_write_reg(DSI_DSIPHY_CFG2, r);
}
-static void dsi_enable_lane_override(struct omap_dss_device *dssdev,
+static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
enum dsi_lane lanes)
{
int clk_lane = dssdev->phy.dsi.clk_lane;
REG_FLD_MOD(DSI_DSIPHY_CFG10, 1, 27, 27); /* ENLPTXSCPDAT */
}
-static void dsi_disable_lane_override(void)
+static void dsi_cio_disable_lane_override(void)
{
/* Disable lane override */
REG_FLD_MOD(DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
REG_FLD_MOD(DSI_DSIPHY_CFG10, 0, 22, 17); /* REGLPTXSCPDAT4TO0DXDY */
}
-static int dsi_complexio_init(struct omap_dss_device *dssdev)
+static int dsi_cio_init(struct omap_dss_device *dssdev)
{
int r = 0;
u32 l;
- DSSDBG("dsi_complexio_init\n");
+ DSSDBGF();
if (dsi.ulps_enabled)
DSSDBG("manual ulps exit\n");
goto err;
}
- dsi_complexio_config(dssdev);
+ dsi_set_lane_config(dssdev);
dsi_if_enable(true);
dsi_if_enable(false);
* manually.
*/
- dsi_enable_lane_override(dssdev,
+ dsi_cio_enable_lane_override(dssdev,
DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P);
}
- r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
+ r = dsi_cio_power(DSI_COMPLEXIO_POWER_ON);
if (r)
goto err;
/* Disable the override. The lanes should be set to Mark-11
* state by the HW */
- dsi_disable_lane_override();
+ dsi_cio_disable_lane_override();
}
/* FORCE_TX_STOP_MODE_IO */
goto err;
}
- dsi_complexio_timings();
+ dsi_cio_timings();
dsi.ulps_enabled = false;
return r;
}
-static void dsi_complexio_uninit(void)
+static void dsi_cio_uninit(void)
{
- dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
+ dsi_cio_power(DSI_COMPLEXIO_POWER_OFF);
}
static int _dsi_wait_reset(void)
dsi_unregister_isr_cio(dsi_completion_handler, &completion,
DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
- dsi_complexio_power(DSI_COMPLEXIO_POWER_ULPS);
+ dsi_cio_power(DSI_COMPLEXIO_POWER_ULPS);
dsi_if_enable(false);
if (r)
goto err2;
- r = dsi_complexio_init(dssdev);
+ r = dsi_cio_init(dssdev);
if (r)
goto err2;
return 0;
err3:
- dsi_complexio_uninit();
+ dsi_cio_uninit();
err2:
dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
dss_select_dsi_clk_source(OMAP_DSS_CLK_SRC_FCK);
dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
dss_select_dsi_clk_source(OMAP_DSS_CLK_SRC_FCK);
- dsi_complexio_uninit();
+ dsi_cio_uninit();
dsi_pll_uninit(disconnect_lanes);
}