Currently, SF->SI and DF->DI conversions on Aarch64 with the "nosimd"
flag provided sometimes cause the emitting of a vector variant of the
fcvtz[su] instruction (e.g. fcvtzu s0, s0).
This modifies the corresponding pattern to only select the vector
variant of the instruction when generating code with SIMD enabled.
gcc/ChangeLog:
* config/aarch64/aarch64.md
(<optab>_trunc<fcvt_target><GPI:mode>2): Set the "arch"
attribute to disambiguate between SIMD and FP variants of the
instruction.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/fcvt_nosimd.c: New test.
"@
fcvtz<su>\t%<s>0, %<s>1
fcvtz<su>\t%<w>0, %<s>1"
- [(set_attr "type" "neon_fp_to_int_s,f_cvtf2i")]
+ [(set_attr "type" "neon_fp_to_int_s,f_cvtf2i")
+ (set_attr "arch" "simd,fp")]
)
;; Convert HF -> SI or DI
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-march=armv8-a+nosimd" } */
+
+#include <stdint.h>
+
+uint64_t test_double_to_uint64(double x) {
+ return (uint64_t)x;
+}
+
+int64_t test_double_to_int64(double x) {
+ return (int64_t)x;
+}
+
+uint32_t test_float_to_uint32(float x) {
+ return (uint32_t)x;
+}
+
+int32_t test_float_to_int32(float x) {
+ return (int32_t)x;
+}
+
+/* { dg-final { scan-assembler-not {\tfcvtz[su]\td[0-9]*, d[0-9]*} } } */
+/* { dg-final { scan-assembler-not {\tfcvtz[su]\ts[0-9]*, s[0-9]*} } } */