dt-bindings: watchdog: starfive: Add StarFive watchdog
authorLey Foon Tan <leyfoon.tan@linux.starfivetech.com>
Tue, 28 Jun 2022 09:31:14 +0000 (09:31 +0000)
committerxingyu.wu <xingyu.wu@starfivetech.com>
Tue, 12 Jul 2022 01:46:10 +0000 (09:46 +0800)
Add dt-bindigns documentation for StarFive watchdog.

Signed-off-by: Ley Foon Tan <leyfoon.tan@linux.starfivetech.com>
Documentation/devicetree/bindings/watchdog/starfive,wdt.yaml [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/watchdog/starfive,wdt.yaml b/Documentation/devicetree/bindings/watchdog/starfive,wdt.yaml
new file mode 100644 (file)
index 0000000..eed74e0
--- /dev/null
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/maxim,max63xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive watchdog
+
+allOf:
+  - $ref: "watchdog.yaml#"
+
+maintainers:
+  - samin.guo <samin.guo@starfivetech.com>
+  - xingyu.wu <xingyu.wu@starfivetech.com>
+
+properties:
+  compatible:
+    enum:
+      - starfive,wdt
+      - starfive,dskit-wdt
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Core clock
+      - description: APB clock
+
+  clock-names:
+    items:
+      - const: core_clk
+      - const: apb_clk
+
+  resets:
+    items:
+      - description: APB reset
+      - description: Core reset
+
+  reset-names:
+    items:
+      - const: rst_apb
+      - const: rst_core
+
+  timeout-sec: true
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names  
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
+    #include <dt-bindings/reset/starfive-jh7110.h>
+
+    wdog: watchdog@13070000 {
+            compatible = "starfive,dskit-wdt";
+            reg = <0x13070000 0x10000>;
+            interrupts = <68>;
+            clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
+                     <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
+            clock-names = "core_clk", "apb_clk";
+            resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
+                     <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
+            reset-names = "rst_apb", "rst_core";
+            timeout-sec = <15>;
+    };
+