# include "atomic_ops/sysdeps/generic_pthread.h"
#endif /* AO_USE_PTHREAD_DEFS */
+#if (defined(__CC_ARM) || defined(__ARMCC__)) && !defined(__GNUC__) \
+ && !defined(AO_USE_PTHREAD_DEFS)
+# include "atomic_ops/sysdeps/armcc/arm_v6.h"
+# define AO_GENERALIZE_TWICE
+#endif
+
#if defined(__GNUC__) && !defined(AO_USE_PTHREAD_DEFS) \
&& !defined(__INTEL_COMPILER)
# if defined(__i386__)
# endif /* __arm__ */
# if defined(__cris__) || defined(CRIS)
# include "atomic_ops/sysdeps/gcc/cris.h"
+# define AO_GENERALIZE_TWICE
# endif
# if defined(__mips__)
# include "atomic_ops/sysdeps/gcc/mips.h"
# endif
#endif /* __GNUC__ && !AO_USE_PTHREAD_DEFS */
+#if (defined(__IBMC__) || defined(__IBMCPP__)) && !defined(__GNUC__) \
+ && !defined(AO_USE_PTHREAD_DEFS)
+# if defined(__powerpc__) || defined(__powerpc) || defined(__ppc__) \
+ || defined(__PPC__) || defined(_M_PPC) || defined(_ARCH_PPC) \
+ || defined(_ARCH_PWR)
+# include "atomic_ops/sysdeps/ibmc/powerpc.h"
+# define AO_GENERALIZE_TWICE
+# endif
+#endif
+
#if defined(__INTEL_COMPILER) && !defined(AO_USE_PTHREAD_DEFS)
# if defined(__ia64__)
# include "atomic_ops/sysdeps/icc/ia64.h"
# endif
#endif
+#if defined(_MSC_VER) || defined(__DMC__) || defined(__BORLANDC__) \
+ || (defined(__WATCOMC__) && defined(__NT__))
+# if defined(_AMD64_) || defined(_M_X64)
+# include "atomic_ops/sysdeps/msftc/x86_64.h"
+# elif defined(_M_IX86) || defined(x86)
+# include "atomic_ops/sysdeps/msftc/x86.h"
+# elif defined(_M_ARM) || defined(ARM) || defined(_ARM_)
+# include "atomic_ops/sysdeps/msftc/arm.h"
+# define AO_GENERALIZE_TWICE
+# endif
+#endif
+
#if defined(__sun) && !defined(__GNUC__) && !defined(AO_USE_PTHREAD_DEFS)
/* Note: use -DAO_USE_PTHREAD_DEFS if Sun CC does not handle inline asm. */
# if defined(__i386)
#if !defined(__GNUC__) && (defined(sparc) || defined(__sparc)) \
&& !defined(AO_USE_PTHREAD_DEFS)
-# include "atomic_ops/sysdeps/sunc/sparc.h"
-# define AO_CAN_EMUL_CAS
-#endif
-
-#if defined(_MSC_VER) || defined(__DMC__) || defined(__BORLANDC__) \
- || (defined(__WATCOMC__) && defined(__NT__))
-# if defined(_AMD64_) || defined(_M_X64)
-# include "atomic_ops/sysdeps/msftc/x86_64.h"
-# elif defined(_M_IX86) || defined(x86)
-# include "atomic_ops/sysdeps/msftc/x86.h"
-# elif defined(_M_ARM) || defined(ARM) || defined(_ARM_)
-# include "atomic_ops/sysdeps/msftc/arm.h"
-# endif
+# include "atomic_ops/sysdeps/sunc/sparc.h"
+# define AO_CAN_EMUL_CAS
#endif
#if defined(AO_REQUIRE_CAS) && !defined(AO_HAVE_compare_and_swap) \
# else
# error Cannot implement AO_compare_and_swap_full on this architecture.
# endif
-#endif /* AO_REQUIRE_CAS && !AO_HAVE_compare_and_swap ... */
+#endif /* AO_REQUIRE_CAS && !AO_HAVE_compare_and_swap ... */
/* The most common way to clear a test-and-set location */
/* at the end of a critical section. */
# define AO_CLEAR(addr) AO_char_store_release((AO_TS_t *)(addr), AO_TS_CLEAR)
#endif
-/*
- * The generalization section.
- * Theoretically this should repeatedly include atomic_ops_generalize.h.
- * In fact, we observe that this converges after a small fixed number
- * of iterations, usually one.
- */
+/* The generalization section. */
+#if !defined(AO_GENERALIZE_TWICE) && defined(AO_CAN_EMUL_CAS) \
+ && !defined(AO_HAVE_compare_and_swap_full)
+# define AO_GENERALIZE_TWICE
+#endif
+
+/* Theoretically we should repeatedly include atomic_ops_generalize.h. */
+/* In fact, we observe that this converges after a small fixed number */
+/* of iterations, usually one. */
#include "atomic_ops/generalize.h"
#ifdef AO_GENERALIZE_TWICE
# include "atomic_ops/generalize.h"
"
*/
AO_INLINE AO_TS_t
-AO_test_and_set(volatile AO_TS_t *addr) {
+AO_test_and_set(volatile AO_TS_t *addr)
+{
AO_TS_t oldval;
unsigned long flag;
#define AO_HAVE_compare_double_and_swap_double
#else
-/* pre ARMv6 architecures ... */
+/* pre ARMv6 architectures ... */
/* I found a slide set that, if I read it correctly, claims that */
/* Loads followed by either a Load or Store are ordered, but nothing */
#include "../all_atomic_load_store.h"
AO_INLINE AO_TS_VAL_t
-AO_test_and_set_full(volatile AO_TS_t *addr) {
+AO_test_and_set_full(volatile AO_TS_t *addr)
+{
AO_TS_VAL_t oldval;
/* SWP on ARM is very similar to XCHG on x86. */
/* The first operand is the result, the second the value */