PD#SWPL-394
Problem:
32bit system clk overflow
Solution:
let mpll clock not overflow
Verify:
gxl
Change-Id: I90c99c026264bb4d6820cd988bd5f8828456e0f6
Signed-off-by: shunzhou.jiang <shunzhou.jiang@amlogic.com>
#include "clkc.h"
/* #undef pr_debug */
/* #define pr_debug pr_info */
-#define SDM_MAX 16384
+#define SDM_MAX 16384ULL
#define MAX_RATE 500000000
#define MIN_RATE 5000000
.shift = 0,
.width = 8,
.lock = &clk_lock,
+ .flags = CLK_DIVIDER_ROUND_CLOSEST,
.hw.init = &(struct clk_init_data){
.name = "amclk_div",
.ops = &clk_divider_ops,