arm64: dts: zynqmp: Wire zynqmp qspi controller

Add missing ZynqMP qspi IP. It works in single mode only.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/5cebbc59a452f282c4ce0f0e1dffecadac8f126a.1611224800.git.michal.simek@xilinx.com

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index 7af5761..6a577e1 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -164,6 +164,10 @@
        clocks = <&zynqmp_clk PCIE_REF>;
 };
 
+&qspi {
+       clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
 &sata {
        clocks = <&zynqmp_clk SATA_REF>;
 };

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 19b349f..533c19b 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -595,6 +595,20 @@
                        };
                };
 
+               qspi: spi@ff0f0000 {
+                       compatible = "xlnx,zynqmp-qspi-1.0";
+                       status = "disabled";
+                       clock-names = "ref_clk", "pclk";
+                       interrupts = <0 15 4>;
+                       interrupt-parent = <&gic>;
+                       num-cs = <1>;
+                       reg = <0x0 0xff0f0000 0x0 0x1000>,
+                             <0x0 0xc0000000 0x0 0x8000000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       power-domains = <&zynqmp_firmware PD_QSPI>;
+               };
+
                psgtr: phy@fd400000 {
                        compatible = "xlnx,zynqmp-psgtr-v1.1";
                        status = "disabled";