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Set proper BadVAddress value for unaligned instruction fetch.
author
ths
<ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Sat, 7 Apr 2007 01:11:15 +0000
(
01:11
+0000)
committer
ths
<ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Sat, 7 Apr 2007 01:11:15 +0000
(
01:11
+0000)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2629
c046a42c
-6fe2-441c-8c8c-
71466251a162
target-mips/translate.c
patch
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diff --git
a/target-mips/translate.c
b/target-mips/translate.c
index
c646f7f
..
eaea425
100644
(file)
--- a/
target-mips/translate.c
+++ b/
target-mips/translate.c
@@
-1486,7
+1486,7
@@
static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
/* Jump to register */
if (offset != 0 && offset != 16) {
/* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the
- others are reserved. */
+
others are reserved. */
generate_exception(ctx, EXCP_RI);
return;
}
@@
-4629,6
+4629,7
@@
static void decode_opc (CPUState *env, DisasContext *ctx)
/* make sure instructions are on a word boundary */
if (ctx->pc & 0x3) {
+ env->CP0_BadVAddr = ctx->pc;
generate_exception(ctx, EXCP_AdEL);
return;
}