AC_CHECK_HEADERS([sys/sysinfo.h], AC_CHECK_MEMBERS([struct sysinfo.totalram], [], [], [[#include <sys/sysinfo.h>]]))
fi
+uxa_requires_libdrm=2.4.52
AC_ARG_ENABLE(uxa,
AS_HELP_STRING([--enable-uxa],
- [Enable Unified Acceleration Architecture (UXA) [default=yes]]),
+ [Enable Unified Acceleration Architecture (UXA) [default=auto]]),
[UXA="$enableval"],
[UXA=auto])
if test "x$UXA" = "xauto"; then
- if ! pkg-config --exists 'libdrm_intel >= 2.4.29'; then
+ if ! pkg-config --exists "libdrm_intel >= $uxa_requires_libdrm"; then
UXA=no
fi
if ! pkg-config --exists 'pixman-1 >= 0.24.0'; then
fi
if test "x$UXA" != "xno"; then
AC_DEFINE(USE_UXA, 1, [Enable UXA support])
- PKG_CHECK_MODULES(DRMINTEL, [libdrm_intel >= 2.4.29])
+ PKG_CHECK_MODULES(DRMINTEL, [libdrm_intel >= $uxa_requires_libdrm])
required_pixman_version=0.24
UXA=yes
fi
int flags;
assert (!intel->in_batch_atomic);
+ assert (INTEL_INFO(intel)->gen < 0100);
/* Big hammer, look to the pipelined flushes in future. */
if ((INTEL_INFO(intel)->gen >= 060)) {
uint32_t read_domains,
uint32_t write_domains, uint32_t delta, int needs_fence)
{
+ uint64_t offset;
+
if (needs_fence)
drm_intel_bo_emit_reloc_fence(intel->batch_bo,
intel->batch_used * 4,
bo, delta,
read_domains, write_domains);
- intel_batch_emit_dword(intel, bo->offset + delta);
+ offset = bo->offset64 + delta;
+
+ intel_batch_emit_dword(intel, offset);
+ if (INTEL_INFO(intel)->gen >= 0100)
+ intel_batch_emit_dword(intel, offset >> 32);
}
static inline void
if (INTEL_INFO(intel)->gen == -1)
return FALSE;
- if (INTEL_INFO(intel)->gen >= 0100)
- return FALSE;
-
if (xf86ReturnOptValBool(intel->Options, OPTION_ACCEL_DISABLE, FALSE) ||
!intel_option_cast_string_to_bool(intel, OPTION_ACCEL_METHOD, TRUE)) {
xf86DrvMsg(intel->scrn->scrnIndex, X_CONFIG,
intel_batch_init(scrn);
- if (INTEL_INFO(intel)->gen >= 040)
+ if (INTEL_INFO(intel)->gen >= 040 && INTEL_INFO(intel)->gen < 0100)
gen4_render_state_init(scrn);
miClearVisualTypes();
intel_batch_teardown(scrn);
- if (INTEL_INFO(intel)->gen >= 040)
+ if (INTEL_INFO(intel)->gen >= 040 && INTEL_INFO(intel)->gen < 0100)
gen4_render_state_cleanup(scrn);
xf86_cursors_fini(screen);
pitch = intel_pixmap_pitch(pixmap);
{
- BEGIN_BATCH_BLT(6);
+ int len = INTEL_INFO(intel)->gen >= 0100 ? 7 : 6;
+ BEGIN_BATCH_BLT(len);
- cmd = XY_COLOR_BLT_CMD | (6 - 2);
+ cmd = XY_COLOR_BLT_CMD | (len - 2);
if (pixmap->drawable.bitsPerPixel == 32)
cmd |=
src_pitch = intel_pixmap_pitch(intel->render_source);
{
- BEGIN_BATCH_BLT(8);
+ int len = INTEL_INFO(intel)->gen >= 0100 ? 10 : 8;
+ BEGIN_BATCH_BLT(len);
- cmd = XY_SRC_COPY_BLT_CMD | (8 - 2);
+ cmd = XY_SRC_COPY_BLT_CMD | (len - 2);
if (dest->drawable.bitsPerPixel == 32)
cmd |=
ScrnInfoPtr scrn = xf86ScreenToScrn(pixmap->drawable.pScreen);
intel_screen_private *intel = intel_get_screen_private(scrn);
- if (IS_GEN6(intel) || IS_GEN7(intel)) {
+ if (INTEL_INFO(intel)->gen >= 060) {
/* workaround a random BLT hang */
BEGIN_BATCH_BLT(3);
OUT_BATCH(XY_SETUP_CLIP_BLT_CMD | (3 - 2));
/* Composite */
if (intel_option_accel_blt(intel)) {
- } else if (IS_GEN2(intel)) {
+ } else if (INTEL_INFO(intel)->gen < 030) {
intel->uxa_driver->check_composite = i830_check_composite;
intel->uxa_driver->check_composite_target = i830_check_composite_target;
intel->uxa_driver->check_composite_texture = i830_check_composite_texture;
intel->vertex_flush = i830_vertex_flush;
intel->batch_commit_notify = i830_batch_commit_notify;
- } else if (IS_GEN3(intel)) {
+ } else if (INTEL_INFO(intel)->gen < 040) {
intel->uxa_driver->check_composite = i915_check_composite;
intel->uxa_driver->check_composite_target = i915_check_composite_target;
intel->uxa_driver->check_composite_texture = i915_check_composite_texture;
intel->vertex_flush = i915_vertex_flush;
intel->batch_commit_notify = i915_batch_commit_notify;
- } else {
+ } else if (INTEL_INFO(intel)->gen < 0100) {
intel->uxa_driver->check_composite = i965_check_composite;
intel->uxa_driver->check_composite_texture = i965_check_composite_texture;
intel->uxa_driver->prepare_composite = i965_prepare_composite;
intel->batch_flush = i965_batch_flush;
intel->batch_commit_notify = i965_batch_commit_notify;
- if (IS_GEN4(intel)) {
+ if (INTEL_INFO(intel)->gen < 050) {
intel->context_switch = gen4_context_switch;
- } else if (IS_GEN5(intel)) {
+ } else if (INTEL_INFO(intel)->gen < 060) {
intel->context_switch = gen5_context_switch;
} else {
intel->context_switch = gen6_context_switch;
*/
if (!intel->force_fallback &&
scrn->bitsPerPixel >= 16 &&
- INTEL_INFO(intel)->gen >= 030) {
+ INTEL_INFO(intel)->gen >= 030 &&
+ INTEL_INFO(intel)->gen < 0100) {
texturedAdaptor = I830SetupImageVideoTextured(screen);
if (texturedAdaptor != NULL) {
xf86DrvMsg(scrn->scrnIndex, X_INFO,