* MAINTAINERS: Added self and Andrew for the mips sim.
+2000-10-31 Ben Elliston <bje@redhat.com>
+
+ * configure.in: Match sh64, not sh5.
+ * configure: Regenerate.
+
2000-10-25 Geoff Keating <geoffk@cygnus.com>
* MAINTAINERS: Added self and Andrew for the ppc sim.
+2000-10-09 Ben Elliston <bje@redhat.com>
+
+ * configure.in: Add support for sh5.
+ * configure: Regenerate.
+
Thu Jul 27 21:26:26 2000 Andrew Cagney <cagney@b1.cygnus.com>
From Stephane Carrez <Stephane.Carrez@worldnet.fr>:
mn10200*-*-*)
sim_target=mn10200
;;
+ sh64-*-*)
+ sim_target=sh64
+ extra_subdirs="${extra_subdirs} testsuite"
+ ;;
sh*-*-*) sim_target=sh ;;
powerpc*-*-eabi* | powerpc*-*-solaris* | powerpc*-*-sysv4* | \
powerpc*-*-elf* | powerpc*-*-linux* | powerpc*-*-netbsd* )
mn10200*-*-*)
sim_target=mn10200
;;
+ sh64-*-*)
+ sim_target=sh64
+ extra_subdirs="${extra_subdirs} testsuite"
+ ;;
sh*-*-*) sim_target=sh ;;
powerpc*-*-eabi* | powerpc*-*-solaris* | powerpc*-*-sysv4* | \
powerpc*-*-elf* | powerpc*-*-linux* | powerpc*-*-netbsd* )
--- /dev/null
+2001-07-05 Ben Elliston <bje@redhat.com>
+
+ * Makefile.in (stamp-arch): Use $(CGEN_CPU_DIR).
+ (stamp-desc): Likewise.
+ (stamp-cpu): Likewise.
+ (stamp-defs-compact): Likewise.
+ (stamp-defs-media): Likewise.
+ (stamp-decode-compact): Likewise.
+ (stamp-decode-media): Likewise.
+
+2001-03-30 Ben Elliston <bje@redhat.com>
+
+ * sim-if.c (sim_open): Set sh64_idesc_{media,compact} to NULL.
+ * sh64-sim.h (sh64_idesc_{compact,media}): Declare extern.
+ * sh64.c (sh64_idesc_{compact,media}): Make non-static.
+
+2001-01-30 Ben Elliston <bje@redhat.com>
+
+ * sh64.c (SYS_argc, SYS_argn, SYS_argnlen): Define.
+ (trap_handler): Implement these syscalls.
+ (count_argc): New function.
+
+2001-01-24 Alexandre Oliva <aoliva@redhat.com>
+
+ * sh64.c (trap_handler): Implement time.
+
+ * sh64.c (fetch_str): New function.
+ (trap_handler): Re-implement write, and implement lseek, read,
+ open and close.
+
+2001-01-18 Elena Zannoni <ezannoni@kwikemart.cygnus.com>
+
+ * sh64.c (sh64_fetch_register): When fetching the PC, return the
+ PC value and set the LSB according to the current ISA.
+
+2001-01-18 Ben Elliston <bje@redhat.com>
+
+ * sh64.c (trap_handler): Use sim_engine_halt to indicate a program
+ has terminated, not exit!
+
+2001-01-12 Ben Elliston <bje@redhat.com>
+
+ * sh64.c (sh64_fcnvds): Re-implement.
+
+ * sh64.c: Include "bfd.h".
+ (trap_handler): New function. Consolidate function bodies of
+ sh64_trapa and sh64_compact_trapa.
+ (sh64_trapa): Use it.
+ (sh64_compact_trapa): Likewise.
+
+2001-01-11 Ben Elliston <bje@redhat.com>
+
+ * sem-media.c, sem-media-switch.c: Regenerate.
+ * sem-compact.c, sem-compact-switch.c: Likewise.
+
+ * sh64.c (sh64_trapa): Adhere to SH64 sys call conventions.
+
+ * cpu.h, sh-desc.c, sh-desc.h, sh-opc.h: Regenerate.
+ * decode-media.c, decode-media.h, defs-media.h: Likewise.
+ * sem-compact.c, sem-compact-switch.c: Likewise.
+ * sem-media.c, sem-media-switch.c: Likewise.
+
+2001-01-10 Ben Elliston <bje@redhat.com>
+
+ * sim-main.h (CIA_SET): Encode the current instruction set mode
+ when setting the cia.
+
+2001-01-08 Ben Elliston <bje@redhat.com>
+
+ * sh64.c (sh64_store_register): Do not set insn set mode--allow
+ sh64_h_pc_set() to do it.
+ (shmedia_init_cpu): Do not initialise the insn set mode--let the
+ loader set it based on bit 0 of the executable's starting address.
+ (shcompact_init_cpu): Likewise.
+ * mloop-compact.c (sh64_compact_pbb_begin): Emit a warning message
+ about malformed programs which have illegal insns in delay slots.
+ (sh64_compact_pbb_cti_chain): Examine the least significant bit of
+ the new pc, not the current instruction set mode to determine if
+ the next pbb in the chain will consist of SHmedia instructions.
+ * mloop-media.c (sh64_media_pbb_cti_chain): Likewise for SHcompact
+ switches. Set bit 0 when setting the pc for the next SHmedia pbb.
+
+ * cpu.c, cpu.h: Regenerate.
+ * sem-compact.c, sem-compact-switch.c: Likewise.
+ * sem-media.c, sem-media-switch.c: Likewise.
+
+ * sh64.c (sh64_compact_trapa): Use sim_io_write_{stdout,error}(),
+ not stdio functions to emit output when executing write traps.
+
+2001-01-07 Alexandre Oliva <aoliva@redhat.com>
+
+ * sh64.c (sh64_compact_trapa): Support writing to stderr. Flush
+ output stream after each (compound) write.
+
+2001-01-06 Ben Elliston <bje@redhat.com>
+
+ * sem-media.c, sem-media-switch.c: Regenerate.
+
+2001-01-04 Ben Elliston <bje@redhat.com>
+
+ * sem-compact.c, sem-compact-switch.c: Regenerate.
+ * cpu.h: Regenerate.
+
+2001-01-03 Ben Elliston <bje@redhat.com>
+
+ * cpu.c, cpu.h: Regenerate.
+ * sem-media.c, sem-media-switch.c: Likewise.
+
+2001-01-02 Ben Elliston <bje@redhat.com>
+
+ * sim-if.c (sh64_disassemble_insn): Set arch and mach fields using
+ BFD primitives.
+
+ * sem-compact.c, sem-compact-switch.c: Regenerate.
+
+2000-12-30 Alexandre Oliva <aoliva@redhat.com>
+
+ * sh64.c (sh64_nsb): Re-implement correctly.
+
+2000-12-26 Alexandre Oliva <aoliva@redhat.com>
+
+ * sh64.c (sh64_nsb): Re-implement.
+
+2000-12-27 Ben Elliston <bje@redhat.com>
+
+ * cpu.c, cpu.h: Regenerate.
+ * sem-compact.c, sem-compact-switch.c: Likewise.
+ * sem-media.c, sem-media-switch.c: Likewise.
+ * sh-desc.c: Likewise.
+
+2000-12-26 Ben Elliston <bje@redhat.com>
+
+ * mloop-compact.in, mloop-media.in: Remove.
+ * mloop-compact.c, mloop-media.c: New files.
+ * eng-compact.c, eng-media.c: Likewise.
+ * Makefile.in (mloop-compact.c): Remove target.
+ (stamp-mloop-compact): Likewise.
+ (mloop-media.c): Likewise.
+ (stamp-mloop-media): Likewise.
+ (sh64-clean): Update.
+ (stamp-mloop): Remove.
+
+2000-12-23 Ben Elliston <bje@redhat.com>
+
+ * sh64.c (sh64_prepare_run): Rename from shmedia_prepare_run.
+ (shcompact_prepare_run): Remove.
+ (sh2_mach, sh3_mach, sh3e_mach, sh4_mach, sh5_mach): Update.
+
+2000-12-22 Ben Elliston <bje@redhat.com>
+
+ * sh64.c (sh64_idesc_media, sh64_idesc_compact): New variables.
+ (sh64_dump): Remove.
+ (sh64_engine_run_full): Only compute idesc tables once.
+ (sh64_engine_run_fast): Likewise.
+ (shmedia_prepare_run): Do nothing.
+ (shcompact_prepare_run): Likewise.
+
+ * sem-compact.c, sem-compact-switch.c: Regenerate.
+ * sem-media.c, sem-media-switch.c: Likewise.
+
+2000-12-19 Ben Elliston <bje@redhat.com>
+
+ * sem-media.c, sem-media-switch.c: Regenerate.
+
+2000-12-15 Ben Elliston <bje@redhat.com>
+
+ * sh64.c (sh64_store_register): When storing a new PC, set ISA
+ mode based on the value of bit 0.
+
+ * sh64.c: Include "sim-sh64.h" for GDB interfacing.
+ (sh64_fetch_register): Implement.
+ (sh64_store_register): Likewise.
+
+ * sh64-sim.h (sh64_fmacs): Declare.
+ (sh64_ftrcdl, sh64_ftrcdq, sh64_ftrcsl): Likewise.
+
+ * sem-media.c, sem-media-switch.c: Regenerate.
+
+2000-12-13 Ben Elliston <bje@redhat.com>
+
+ * sh64-sim.h (sh64_compact_trapa): Renamed from sh64_trapa.
+ (sh64_trapa): Renamed from sh64_trap.
+ * sh64.c (sh64_trapa): Call sh64_compact_trapa for handling.
+ Apply renaming described above.
+
+ * decode-media.c, decode-media.h, defs-media.h: Regenerate.
+ * sem-media.c sem-media-switch.c: Likewise.
+ * sh-desc.c, sh-desc.h, sh-opc.h: Likewise.
+
+2000-12-12 Ben Elliston <bje@redhat.com>
+
+ * cpu.c, cpu.h, sh-desc.c: Regenerate.
+ * sem-media.c, sem-media-switch.c: Likewise.
+ * sem-compact.c, sem-compact-switch.c: Likewise.
+ * sh64-sim.h (sh64_ftrvs): Declare.
+ * sh64.c (sh64_ftrvs): Bug fixes.
+
+ * sh64.c (sh64_fcmpgtd): Fix order of arguments to sim_fpu_is_gt.
+ (sh64_fcmpgts): Likewise.
+
+2000-12-11 Ben Elliston <bje@redhat.com>
+
+ * decode-media.c, decode-media.h: Regenerate.
+ * defs-media.h: Likewise.
+ * sem-media.c, sem-media-switch.c: Likewise.
+ * sh-desc.c: Likewise.
+
+2000-12-08 Ben Elliston <bje@redhat.com>
+
+ * decode-media.c, decode-media.h: Regenerate.
+ * defs-media.h: Likewise.
+ * sem-media.c, sem-media-switch.c: Likewise.
+
+2000-12-07 Ben Elliston <bje@redhat.com>
+
+ * decode-media.c, decode-media.h: Regenerate.
+ * sem-media.c, sem-media-switch.c: Likewise.
+
+ * defs-media.h: Regenete.
+ * decode-compact.c, decode-media.c: Likewise.
+
+2000-12-06 Ben Elliston <bje@redhat.com>
+
+ * sh64.c (sh64_fcmpund): Return a BI.
+ (sh64_fcmpuns): Likewise.
+ (sh64_nsb): Treat source value as unsigned.
+ (sh64_compact_model_insn_before): New function.
+ (sh64_media_model_insn_before): Likewise.
+ (sh64_compact_model_insn_after): Likewise.
+ (sh64_media_model_insn_after): Likewise.
+ (sh_models): Use sh5_mach for "sh5".
+ * sh64-sim.h: Add missing function prototypes.
+
+ * cpu.c, cpu.h, defs-media.h, sh-desc.c: Regenerate.
+ * decode-media.c, decode-media.h: Likewise.
+ * sem-media.c, sem-media-switch.c: Likewise.
+
+2000-12-05 Ben Elliston <bje@redhat.com>
+
+ * mloop-compact.in, mloop-media.in: Use @prefix@.
+ * Makefile.in (stamp-mloop-compact): Pass -outfile-suffix option
+ to make generated files safe in the presence of parallel makes.
+ (stamp-mloop-media): Likewise.
+
+ * decode-media.c, defs-media.h: Regenerate.
+
+2000-12-04 Ben Elliston <bje@redhat.com>
+
+ * sh64-sim.h: Add function prototypes from sh64.c.
+
+ * Makefile.in (SH64_OBJS): Add ISA variant objects.
+ (SIM_EXTRA_DEPS): Do not depend on opcodes headers.
+ (SH64_INCLUDE_DEPS): Update for ISA variants.
+ (stamp-mloop-compact, stamp-mloop-media): New targets.
+ (decode-compact.o, sem-compact.o): New rules.
+ (decode-media.o, sem-media.o): Likewise.
+ (sh64-clean): Update.
+ (stamp-all, stamp-mloop, stamp-decode, stamp-defs): New targets.
+ (stamp-desc, stamp-cpu): Likewise.
+ (stamp-defs-compact, stamp-defs-media): Likewise.
+ (stamp-decode-compact, stamp-decode-media): Likewise.
+
+ * defs-compact.h, defs-media.h: Regenerate.
+
+2000-12-03 Ben Elliston <bje@redhat.com>
+
+ * sh64-sim.h (sh64_fcmpeqd, sh64_fcmpeqs): Declare.
+ (sh64_fcmpged, sh64_fcmpges): Likewise.
+ (sh64_fcmpgtd, sh64_fcmpgts): Likewise.
+
+ * sh64.c (sh64_endian): New function.
+ (sh64_fcmpeqd, sh64_fcmpeqs): Return a BI.
+ (sh64_fcmpged, sh64_fcmpges): Likewise.
+ (sh64_fcmpgtd, sh64_fcmpgts): Likewise.
+ (sh64_trap): Implement a basic syscall facility.
+ (sh64_trapa): Exit with return code in R5, not 0.
+ (sh64_model_sh5_u_exec): Remove.
+ (sh64_engine_run_full): New function.
+ (sh64_engine_run_fast): Likewise.
+ (shmedia_prepare_run): Likewise.
+ (shcompact_prepare_run): Likewise.
+ (sh64_get_idata): Likewise.
+ (sh64_init_cpu): Likewise.
+ (shmedia_init_cpu): Likewise.
+ (shcompact_init_cpu): Likewise.
+ (sh64_model_init): Likewise.
+ (sh_models): Define.
+ (sh5_imp_properties): Likewise.
+ (sh2_mach, sh3_mach, sh4_mach, sh5_mach): Define.
+
+ * sem-compact.c, sem-compact-switch.c: Regenerate.
+
+2000-12-01 Ben Elliston <bje@redhat.com>
+
+ * sh64-sim.h (sh64_endian): Declare.
+ * sim-main.h (sim_cia): Use UDI, not USI.
+ (WITH_PROFILE_MODEL_P): Remove.
+ * sim-if.c (sim_sh64_disassemble_insn): Remove.
+ (sh64_disassemble_insn): New function.
+ (sim_open): Use as this CPU's disassembler.
+ * eng.h: New file.
+ * decode.h (WITH_PROFILE_MODEL_P): Undefine.
+
+ * decode-compact.c, decode-media.c: Regenerate.
+ * defs-compact.h, defs-media.h: Likewise.
+ * sem-compact.c, sem-compact-switch.c: Likewise.
+ * sh-desc.c, sh-desc.h: Likewise.
+ * cpu.c, cpu.h, cpuall.h: Likewise.
+
+2000-11-30 Ben Elliston <bje@redhat.com>
+
+ * arch.c, sh-desc.c, sh-desc.h: Regenerate.
+
+ * tconfig.in (SIM_HAVE_BIENDIAN): Define.
+ * configure.in (SIM_AC_OPTION_BIGENDIAN): Do not hard-wire a
+ target byte order, but default to big endian.
+ * configure: Regenerate.
+
+2000-11-27 Ben Elliston <bje@redhat.com>
+
+ * sim-main.h (WITH_PROFILE_MODEL_P): Define.
+ * sh64-sim.h (ISM_COMPACT, ISM_MEDIA): New enums.
+
+ * sh-desc.c, sh-desc.h: Regenerate.
+ * arch.c, cpu.h, cpuall.h: Regenerate.
+ * decode.h (WITH_PROFILE_MODEL_P): Remove.
+
+ * mloop-compact.in, mloop-media.in: New files.
+ * decode.h: Likewise.
+
+2000-11-26 Ben Elliston <bje@redhat.com>
+
+ * sem-compact.c, sem-compact-switch.c: Generate.
+ * sem-media.c, sem-media-switch.c: Likewise.
+
+2000-11-25 Ben Elliston <bje@redhat.com>
+
+ * sh-desc.c, sh-desc.h, sh-opc.h: Generate.
+
+ * arch.c, arch.h, cpuall.h, cpu.c, cpu.h: Generate.
+ * decode-compact.c, decode-compact.h: Likewise.
+ * decode-media.c, decode-media.h: Likewise.
+ * sh64-sim.h: New file.
+ * sim-main.h: Likewise.
+
+2000-11-22 Ben Elliston <bje@redhat.com>
+
+ * sim-if.c: New file.
+ * sh64.c: Likewise.
+
+2000-11-16 Ben Elliston <bje@redhat.com>
+
+ * config.in: New file.
+ * tconfig.in: Likewise.
+ * configure.in: Likewise.
+ * configure: Generate.
+ * Makefile.in: New file.
--- /dev/null
+# Makefile template for Configure for the SH64 simulator
+# Copyright (C) 2000 Free Software Foundation, Inc.
+# Contributed by Red Hat, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+## COMMON_PRE_CONFIG_FRAG
+
+SH64_OBJS = sh64.o cpu.o sh-desc.o \
+ decode-compact.o sem-compact.o mloop-compact.o \
+ decode-media.o sem-media.o mloop-media.o
+
+CONFIG_DEVICES = dv-sockser.o
+CONFIG_DEVICES =
+
+SIM_OBJS = \
+ $(SIM_NEW_COMMON_OBJS) \
+ sim-cpu.o \
+ sim-hload.o \
+ sim-hrw.o \
+ sim-model.o \
+ sim-reg.o \
+ cgen-utils.o cgen-trace.o cgen-scache.o \
+ cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
+ sim-if.o arch.o \
+ $(SH64_OBJS) \
+ $(CONFIG_DEVICES)
+
+# Extra headers included by sim-main.h.
+SIM_EXTRA_DEPS = \
+ $(CGEN_INCLUDE_DEPS) \
+ arch.h cpuall.h sh64-sim.h
+
+SIM_EXTRA_CFLAGS =
+
+SIM_RUN_OBJS = nrun.o
+SIM_EXTRA_CLEAN = sh64-clean
+
+## COMMON_POST_CONFIG_FRAG
+
+arch = sh
+
+sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
+
+arch.o: arch.c $(SIM_MAIN_DEPS)
+
+devices.o: devices.c $(SIM_MAIN_DEPS)
+
+# SH64 objs
+
+SH64_INCLUDE_DEPS = \
+ $(CGEN_MAIN_CPU_DEPS) \
+ cpu.h decode.h \
+ decode-compact.h eng-compact.h defs-compact.h \
+ decode-media.h eng-media.h defs-media.h
+
+sh64.o: sh64.c $(SH64_INCLUDE_DEPS)
+
+mloop-compact.o: mloop-compact.c sem-compact-switch.c $(SH64_INCLUDE_DEPS)
+ $(CC) -c $(srcdir)/mloop-compact.c $(ALL_CFLAGS) -DWANT_ISA_COMPACT
+
+mloop-media.o: mloop-media.c sem-media-switch.c $(SH64_INCLUDE_DEPS)
+ $(CC) -c $(srcdir)/mloop-media.c $(ALL_CFLAGS) -DWANT_ISA_MEDIA
+
+cpu.o: cpu.c $(SH64_INCLUDE_DEPS)
+
+decode-compact.o: decode-compact.c $(SH64_INCLUDE_DEPS)
+ $(CC) -c $(srcdir)/decode-compact.c $(ALL_CFLAGS) -DWANT_ISA_COMPACT
+
+sem-compact.o: sem-compact.c $(SH64_INCLUDE_DEPS)
+ $(CC) -c $(srcdir)/sem-compact.c $(ALL_CFLAGS) -DWANT_ISA_COMPACT
+
+decode-media.o: decode-media.c $(SH64_INCLUDE_DEPS)
+ $(CC) -c $(srcdir)/decode-media.c $(ALL_CFLAGS) -DWANT_ISA_MEDIA
+
+sem-media.o: sem-media.c $(SH64_INCLUDE_DEPS)
+ $(CC) -c $(srcdir)/sem-media.c $(ALL_CFLAGS) -DWANT_ISA_MEDIA
+
+sh64-clean:
+ rm -f tmp-*
+ rm -f stamp-defs-{compact,media}
+ rm -f stamp-arch stamp-desc stamp-cpu stamp-decode-{compact,media}
+
+# cgen support, enable with --enable-cgen-maint
+CGEN_MAINT = ; @true
+# The following line is commented in or out depending upon --enable-cgen-maint.
+@CGEN_MAINT@CGEN_MAINT =
+
+.PHONY: stamp-all stamp-decode stamp-defs
+
+stamp-all: stamp-arch stamp-desc stamp-cpu stamp-decode stamp-defs
+stamp-decode: stamp-decode-compact stamp-decode-media
+stamp-defs: stamp-defs-compact stamp-defs-media
+
+stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu $(CGEN_CPU_DIR)/sh64-compact.cpu Makefile
+ $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all isa=compact,media \
+ FLAGS="with-scache"
+ touch $@
+arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
+ @true
+
+stamp-desc: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu Makefile
+ $(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) cpu=sh64 mach=all isa=compact,media
+ touch $@
+desc.h: $(CGEN_MAINT) stamp-desc
+ @true
+
+stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu $(CGEN_CPU_DIR)/sh64-media.cpu Makefile
+ $(MAKE) cgen-cpu $(CGEN_FLAGS_TO_PASS) \
+ cpu=sh64 mach=sh4,sh5 isa=compact,media FLAGS="with-multiple-isa with-scache"
+ rm -f $(srcdir)/model.c
+ touch $@
+cpu.h: $(CGEN_MAINT) stamp-cpu
+ @true
+
+stamp-defs-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu Makefile
+ $(MAKE) cgen-defs $(CGEN_FLAGS_TO_PASS) \
+ cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact"
+ touch $@
+defs-compact.h: $(CGEN_MAINT) stamp-defs-compact
+ @true
+
+stamp-defs-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu Makefile
+ $(MAKE) cgen-defs $(CGEN_FLAGS_TO_PASS) \
+ cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media"
+ touch $@
+defs-media.h: $(CGEN_MAINT) stamp-defs-media
+
+stamp-decode-compact: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-compact.cpu Makefile
+ $(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \
+ cpu=sh64 mach=sh5 isa=compact FLAGS="with-scache" SUFFIX="-compact" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
+ touch $@
+sem-compact.c sem-compact-switch.c decode-compact.c decode-compact.h: $(CGEN_MAINT) stamp-compact
+ @true
+
+stamp-decode-media: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/sh.cpu $(CGEN_CPU_DIR)/sh.opc $(CGEN_CPU_DIR)/sh64-media.cpu Makefile
+ $(MAKE) cgen-decode $(CGEN_FLAGS_TO_PASS) \
+ cpu=sh64 mach=sh5 isa=media FLAGS="with-scache" SUFFIX="-media" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
+ touch $@
+sem-media.c sem-media-switch.c decode-media.c decode-media.h: $(CGEN_MAINT) stamp-media
+ @true
--- /dev/null
+/* Simulator support for sh.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sim-main.h"
+#include "bfd.h"
+
+const MACH *sim_machs[] =
+{
+#ifdef HAVE_CPU_SH64
+ & sh2_mach,
+#endif
+#ifdef HAVE_CPU_SH64
+ & sh3_mach,
+#endif
+#ifdef HAVE_CPU_SH64
+ & sh3e_mach,
+#endif
+#ifdef HAVE_CPU_SH64
+ & sh4_mach,
+#endif
+#ifdef HAVE_CPU_SH64
+ & sh5_mach,
+#endif
+ 0
+};
+
--- /dev/null
+/* Simulator header for sh.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef SH_ARCH_H
+#define SH_ARCH_H
+
+#define TARGET_BIG_ENDIAN 1
+
+/* Enum declaration for model types. */
+typedef enum model_type {
+ MODEL_SH5, MODEL_MAX
+} MODEL_TYPE;
+
+#define MAX_MODELS ((int) MODEL_MAX)
+
+/* Enum declaration for unit types. */
+typedef enum unit_type {
+ UNIT_NONE, UNIT_SH5_U_EXEC, UNIT_MAX
+} UNIT_TYPE;
+
+#define MAX_UNITS (1)
+
+#endif /* SH_ARCH_H */
--- /dev/null
+/* config.in. Generated automatically from configure.in by autoheader. */
+
+/* Define if using alloca.c. */
+#undef C_ALLOCA
+
+/* Define to empty if the keyword does not work. */
+#undef const
+
+/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
+ This function is required for alloca.c support on those systems. */
+#undef CRAY_STACKSEG_END
+
+/* Define if you have alloca, as a function or macro. */
+#undef HAVE_ALLOCA
+
+/* Define if you have <alloca.h> and it should be used (not on Ultrix). */
+#undef HAVE_ALLOCA_H
+
+/* Define if you have a working `mmap' system call. */
+#undef HAVE_MMAP
+
+/* Define as __inline if that's what the C compiler calls it. */
+#undef inline
+
+/* Define to `long' if <sys/types.h> doesn't define. */
+#undef off_t
+
+/* Define if you need to in order for stat and other things to work. */
+#undef _POSIX_SOURCE
+
+/* Define as the return type of signal handlers (int or void). */
+#undef RETSIGTYPE
+
+/* Define to `unsigned' if <sys/types.h> doesn't define. */
+#undef size_t
+
+/* If using the C implementation of alloca, define if you know the
+ direction of stack growth for your system; otherwise it will be
+ automatically deduced at run-time.
+ STACK_DIRECTION > 0 => grows toward higher addresses
+ STACK_DIRECTION < 0 => grows toward lower addresses
+ STACK_DIRECTION = 0 => direction of growth unknown
+ */
+#undef STACK_DIRECTION
+
+/* Define if you have the ANSI C header files. */
+#undef STDC_HEADERS
+
+/* Define if your processor stores words with the most significant
+ byte first (like Motorola and SPARC, unlike Intel and VAX). */
+#undef WORDS_BIGENDIAN
+
+/* Define to 1 if NLS is requested. */
+#undef ENABLE_NLS
+
+/* Define as 1 if you have gettext and don't want to use GNU gettext. */
+#undef HAVE_GETTEXT
+
+/* Define as 1 if you have the stpcpy function. */
+#undef HAVE_STPCPY
+
+/* Define if your locale.h file contains LC_MESSAGES. */
+#undef HAVE_LC_MESSAGES
+
+/* Define if you have the __argz_count function. */
+#undef HAVE___ARGZ_COUNT
+
+/* Define if you have the __argz_next function. */
+#undef HAVE___ARGZ_NEXT
+
+/* Define if you have the __argz_stringify function. */
+#undef HAVE___ARGZ_STRINGIFY
+
+/* Define if you have the __setfpucw function. */
+#undef HAVE___SETFPUCW
+
+/* Define if you have the dcgettext function. */
+#undef HAVE_DCGETTEXT
+
+/* Define if you have the getcwd function. */
+#undef HAVE_GETCWD
+
+/* Define if you have the getpagesize function. */
+#undef HAVE_GETPAGESIZE
+
+/* Define if you have the getrusage function. */
+#undef HAVE_GETRUSAGE
+
+/* Define if you have the munmap function. */
+#undef HAVE_MUNMAP
+
+/* Define if you have the putenv function. */
+#undef HAVE_PUTENV
+
+/* Define if you have the setenv function. */
+#undef HAVE_SETENV
+
+/* Define if you have the setlocale function. */
+#undef HAVE_SETLOCALE
+
+/* Define if you have the sigaction function. */
+#undef HAVE_SIGACTION
+
+/* Define if you have the stpcpy function. */
+#undef HAVE_STPCPY
+
+/* Define if you have the strcasecmp function. */
+#undef HAVE_STRCASECMP
+
+/* Define if you have the strchr function. */
+#undef HAVE_STRCHR
+
+/* Define if you have the time function. */
+#undef HAVE_TIME
+
+/* Define if you have the <argz.h> header file. */
+#undef HAVE_ARGZ_H
+
+/* Define if you have the <dlfcn.h> header file. */
+#undef HAVE_DLFCN_H
+
+/* Define if you have the <errno.h> header file. */
+#undef HAVE_ERRNO_H
+
+/* Define if you have the <fcntl.h> header file. */
+#undef HAVE_FCNTL_H
+
+/* Define if you have the <fpu_control.h> header file. */
+#undef HAVE_FPU_CONTROL_H
+
+/* Define if you have the <limits.h> header file. */
+#undef HAVE_LIMITS_H
+
+/* Define if you have the <locale.h> header file. */
+#undef HAVE_LOCALE_H
+
+/* Define if you have the <malloc.h> header file. */
+#undef HAVE_MALLOC_H
+
+/* Define if you have the <nl_types.h> header file. */
+#undef HAVE_NL_TYPES_H
+
+/* Define if you have the <stdlib.h> header file. */
+#undef HAVE_STDLIB_H
+
+/* Define if you have the <string.h> header file. */
+#undef HAVE_STRING_H
+
+/* Define if you have the <strings.h> header file. */
+#undef HAVE_STRINGS_H
+
+/* Define if you have the <sys/param.h> header file. */
+#undef HAVE_SYS_PARAM_H
+
+/* Define if you have the <sys/resource.h> header file. */
+#undef HAVE_SYS_RESOURCE_H
+
+/* Define if you have the <sys/stat.h> header file. */
+#undef HAVE_SYS_STAT_H
+
+/* Define if you have the <sys/time.h> header file. */
+#undef HAVE_SYS_TIME_H
+
+/* Define if you have the <time.h> header file. */
+#undef HAVE_TIME_H
+
+/* Define if you have the <unistd.h> header file. */
+#undef HAVE_UNISTD_H
+
+/* Define if you have the <values.h> header file. */
+#undef HAVE_VALUES_H
+
+/* Define if you have the nsl library (-lnsl). */
+#undef HAVE_LIBNSL
+
+/* Define if you have the socket library (-lsocket). */
+#undef HAVE_LIBSOCKET
--- /dev/null
+#! /bin/sh
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+sim_inline="-DDEFAULT_INLINE=0"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+# This file is derived from `gettext.m4'. The difference is that the
+# included macros assume Cygnus-style source and build trees.
+
+# Macro to add for using GNU gettext.
+# Ulrich Drepper <drepper@cygnus.com>, 1995.
+#
+# This file file be copied and used freely without restrictions. It can
+# be used in projects which are not available under the GNU Public License
+# but which still want to provide support for the GNU gettext functionality.
+# Please note that the actual code is *not* freely available.
+
+# serial 3
+
+
+
+
+
+# Search path for a program which passes the given test.
+# Ulrich Drepper <drepper@cygnus.com>, 1996.
+#
+# This file file be copied and used freely without restrictions. It can
+# be used in projects which are not available under the GNU Public License
+# but which still want to provide support for the GNU gettext functionality.
+# Please note that the actual code is *not* freely available.
+
+# serial 1
+
+
+
+# Check whether LC_MESSAGES is available in <locale.h>.
+# Ulrich Drepper <drepper@cygnus.com>, 1995.
+#
+# This file file be copied and used freely without restrictions. It can
+# be used in projects which are not available under the GNU Public License
+# but which still want to provide support for the GNU gettext functionality.
+# Please note that the actual code is *not* freely available.
+
+# serial 1
+
+
+
+
+
+
+# Guess values for system-dependent variables and create Makefiles.
+# Generated automatically using autoconf version 2.13
+# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc.
+#
+# This configure script is free software; the Free Software Foundation
+# gives unlimited permission to copy, distribute and modify it.
+
+# Defaults:
+ac_help=
+ac_default_prefix=/usr/local
+# Any additions from configure.in:
+ac_help="$ac_help
+ --disable-nls do not use Native Language Support"
+ac_help="$ac_help
+ --with-included-gettext use the GNU gettext library included here"
+ac_help="$ac_help
+ --enable-maintainer-mode Enable developer functionality."
+ac_help="$ac_help
+ --enable-sim-bswap Use Host specific BSWAP instruction."
+ac_help="$ac_help
+ --enable-sim-cflags=opts Extra CFLAGS for use in building simulator"
+ac_help="$ac_help
+ --enable-sim-debug=opts Enable debugging flags"
+ac_help="$ac_help
+ --enable-sim-stdio Specify whether to use stdio for console input/output."
+ac_help="$ac_help
+ --enable-sim-trace=opts Enable tracing flags"
+ac_help="$ac_help
+ --enable-sim-profile=opts Enable profiling flags"
+ac_help="$ac_help
+ --enable-sim-endian=endian Specify target byte endian orientation."
+ac_help="$ac_help
+ --enable-sim-alignment=align Specify strict, nonstrict or forced alignment of memory accesses."
+ac_help="$ac_help
+ --enable-sim-hostendian=end Specify host byte endian orientation."
+ac_help="$ac_help
+ --enable-sim-scache=size Specify simulator execution cache size."
+ac_help="$ac_help
+ --enable-sim-default-model=model Specify default model to simulate."
+ac_help="$ac_help
+ --enable-sim-environment=environment Specify mixed, user, virtual or operating environment."
+ac_help="$ac_help
+ --enable-sim-inline=inlines Specify which functions should be inlined."
+ac_help="$ac_help
+ --enable-cgen-maint[=DIR] build cgen generated files"
+
+# Initialize some variables set by options.
+# The variables have the same names as the options, with
+# dashes changed to underlines.
+build=NONE
+cache_file=./config.cache
+exec_prefix=NONE
+host=NONE
+no_create=
+nonopt=NONE
+no_recursion=
+prefix=NONE
+program_prefix=NONE
+program_suffix=NONE
+program_transform_name=s,x,x,
+silent=
+site=
+sitefile=
+srcdir=
+target=NONE
+verbose=
+x_includes=NONE
+x_libraries=NONE
+bindir='${exec_prefix}/bin'
+sbindir='${exec_prefix}/sbin'
+libexecdir='${exec_prefix}/libexec'
+datadir='${prefix}/share'
+sysconfdir='${prefix}/etc'
+sharedstatedir='${prefix}/com'
+localstatedir='${prefix}/var'
+libdir='${exec_prefix}/lib'
+includedir='${prefix}/include'
+oldincludedir='/usr/include'
+infodir='${prefix}/info'
+mandir='${prefix}/man'
+
+# Initialize some other variables.
+subdirs=
+MFLAGS= MAKEFLAGS=
+SHELL=${CONFIG_SHELL-/bin/sh}
+# Maximum number of lines to put in a shell here document.
+ac_max_here_lines=12
+
+ac_prev=
+for ac_option
+do
+
+ # If the previous option needs an argument, assign it.
+ if test -n "$ac_prev"; then
+ eval "$ac_prev=\$ac_option"
+ ac_prev=
+ continue
+ fi
+
+ case "$ac_option" in
+ -*=*) ac_optarg=`echo "$ac_option" | sed 's/[-_a-zA-Z0-9]*=//'` ;;
+ *) ac_optarg= ;;
+ esac
+
+ # Accept the important Cygnus configure options, so we can diagnose typos.
+
+ case "$ac_option" in
+
+ -bindir | --bindir | --bindi | --bind | --bin | --bi)
+ ac_prev=bindir ;;
+ -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
+ bindir="$ac_optarg" ;;
+
+ -build | --build | --buil | --bui | --bu)
+ ac_prev=build ;;
+ -build=* | --build=* | --buil=* | --bui=* | --bu=*)
+ build="$ac_optarg" ;;
+
+ -cache-file | --cache-file | --cache-fil | --cache-fi \
+ | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
+ ac_prev=cache_file ;;
+ -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
+ | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
+ cache_file="$ac_optarg" ;;
+
+ -datadir | --datadir | --datadi | --datad | --data | --dat | --da)
+ ac_prev=datadir ;;
+ -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \
+ | --da=*)
+ datadir="$ac_optarg" ;;
+
+ -disable-* | --disable-*)
+ ac_feature=`echo $ac_option|sed -e 's/-*disable-//'`
+ # Reject names that are not valid shell variable names.
+ if test -n "`echo $ac_feature| sed 's/[-a-zA-Z0-9_]//g'`"; then
+ { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; }
+ fi
+ ac_feature=`echo $ac_feature| sed 's/-/_/g'`
+ eval "enable_${ac_feature}=no" ;;
+
+ -enable-* | --enable-*)
+ ac_feature=`echo $ac_option|sed -e 's/-*enable-//' -e 's/=.*//'`
+ # Reject names that are not valid shell variable names.
+ if test -n "`echo $ac_feature| sed 's/[-_a-zA-Z0-9]//g'`"; then
+ { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; }
+ fi
+ ac_feature=`echo $ac_feature| sed 's/-/_/g'`
+ case "$ac_option" in
+ *=*) ;;
+ *) ac_optarg=yes ;;
+ esac
+ eval "enable_${ac_feature}='$ac_optarg'" ;;
+
+ -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
+ | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
+ | --exec | --exe | --ex)
+ ac_prev=exec_prefix ;;
+ -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
+ | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
+ | --exec=* | --exe=* | --ex=*)
+ exec_prefix="$ac_optarg" ;;
+
+ -gas | --gas | --ga | --g)
+ # Obsolete; use --with-gas.
+ with_gas=yes ;;
+
+ -help | --help | --hel | --he)
+ # Omit some internal or obsolete options to make the list less imposing.
+ # This message is too long to be a string in the A/UX 3.1 sh.
+ cat << EOF
+Usage: configure [options] [host]
+Options: [defaults in brackets after descriptions]
+Configuration:
+ --cache-file=FILE cache test results in FILE
+ --help print this message
+ --no-create do not create output files
+ --quiet, --silent do not print \`checking...' messages
+ --site-file=FILE use FILE as the site file
+ --version print the version of autoconf that created configure
+Directory and file names:
+ --prefix=PREFIX install architecture-independent files in PREFIX
+ [$ac_default_prefix]
+ --exec-prefix=EPREFIX install architecture-dependent files in EPREFIX
+ [same as prefix]
+ --bindir=DIR user executables in DIR [EPREFIX/bin]
+ --sbindir=DIR system admin executables in DIR [EPREFIX/sbin]
+ --libexecdir=DIR program executables in DIR [EPREFIX/libexec]
+ --datadir=DIR read-only architecture-independent data in DIR
+ [PREFIX/share]
+ --sysconfdir=DIR read-only single-machine data in DIR [PREFIX/etc]
+ --sharedstatedir=DIR modifiable architecture-independent data in DIR
+ [PREFIX/com]
+ --localstatedir=DIR modifiable single-machine data in DIR [PREFIX/var]
+ --libdir=DIR object code libraries in DIR [EPREFIX/lib]
+ --includedir=DIR C header files in DIR [PREFIX/include]
+ --oldincludedir=DIR C header files for non-gcc in DIR [/usr/include]
+ --infodir=DIR info documentation in DIR [PREFIX/info]
+ --mandir=DIR man documentation in DIR [PREFIX/man]
+ --srcdir=DIR find the sources in DIR [configure dir or ..]
+ --program-prefix=PREFIX prepend PREFIX to installed program names
+ --program-suffix=SUFFIX append SUFFIX to installed program names
+ --program-transform-name=PROGRAM
+ run sed PROGRAM on installed program names
+EOF
+ cat << EOF
+Host type:
+ --build=BUILD configure for building on BUILD [BUILD=HOST]
+ --host=HOST configure for HOST [guessed]
+ --target=TARGET configure for TARGET [TARGET=HOST]
+Features and packages:
+ --disable-FEATURE do not include FEATURE (same as --enable-FEATURE=no)
+ --enable-FEATURE[=ARG] include FEATURE [ARG=yes]
+ --with-PACKAGE[=ARG] use PACKAGE [ARG=yes]
+ --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no)
+ --x-includes=DIR X include files are in DIR
+ --x-libraries=DIR X library files are in DIR
+EOF
+ if test -n "$ac_help"; then
+ echo "--enable and --with options recognized:$ac_help"
+ fi
+ exit 0 ;;
+
+ -host | --host | --hos | --ho)
+ ac_prev=host ;;
+ -host=* | --host=* | --hos=* | --ho=*)
+ host="$ac_optarg" ;;
+
+ -includedir | --includedir | --includedi | --included | --include \
+ | --includ | --inclu | --incl | --inc)
+ ac_prev=includedir ;;
+ -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \
+ | --includ=* | --inclu=* | --incl=* | --inc=*)
+ includedir="$ac_optarg" ;;
+
+ -infodir | --infodir | --infodi | --infod | --info | --inf)
+ ac_prev=infodir ;;
+ -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*)
+ infodir="$ac_optarg" ;;
+
+ -libdir | --libdir | --libdi | --libd)
+ ac_prev=libdir ;;
+ -libdir=* | --libdir=* | --libdi=* | --libd=*)
+ libdir="$ac_optarg" ;;
+
+ -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \
+ | --libexe | --libex | --libe)
+ ac_prev=libexecdir ;;
+ -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \
+ | --libexe=* | --libex=* | --libe=*)
+ libexecdir="$ac_optarg" ;;
+
+ -localstatedir | --localstatedir | --localstatedi | --localstated \
+ | --localstate | --localstat | --localsta | --localst \
+ | --locals | --local | --loca | --loc | --lo)
+ ac_prev=localstatedir ;;
+ -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \
+ | --localstate=* | --localstat=* | --localsta=* | --localst=* \
+ | --locals=* | --local=* | --loca=* | --loc=* | --lo=*)
+ localstatedir="$ac_optarg" ;;
+
+ -mandir | --mandir | --mandi | --mand | --man | --ma | --m)
+ ac_prev=mandir ;;
+ -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*)
+ mandir="$ac_optarg" ;;
+
+ -nfp | --nfp | --nf)
+ # Obsolete; use --without-fp.
+ with_fp=no ;;
+
+ -no-create | --no-create | --no-creat | --no-crea | --no-cre \
+ | --no-cr | --no-c)
+ no_create=yes ;;
+
+ -no-recursion | --no-recursion | --no-recursio | --no-recursi \
+ | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r)
+ no_recursion=yes ;;
+
+ -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \
+ | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \
+ | --oldin | --oldi | --old | --ol | --o)
+ ac_prev=oldincludedir ;;
+ -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \
+ | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \
+ | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*)
+ oldincludedir="$ac_optarg" ;;
+
+ -prefix | --prefix | --prefi | --pref | --pre | --pr | --p)
+ ac_prev=prefix ;;
+ -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*)
+ prefix="$ac_optarg" ;;
+
+ -program-prefix | --program-prefix | --program-prefi | --program-pref \
+ | --program-pre | --program-pr | --program-p)
+ ac_prev=program_prefix ;;
+ -program-prefix=* | --program-prefix=* | --program-prefi=* \
+ | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*)
+ program_prefix="$ac_optarg" ;;
+
+ -program-suffix | --program-suffix | --program-suffi | --program-suff \
+ | --program-suf | --program-su | --program-s)
+ ac_prev=program_suffix ;;
+ -program-suffix=* | --program-suffix=* | --program-suffi=* \
+ | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*)
+ program_suffix="$ac_optarg" ;;
+
+ -program-transform-name | --program-transform-name \
+ | --program-transform-nam | --program-transform-na \
+ | --program-transform-n | --program-transform- \
+ | --program-transform | --program-transfor \
+ | --program-transfo | --program-transf \
+ | --program-trans | --program-tran \
+ | --progr-tra | --program-tr | --program-t)
+ ac_prev=program_transform_name ;;
+ -program-transform-name=* | --program-transform-name=* \
+ | --program-transform-nam=* | --program-transform-na=* \
+ | --program-transform-n=* | --program-transform-=* \
+ | --program-transform=* | --program-transfor=* \
+ | --program-transfo=* | --program-transf=* \
+ | --program-trans=* | --program-tran=* \
+ | --progr-tra=* | --program-tr=* | --program-t=*)
+ program_transform_name="$ac_optarg" ;;
+
+ -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+ | -silent | --silent | --silen | --sile | --sil)
+ silent=yes ;;
+
+ -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
+ ac_prev=sbindir ;;
+ -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
+ | --sbi=* | --sb=*)
+ sbindir="$ac_optarg" ;;
+
+ -sharedstatedir | --sharedstatedir | --sharedstatedi \
+ | --sharedstated | --sharedstate | --sharedstat | --sharedsta \
+ | --sharedst | --shareds | --shared | --share | --shar \
+ | --sha | --sh)
+ ac_prev=sharedstatedir ;;
+ -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \
+ | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \
+ | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \
+ | --sha=* | --sh=*)
+ sharedstatedir="$ac_optarg" ;;
+
+ -site | --site | --sit)
+ ac_prev=site ;;
+ -site=* | --site=* | --sit=*)
+ site="$ac_optarg" ;;
+
+ -site-file | --site-file | --site-fil | --site-fi | --site-f)
+ ac_prev=sitefile ;;
+ -site-file=* | --site-file=* | --site-fil=* | --site-fi=* | --site-f=*)
+ sitefile="$ac_optarg" ;;
+
+ -srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
+ ac_prev=srcdir ;;
+ -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
+ srcdir="$ac_optarg" ;;
+
+ -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \
+ | --syscon | --sysco | --sysc | --sys | --sy)
+ ac_prev=sysconfdir ;;
+ -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \
+ | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*)
+ sysconfdir="$ac_optarg" ;;
+
+ -target | --target | --targe | --targ | --tar | --ta | --t)
+ ac_prev=target ;;
+ -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*)
+ target="$ac_optarg" ;;
+
+ -v | -verbose | --verbose | --verbos | --verbo | --verb)
+ verbose=yes ;;
+
+ -version | --version | --versio | --versi | --vers)
+ echo "configure generated by autoconf version 2.13"
+ exit 0 ;;
+
+ -with-* | --with-*)
+ ac_package=`echo $ac_option|sed -e 's/-*with-//' -e 's/=.*//'`
+ # Reject names that are not valid shell variable names.
+ if test -n "`echo $ac_package| sed 's/[-_a-zA-Z0-9]//g'`"; then
+ { echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; }
+ fi
+ ac_package=`echo $ac_package| sed 's/-/_/g'`
+ case "$ac_option" in
+ *=*) ;;
+ *) ac_optarg=yes ;;
+ esac
+ eval "with_${ac_package}='$ac_optarg'" ;;
+
+ -without-* | --without-*)
+ ac_package=`echo $ac_option|sed -e 's/-*without-//'`
+ # Reject names that are not valid shell variable names.
+ if test -n "`echo $ac_package| sed 's/[-a-zA-Z0-9_]//g'`"; then
+ { echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; }
+ fi
+ ac_package=`echo $ac_package| sed 's/-/_/g'`
+ eval "with_${ac_package}=no" ;;
+
+ --x)
+ # Obsolete; use --with-x.
+ with_x=yes ;;
+
+ -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \
+ | --x-incl | --x-inc | --x-in | --x-i)
+ ac_prev=x_includes ;;
+ -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \
+ | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*)
+ x_includes="$ac_optarg" ;;
+
+ -x-libraries | --x-libraries | --x-librarie | --x-librari \
+ | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l)
+ ac_prev=x_libraries ;;
+ -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \
+ | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*)
+ x_libraries="$ac_optarg" ;;
+
+ -*) { echo "configure: error: $ac_option: invalid option; use --help to show usage" 1>&2; exit 1; }
+ ;;
+
+ *)
+ if test -n "`echo $ac_option| sed 's/[-a-z0-9.]//g'`"; then
+ echo "configure: warning: $ac_option: invalid host type" 1>&2
+ fi
+ if test "x$nonopt" != xNONE; then
+ { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; }
+ fi
+ nonopt="$ac_option"
+ ;;
+
+ esac
+done
+
+if test -n "$ac_prev"; then
+ { echo "configure: error: missing argument to --`echo $ac_prev | sed 's/_/-/g'`" 1>&2; exit 1; }
+fi
+
+trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
+
+# File descriptor usage:
+# 0 standard input
+# 1 file creation
+# 2 errors and warnings
+# 3 some systems may open it to /dev/tty
+# 4 used on the Kubota Titan
+# 6 checking for... messages and results
+# 5 compiler messages saved in config.log
+if test "$silent" = yes; then
+ exec 6>/dev/null
+else
+ exec 6>&1
+fi
+exec 5>./config.log
+
+echo "\
+This file contains any messages produced by compilers while
+running configure, to aid debugging if configure makes a mistake.
+" 1>&5
+
+# Strip out --no-create and --no-recursion so they do not pile up.
+# Also quote any args containing shell metacharacters.
+ac_configure_args=
+for ac_arg
+do
+ case "$ac_arg" in
+ -no-create | --no-create | --no-creat | --no-crea | --no-cre \
+ | --no-cr | --no-c) ;;
+ -no-recursion | --no-recursion | --no-recursio | --no-recursi \
+ | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) ;;
+ *" "*|*" "*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?]*)
+ ac_configure_args="$ac_configure_args '$ac_arg'" ;;
+ *) ac_configure_args="$ac_configure_args $ac_arg" ;;
+ esac
+done
+
+# NLS nuisances.
+# Only set these to C if already set. These must not be set unconditionally
+# because not all systems understand e.g. LANG=C (notably SCO).
+# Fixing LC_MESSAGES prevents Solaris sh from translating var values in `set'!
+# Non-C LC_CTYPE values break the ctype check.
+if test "${LANG+set}" = set; then LANG=C; export LANG; fi
+if test "${LC_ALL+set}" = set; then LC_ALL=C; export LC_ALL; fi
+if test "${LC_MESSAGES+set}" = set; then LC_MESSAGES=C; export LC_MESSAGES; fi
+if test "${LC_CTYPE+set}" = set; then LC_CTYPE=C; export LC_CTYPE; fi
+
+# confdefs.h avoids OS command line length limits that DEFS can exceed.
+rm -rf conftest* confdefs.h
+# AIX cpp loses on an empty file, so make sure it contains at least a newline.
+echo > confdefs.h
+
+# A filename unique to this package, relative to the directory that
+# configure is in, which we can look for to find out if srcdir is correct.
+ac_unique_file=Makefile.in
+
+# Find the source files, if location was not specified.
+if test -z "$srcdir"; then
+ ac_srcdir_defaulted=yes
+ # Try the directory containing this script, then its parent.
+ ac_prog=$0
+ ac_confdir=`echo $ac_prog|sed 's%/[^/][^/]*$%%'`
+ test "x$ac_confdir" = "x$ac_prog" && ac_confdir=.
+ srcdir=$ac_confdir
+ if test ! -r $srcdir/$ac_unique_file; then
+ srcdir=..
+ fi
+else
+ ac_srcdir_defaulted=no
+fi
+if test ! -r $srcdir/$ac_unique_file; then
+ if test "$ac_srcdir_defaulted" = yes; then
+ { echo "configure: error: can not find sources in $ac_confdir or .." 1>&2; exit 1; }
+ else
+ { echo "configure: error: can not find sources in $srcdir" 1>&2; exit 1; }
+ fi
+fi
+srcdir=`echo "${srcdir}" | sed 's%\([^/]\)/*$%\1%'`
+
+# Prefer explicitly selected file to automatically selected ones.
+if test -z "$sitefile"; then
+ if test -z "$CONFIG_SITE"; then
+ if test "x$prefix" != xNONE; then
+ CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
+ else
+ CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
+ fi
+ fi
+else
+ CONFIG_SITE="$sitefile"
+fi
+for ac_site_file in $CONFIG_SITE; do
+ if test -r "$ac_site_file"; then
+ echo "loading site script $ac_site_file"
+ . "$ac_site_file"
+ fi
+done
+
+if test -r "$cache_file"; then
+ echo "loading cache $cache_file"
+ . $cache_file
+else
+ echo "creating cache $cache_file"
+ > $cache_file
+fi
+
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+ac_exeext=
+ac_objext=o
+if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null; then
+ # Stardent Vistra SVR4 grep lacks -e, says ghazi@caip.rutgers.edu.
+ if (echo -n testing; echo 1,2,3) | sed s/-n/xn/ | grep xn >/dev/null; then
+ ac_n= ac_c='
+' ac_t=' '
+ else
+ ac_n=-n ac_c= ac_t=
+ fi
+else
+ ac_n= ac_c='\c' ac_t=
+fi
+
+
+
+echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6
+echo "configure:695: checking how to run the C preprocessor" >&5
+# On Suns, sometimes $CPP names a directory.
+if test -n "$CPP" && test -d "$CPP"; then
+ CPP=
+fi
+if test -z "$CPP"; then
+if eval "test \"`echo '$''{'ac_cv_prog_CPP'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ # This must be in double quotes, not single quotes, because CPP may get
+ # substituted into the Makefile and "${CC-cc}" will confuse make.
+ CPP="${CC-cc} -E"
+ # On the NeXT, cc -E runs the code through the compiler's parser,
+ # not just through cpp.
+ cat > conftest.$ac_ext <<EOF
+#line 710 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:716: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ :
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ CPP="${CC-cc} -E -traditional-cpp"
+ cat > conftest.$ac_ext <<EOF
+#line 727 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:733: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ :
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ CPP="${CC-cc} -nologo -E"
+ cat > conftest.$ac_ext <<EOF
+#line 744 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:750: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ :
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ CPP=/lib/cpp
+fi
+rm -f conftest*
+fi
+rm -f conftest*
+fi
+rm -f conftest*
+ ac_cv_prog_CPP="$CPP"
+fi
+ CPP="$ac_cv_prog_CPP"
+else
+ ac_cv_prog_CPP="$CPP"
+fi
+echo "$ac_t""$CPP" 1>&6
+
+echo $ac_n "checking whether ${MAKE-make} sets \${MAKE}""... $ac_c" 1>&6
+echo "configure:775: checking whether ${MAKE-make} sets \${MAKE}" >&5
+set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_prog_make_${ac_make}_set'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftestmake <<\EOF
+all:
+ @echo 'ac_maketemp="${MAKE}"'
+EOF
+# GNU make sometimes prints "make[1]: Entering...", which would confuse us.
+eval `${MAKE-make} -f conftestmake 2>/dev/null | grep temp=`
+if test -n "$ac_maketemp"; then
+ eval ac_cv_prog_make_${ac_make}_set=yes
+else
+ eval ac_cv_prog_make_${ac_make}_set=no
+fi
+rm -f conftestmake
+fi
+if eval "test \"`echo '$ac_cv_prog_make_'${ac_make}_set`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ SET_MAKE=
+else
+ echo "$ac_t""no" 1>&6
+ SET_MAKE="MAKE=${MAKE-make}"
+fi
+
+echo $ac_n "checking for POSIXized ISC""... $ac_c" 1>&6
+echo "configure:802: checking for POSIXized ISC" >&5
+if test -d /etc/conf/kconfig.d &&
+ grep _POSIX_VERSION /usr/include/sys/unistd.h >/dev/null 2>&1
+then
+ echo "$ac_t""yes" 1>&6
+ ISC=yes # If later tests want to check for ISC.
+ cat >> confdefs.h <<\EOF
+#define _POSIX_SOURCE 1
+EOF
+
+ if test "$GCC" = yes; then
+ CC="$CC -posix"
+ else
+ CC="$CC -Xp"
+ fi
+else
+ echo "$ac_t""no" 1>&6
+ ISC=
+fi
+
+echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6
+echo "configure:823: checking for ANSI C header files" >&5
+if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 828 "configure"
+#include "confdefs.h"
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include <float.h>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:836: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ rm -rf conftest*
+ ac_cv_header_stdc=yes
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+if test $ac_cv_header_stdc = yes; then
+ # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
+cat > conftest.$ac_ext <<EOF
+#line 853 "configure"
+#include "confdefs.h"
+#include <string.h>
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+ egrep "memchr" >/dev/null 2>&1; then
+ :
+else
+ rm -rf conftest*
+ ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+ # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
+cat > conftest.$ac_ext <<EOF
+#line 871 "configure"
+#include "confdefs.h"
+#include <stdlib.h>
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+ egrep "free" >/dev/null 2>&1; then
+ :
+else
+ rm -rf conftest*
+ ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+ # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
+if test "$cross_compiling" = yes; then
+ :
+else
+ cat > conftest.$ac_ext <<EOF
+#line 892 "configure"
+#include "confdefs.h"
+#include <ctype.h>
+#define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
+#define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
+#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
+int main () { int i; for (i = 0; i < 256; i++)
+if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2);
+exit (0); }
+
+EOF
+if { (eval echo configure:903: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+ :
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -fr conftest*
+ ac_cv_header_stdc=no
+fi
+rm -fr conftest*
+fi
+
+fi
+fi
+
+echo "$ac_t""$ac_cv_header_stdc" 1>&6
+if test $ac_cv_header_stdc = yes; then
+ cat >> confdefs.h <<\EOF
+#define STDC_HEADERS 1
+EOF
+
+fi
+
+echo $ac_n "checking for working const""... $ac_c" 1>&6
+echo "configure:927: checking for working const" >&5
+if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 932 "configure"
+#include "confdefs.h"
+
+int main() {
+
+/* Ultrix mips cc rejects this. */
+typedef int charset[2]; const charset x;
+/* SunOS 4.1.1 cc rejects this. */
+char const *const *ccp;
+char **p;
+/* NEC SVR4.0.2 mips cc rejects this. */
+struct point {int x, y;};
+static struct point const zero = {0,0};
+/* AIX XL C 1.02.0.0 rejects this.
+ It does not let you subtract one const X* pointer from another in an arm
+ of an if-expression whose if-part is not a constant expression */
+const char *g = "string";
+ccp = &g + (g ? g-g : 0);
+/* HPUX 7.0 cc rejects these. */
+++ccp;
+p = (char**) ccp;
+ccp = (char const *const *) p;
+{ /* SCO 3.2v4 cc rejects this. */
+ char *t;
+ char const *s = 0 ? (char *) 0 : (char const *) 0;
+
+ *t++ = 0;
+}
+{ /* Someone thinks the Sun supposedly-ANSI compiler will reject this. */
+ int x[] = {25, 17};
+ const int *foo = &x[0];
+ ++foo;
+}
+{ /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */
+ typedef const int *iptr;
+ iptr p = 0;
+ ++p;
+}
+{ /* AIX XL C 1.02.0.0 rejects this saying
+ "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */
+ struct s { int j; const int *ap[3]; };
+ struct s *b; b->j = 5;
+}
+{ /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */
+ const int foo = 10;
+}
+
+; return 0; }
+EOF
+if { (eval echo configure:981: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+ rm -rf conftest*
+ ac_cv_c_const=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ ac_cv_c_const=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_c_const" 1>&6
+if test $ac_cv_c_const = no; then
+ cat >> confdefs.h <<\EOF
+#define const
+EOF
+
+fi
+
+echo $ac_n "checking for inline""... $ac_c" 1>&6
+echo "configure:1002: checking for inline" >&5
+if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ ac_cv_c_inline=no
+for ac_kw in inline __inline__ __inline; do
+ cat > conftest.$ac_ext <<EOF
+#line 1009 "configure"
+#include "confdefs.h"
+
+int main() {
+} $ac_kw foo() {
+; return 0; }
+EOF
+if { (eval echo configure:1016: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+ rm -rf conftest*
+ ac_cv_c_inline=$ac_kw; break
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+fi
+rm -f conftest*
+done
+
+fi
+
+echo "$ac_t""$ac_cv_c_inline" 1>&6
+case "$ac_cv_c_inline" in
+ inline | yes) ;;
+ no) cat >> confdefs.h <<\EOF
+#define inline
+EOF
+ ;;
+ *) cat >> confdefs.h <<EOF
+#define inline $ac_cv_c_inline
+EOF
+ ;;
+esac
+
+echo $ac_n "checking for off_t""... $ac_c" 1>&6
+echo "configure:1042: checking for off_t" >&5
+if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1047 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#if STDC_HEADERS
+#include <stdlib.h>
+#include <stddef.h>
+#endif
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+ egrep "(^|[^a-zA-Z_0-9])off_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
+ rm -rf conftest*
+ ac_cv_type_off_t=yes
+else
+ rm -rf conftest*
+ ac_cv_type_off_t=no
+fi
+rm -f conftest*
+
+fi
+echo "$ac_t""$ac_cv_type_off_t" 1>&6
+if test $ac_cv_type_off_t = no; then
+ cat >> confdefs.h <<\EOF
+#define off_t long
+EOF
+
+fi
+
+echo $ac_n "checking for size_t""... $ac_c" 1>&6
+echo "configure:1075: checking for size_t" >&5
+if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1080 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#if STDC_HEADERS
+#include <stdlib.h>
+#include <stddef.h>
+#endif
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+ egrep "(^|[^a-zA-Z_0-9])size_t[^a-zA-Z_0-9]" >/dev/null 2>&1; then
+ rm -rf conftest*
+ ac_cv_type_size_t=yes
+else
+ rm -rf conftest*
+ ac_cv_type_size_t=no
+fi
+rm -f conftest*
+
+fi
+echo "$ac_t""$ac_cv_type_size_t" 1>&6
+if test $ac_cv_type_size_t = no; then
+ cat >> confdefs.h <<\EOF
+#define size_t unsigned
+EOF
+
+fi
+
+# The Ultrix 4.2 mips builtin alloca declared by alloca.h only works
+# for constant arguments. Useless!
+echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6
+echo "configure:1110: checking for working alloca.h" >&5
+if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1115 "configure"
+#include "confdefs.h"
+#include <alloca.h>
+int main() {
+char *p = alloca(2 * sizeof(int));
+; return 0; }
+EOF
+if { (eval echo configure:1122: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ rm -rf conftest*
+ ac_cv_header_alloca_h=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ ac_cv_header_alloca_h=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_header_alloca_h" 1>&6
+if test $ac_cv_header_alloca_h = yes; then
+ cat >> confdefs.h <<\EOF
+#define HAVE_ALLOCA_H 1
+EOF
+
+fi
+
+echo $ac_n "checking for alloca""... $ac_c" 1>&6
+echo "configure:1143: checking for alloca" >&5
+if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1148 "configure"
+#include "confdefs.h"
+
+#ifdef __GNUC__
+# define alloca __builtin_alloca
+#else
+# ifdef _MSC_VER
+# include <malloc.h>
+# define alloca _alloca
+# else
+# if HAVE_ALLOCA_H
+# include <alloca.h>
+# else
+# ifdef _AIX
+ #pragma alloca
+# else
+# ifndef alloca /* predefined by HP cc +Olibcalls */
+char *alloca ();
+# endif
+# endif
+# endif
+# endif
+#endif
+
+int main() {
+char *p = (char *) alloca(1);
+; return 0; }
+EOF
+if { (eval echo configure:1176: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ rm -rf conftest*
+ ac_cv_func_alloca_works=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ ac_cv_func_alloca_works=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_func_alloca_works" 1>&6
+if test $ac_cv_func_alloca_works = yes; then
+ cat >> confdefs.h <<\EOF
+#define HAVE_ALLOCA 1
+EOF
+
+fi
+
+if test $ac_cv_func_alloca_works = no; then
+ # The SVR3 libPW and SVR4 libucb both contain incompatible functions
+ # that cause trouble. Some versions do not even contain alloca or
+ # contain a buggy version. If you still want to use their alloca,
+ # use ar to extract alloca.o from them instead of compiling alloca.c.
+ ALLOCA=alloca.${ac_objext}
+ cat >> confdefs.h <<\EOF
+#define C_ALLOCA 1
+EOF
+
+
+echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6
+echo "configure:1208: checking whether alloca needs Cray hooks" >&5
+if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1213 "configure"
+#include "confdefs.h"
+#if defined(CRAY) && ! defined(CRAY2)
+webecray
+#else
+wenotbecray
+#endif
+
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+ egrep "webecray" >/dev/null 2>&1; then
+ rm -rf conftest*
+ ac_cv_os_cray=yes
+else
+ rm -rf conftest*
+ ac_cv_os_cray=no
+fi
+rm -f conftest*
+
+fi
+
+echo "$ac_t""$ac_cv_os_cray" 1>&6
+if test $ac_cv_os_cray = yes; then
+for ac_func in _getb67 GETB67 getb67; do
+ echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:1238: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1243 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+ which can conflict with char $ac_func(); below. */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error. */
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+ to always fail with ENOSYS. Some functions are actually named
+ something starting with __ and the normal name is an alias. */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:1266: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ rm -rf conftest*
+ eval "ac_cv_func_$ac_func=yes"
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ cat >> confdefs.h <<EOF
+#define CRAY_STACKSEG_END $ac_func
+EOF
+
+ break
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+done
+fi
+
+echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6
+echo "configure:1293: checking stack direction for C alloca" >&5
+if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if test "$cross_compiling" = yes; then
+ ac_cv_c_stack_direction=0
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1301 "configure"
+#include "confdefs.h"
+find_stack_direction ()
+{
+ static char *addr = 0;
+ auto char dummy;
+ if (addr == 0)
+ {
+ addr = &dummy;
+ return find_stack_direction ();
+ }
+ else
+ return (&dummy > addr) ? 1 : -1;
+}
+main ()
+{
+ exit (find_stack_direction() < 0);
+}
+EOF
+if { (eval echo configure:1320: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+ ac_cv_c_stack_direction=1
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -fr conftest*
+ ac_cv_c_stack_direction=-1
+fi
+rm -fr conftest*
+fi
+
+fi
+
+echo "$ac_t""$ac_cv_c_stack_direction" 1>&6
+cat >> confdefs.h <<EOF
+#define STACK_DIRECTION $ac_cv_c_stack_direction
+EOF
+
+fi
+
+for ac_hdr in unistd.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:1345: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1350 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:1355: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=yes"
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_func in getpagesize
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:1384: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1389 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+ which can conflict with char $ac_func(); below. */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error. */
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+ to always fail with ENOSYS. Some functions are actually named
+ something starting with __ and the normal name is an alias. */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:1412: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ rm -rf conftest*
+ eval "ac_cv_func_$ac_func=yes"
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+done
+
+echo $ac_n "checking for working mmap""... $ac_c" 1>&6
+echo "configure:1437: checking for working mmap" >&5
+if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if test "$cross_compiling" = yes; then
+ ac_cv_func_mmap_fixed_mapped=no
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1445 "configure"
+#include "confdefs.h"
+
+/* Thanks to Mike Haertel and Jim Avera for this test.
+ Here is a matrix of mmap possibilities:
+ mmap private not fixed
+ mmap private fixed at somewhere currently unmapped
+ mmap private fixed at somewhere already mapped
+ mmap shared not fixed
+ mmap shared fixed at somewhere currently unmapped
+ mmap shared fixed at somewhere already mapped
+ For private mappings, we should verify that changes cannot be read()
+ back from the file, nor mmap's back from the file at a different
+ address. (There have been systems where private was not correctly
+ implemented like the infamous i386 svr4.0, and systems where the
+ VM page cache was not coherent with the filesystem buffer cache
+ like early versions of FreeBSD and possibly contemporary NetBSD.)
+ For shared mappings, we should conversely verify that changes get
+ propogated back to all the places they're supposed to be.
+
+ Grep wants private fixed already mapped.
+ The main things grep needs to know about mmap are:
+ * does it exist and is it safe to write into the mmap'd area
+ * how to use it (BSD variants) */
+#include <sys/types.h>
+#include <fcntl.h>
+#include <sys/mman.h>
+
+/* This mess was copied from the GNU getpagesize.h. */
+#ifndef HAVE_GETPAGESIZE
+# ifdef HAVE_UNISTD_H
+# include <unistd.h>
+# endif
+
+/* Assume that all systems that can run configure have sys/param.h. */
+# ifndef HAVE_SYS_PARAM_H
+# define HAVE_SYS_PARAM_H 1
+# endif
+
+# ifdef _SC_PAGESIZE
+# define getpagesize() sysconf(_SC_PAGESIZE)
+# else /* no _SC_PAGESIZE */
+# ifdef HAVE_SYS_PARAM_H
+# include <sys/param.h>
+# ifdef EXEC_PAGESIZE
+# define getpagesize() EXEC_PAGESIZE
+# else /* no EXEC_PAGESIZE */
+# ifdef NBPG
+# define getpagesize() NBPG * CLSIZE
+# ifndef CLSIZE
+# define CLSIZE 1
+# endif /* no CLSIZE */
+# else /* no NBPG */
+# ifdef NBPC
+# define getpagesize() NBPC
+# else /* no NBPC */
+# ifdef PAGESIZE
+# define getpagesize() PAGESIZE
+# endif /* PAGESIZE */
+# endif /* no NBPC */
+# endif /* no NBPG */
+# endif /* no EXEC_PAGESIZE */
+# else /* no HAVE_SYS_PARAM_H */
+# define getpagesize() 8192 /* punt totally */
+# endif /* no HAVE_SYS_PARAM_H */
+# endif /* no _SC_PAGESIZE */
+
+#endif /* no HAVE_GETPAGESIZE */
+
+#ifdef __cplusplus
+extern "C" { void *malloc(unsigned); }
+#else
+char *malloc();
+#endif
+
+int
+main()
+{
+ char *data, *data2, *data3;
+ int i, pagesize;
+ int fd;
+
+ pagesize = getpagesize();
+
+ /*
+ * First, make a file with some known garbage in it.
+ */
+ data = malloc(pagesize);
+ if (!data)
+ exit(1);
+ for (i = 0; i < pagesize; ++i)
+ *(data + i) = rand();
+ umask(0);
+ fd = creat("conftestmmap", 0600);
+ if (fd < 0)
+ exit(1);
+ if (write(fd, data, pagesize) != pagesize)
+ exit(1);
+ close(fd);
+
+ /*
+ * Next, try to mmap the file at a fixed address which
+ * already has something else allocated at it. If we can,
+ * also make sure that we see the same garbage.
+ */
+ fd = open("conftestmmap", O_RDWR);
+ if (fd < 0)
+ exit(1);
+ data2 = malloc(2 * pagesize);
+ if (!data2)
+ exit(1);
+ data2 += (pagesize - ((int) data2 & (pagesize - 1))) & (pagesize - 1);
+ if (data2 != mmap(data2, pagesize, PROT_READ | PROT_WRITE,
+ MAP_PRIVATE | MAP_FIXED, fd, 0L))
+ exit(1);
+ for (i = 0; i < pagesize; ++i)
+ if (*(data + i) != *(data2 + i))
+ exit(1);
+
+ /*
+ * Finally, make sure that changes to the mapped area
+ * do not percolate back to the file as seen by read().
+ * (This is a bug on some variants of i386 svr4.0.)
+ */
+ for (i = 0; i < pagesize; ++i)
+ *(data2 + i) = *(data2 + i) + 1;
+ data3 = malloc(pagesize);
+ if (!data3)
+ exit(1);
+ if (read(fd, data3, pagesize) != pagesize)
+ exit(1);
+ for (i = 0; i < pagesize; ++i)
+ if (*(data + i) != *(data3 + i))
+ exit(1);
+ close(fd);
+ unlink("conftestmmap");
+ exit(0);
+}
+
+EOF
+if { (eval echo configure:1585: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+ ac_cv_func_mmap_fixed_mapped=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -fr conftest*
+ ac_cv_func_mmap_fixed_mapped=no
+fi
+rm -fr conftest*
+fi
+
+fi
+
+echo "$ac_t""$ac_cv_func_mmap_fixed_mapped" 1>&6
+if test $ac_cv_func_mmap_fixed_mapped = yes; then
+ cat >> confdefs.h <<\EOF
+#define HAVE_MMAP 1
+EOF
+
+fi
+
+echo $ac_n "checking for Cygwin environment""... $ac_c" 1>&6
+echo "configure:1608: checking for Cygwin environment" >&5
+if eval "test \"`echo '$''{'ac_cv_cygwin'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1613 "configure"
+#include "confdefs.h"
+
+int main() {
+
+#ifndef __CYGWIN__
+#define __CYGWIN__ __CYGWIN32__
+#endif
+return __CYGWIN__;
+; return 0; }
+EOF
+if { (eval echo configure:1624: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+ rm -rf conftest*
+ ac_cv_cygwin=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ ac_cv_cygwin=no
+fi
+rm -f conftest*
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_cygwin" 1>&6
+CYGWIN=
+test "$ac_cv_cygwin" = yes && CYGWIN=yes
+echo $ac_n "checking for mingw32 environment""... $ac_c" 1>&6
+echo "configure:1641: checking for mingw32 environment" >&5
+if eval "test \"`echo '$''{'ac_cv_mingw32'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1646 "configure"
+#include "confdefs.h"
+
+int main() {
+return __MINGW32__;
+; return 0; }
+EOF
+if { (eval echo configure:1653: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+ rm -rf conftest*
+ ac_cv_mingw32=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ ac_cv_mingw32=no
+fi
+rm -f conftest*
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_mingw32" 1>&6
+MINGW32=
+test "$ac_cv_mingw32" = yes && MINGW32=yes
+
+# autoconf.info says this should be called right after AC_INIT.
+
+
+ac_aux_dir=
+for ac_dir in `cd $srcdir;pwd`/../.. $srcdir/`cd $srcdir;pwd`/../..; do
+ if test -f $ac_dir/install-sh; then
+ ac_aux_dir=$ac_dir
+ ac_install_sh="$ac_aux_dir/install-sh -c"
+ break
+ elif test -f $ac_dir/install.sh; then
+ ac_aux_dir=$ac_dir
+ ac_install_sh="$ac_aux_dir/install.sh -c"
+ break
+ fi
+done
+if test -z "$ac_aux_dir"; then
+ { echo "configure: error: can not find install-sh or install.sh in `cd $srcdir;pwd`/../.. $srcdir/`cd $srcdir;pwd`/../.." 1>&2; exit 1; }
+fi
+ac_config_guess=$ac_aux_dir/config.guess
+ac_config_sub=$ac_aux_dir/config.sub
+ac_configure=$ac_aux_dir/configure # This should be Cygnus configure.
+
+
+# Do some error checking and defaulting for the host and target type.
+# The inputs are:
+# configure --host=HOST --target=TARGET --build=BUILD NONOPT
+#
+# The rules are:
+# 1. You are not allowed to specify --host, --target, and nonopt at the
+# same time.
+# 2. Host defaults to nonopt.
+# 3. If nonopt is not specified, then host defaults to the current host,
+# as determined by config.guess.
+# 4. Target and build default to nonopt.
+# 5. If nonopt is not specified, then target and build default to host.
+
+# The aliases save the names the user supplied, while $host etc.
+# will get canonicalized.
+case $host---$target---$nonopt in
+NONE---*---* | *---NONE---* | *---*---NONE) ;;
+*) { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } ;;
+esac
+
+
+# Make sure we can run config.sub.
+if ${CONFIG_SHELL-/bin/sh} $ac_config_sub sun4 >/dev/null 2>&1; then :
+else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; }
+fi
+
+echo $ac_n "checking host system type""... $ac_c" 1>&6
+echo "configure:1720: checking host system type" >&5
+
+host_alias=$host
+case "$host_alias" in
+NONE)
+ case $nonopt in
+ NONE)
+ if host_alias=`${CONFIG_SHELL-/bin/sh} $ac_config_guess`; then :
+ else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; }
+ fi ;;
+ *) host_alias=$nonopt ;;
+ esac ;;
+esac
+
+host=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $host_alias`
+host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+echo "$ac_t""$host" 1>&6
+
+echo $ac_n "checking target system type""... $ac_c" 1>&6
+echo "configure:1741: checking target system type" >&5
+
+target_alias=$target
+case "$target_alias" in
+NONE)
+ case $nonopt in
+ NONE) target_alias=$host_alias ;;
+ *) target_alias=$nonopt ;;
+ esac ;;
+esac
+
+target=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $target_alias`
+target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+echo "$ac_t""$target" 1>&6
+
+echo $ac_n "checking build system type""... $ac_c" 1>&6
+echo "configure:1759: checking build system type" >&5
+
+build_alias=$build
+case "$build_alias" in
+NONE)
+ case $nonopt in
+ NONE) build_alias=$host_alias ;;
+ *) build_alias=$nonopt ;;
+ esac ;;
+esac
+
+build=`${CONFIG_SHELL-/bin/sh} $ac_config_sub $build_alias`
+build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+echo "$ac_t""$build" 1>&6
+
+test "$host_alias" != "$target_alias" &&
+ test "$program_prefix$program_suffix$program_transform_name" = \
+ NONENONEs,x,x, &&
+ program_prefix=${target_alias}-
+
+if test "$program_transform_name" = s,x,x,; then
+ program_transform_name=
+else
+ # Double any \ or $. echo might interpret backslashes.
+ cat <<\EOF_SED > conftestsed
+s,\\,\\\\,g; s,\$,$$,g
+EOF_SED
+ program_transform_name="`echo $program_transform_name|sed -f conftestsed`"
+ rm -f conftestsed
+fi
+test "$program_prefix" != NONE &&
+ program_transform_name="s,^,${program_prefix},; $program_transform_name"
+# Use a double $ so make ignores it.
+test "$program_suffix" != NONE &&
+ program_transform_name="s,\$\$,${program_suffix},; $program_transform_name"
+
+# sed with no file args requires a program.
+test "$program_transform_name" = "" && program_transform_name="s,x,x,"
+
+# Extract the first word of "gcc", so it can be a program name with args.
+set dummy gcc; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1803: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":"
+ ac_dummy="$PATH"
+ for ac_dir in $ac_dummy; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ ac_cv_prog_CC="gcc"
+ break
+ fi
+ done
+ IFS="$ac_save_ifs"
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+ echo "$ac_t""$CC" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+if test -z "$CC"; then
+ # Extract the first word of "cc", so it can be a program name with args.
+set dummy cc; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1833: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":"
+ ac_prog_rejected=no
+ ac_dummy="$PATH"
+ for ac_dir in $ac_dummy; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then
+ ac_prog_rejected=yes
+ continue
+ fi
+ ac_cv_prog_CC="cc"
+ break
+ fi
+ done
+ IFS="$ac_save_ifs"
+if test $ac_prog_rejected = yes; then
+ # We found a bogon in the path, so make sure we never use it.
+ set dummy $ac_cv_prog_CC
+ shift
+ if test $# -gt 0; then
+ # We chose a different compiler from the bogus one.
+ # However, it has the same basename, so the bogon will be chosen
+ # first if we set CC to just the basename; use the full file name.
+ shift
+ set dummy "$ac_dir/$ac_word" "$@"
+ shift
+ ac_cv_prog_CC="$@"
+ fi
+fi
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+ echo "$ac_t""$CC" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+ if test -z "$CC"; then
+ case "`uname -s`" in
+ *win32* | *WIN32*)
+ # Extract the first word of "cl", so it can be a program name with args.
+set dummy cl; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1884: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":"
+ ac_dummy="$PATH"
+ for ac_dir in $ac_dummy; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ ac_cv_prog_CC="cl"
+ break
+ fi
+ done
+ IFS="$ac_save_ifs"
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+ echo "$ac_t""$CC" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+ ;;
+ esac
+ fi
+ test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; }
+fi
+
+echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
+echo "configure:1916: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
+
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+cat > conftest.$ac_ext << EOF
+
+#line 1927 "configure"
+#include "confdefs.h"
+
+main(){return(0);}
+EOF
+if { (eval echo configure:1932: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ ac_cv_prog_cc_works=yes
+ # If we can't run a trivial program, we are probably using a cross compiler.
+ if (./conftest; exit) 2>/dev/null; then
+ ac_cv_prog_cc_cross=no
+ else
+ ac_cv_prog_cc_cross=yes
+ fi
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ ac_cv_prog_cc_works=no
+fi
+rm -fr conftest*
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+echo "$ac_t""$ac_cv_prog_cc_works" 1>&6
+if test $ac_cv_prog_cc_works = no; then
+ { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
+fi
+echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
+echo "configure:1958: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
+echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
+cross_compiling=$ac_cv_prog_cc_cross
+
+echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
+echo "configure:1963: checking whether we are using GNU C" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.c <<EOF
+#ifdef __GNUC__
+ yes;
+#endif
+EOF
+if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1972: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
+ ac_cv_prog_gcc=yes
+else
+ ac_cv_prog_gcc=no
+fi
+fi
+
+echo "$ac_t""$ac_cv_prog_gcc" 1>&6
+
+if test $ac_cv_prog_gcc = yes; then
+ GCC=yes
+else
+ GCC=
+fi
+
+ac_test_CFLAGS="${CFLAGS+set}"
+ac_save_CFLAGS="$CFLAGS"
+CFLAGS=
+echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
+echo "configure:1991: checking whether ${CC-cc} accepts -g" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ echo 'void f(){}' > conftest.c
+if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then
+ ac_cv_prog_cc_g=yes
+else
+ ac_cv_prog_cc_g=no
+fi
+rm -f conftest*
+
+fi
+
+echo "$ac_t""$ac_cv_prog_cc_g" 1>&6
+if test "$ac_test_CFLAGS" = set; then
+ CFLAGS="$ac_save_CFLAGS"
+elif test $ac_cv_prog_cc_g = yes; then
+ if test "$GCC" = yes; then
+ CFLAGS="-g -O2"
+ else
+ CFLAGS="-g"
+ fi
+else
+ if test "$GCC" = yes; then
+ CFLAGS="-O2"
+ else
+ CFLAGS=
+ fi
+fi
+
+# Find a good install program. We prefer a C program (faster),
+# so one script is as good as another. But avoid the broken or
+# incompatible versions:
+# SysV /etc/install, /usr/sbin/install
+# SunOS /usr/etc/install
+# IRIX /sbin/install
+# AIX /bin/install
+# AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag
+# AFS /usr/afsws/bin/install, which mishandles nonexistent args
+# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
+# ./install, which can be erroneously created by make from ./install.sh.
+echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
+echo "configure:2034: checking for a BSD compatible install" >&5
+if test -z "$INSTALL"; then
+if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ IFS="${IFS= }"; ac_save_IFS="$IFS"; IFS=":"
+ for ac_dir in $PATH; do
+ # Account for people who put trailing slashes in PATH elements.
+ case "$ac_dir/" in
+ /|./|.//|/etc/*|/usr/sbin/*|/usr/etc/*|/sbin/*|/usr/afsws/bin/*|/usr/ucb/*) ;;
+ *)
+ # OSF1 and SCO ODT 3.0 have their own names for install.
+ # Don't use installbsd from OSF since it installs stuff as root
+ # by default.
+ for ac_prog in ginstall scoinst install; do
+ if test -f $ac_dir/$ac_prog; then
+ if test $ac_prog = install &&
+ grep dspmsg $ac_dir/$ac_prog >/dev/null 2>&1; then
+ # AIX install. It has an incompatible calling convention.
+ :
+ else
+ ac_cv_path_install="$ac_dir/$ac_prog -c"
+ break 2
+ fi
+ fi
+ done
+ ;;
+ esac
+ done
+ IFS="$ac_save_IFS"
+
+fi
+ if test "${ac_cv_path_install+set}" = set; then
+ INSTALL="$ac_cv_path_install"
+ else
+ # As a last resort, use the slow shell script. We don't cache a
+ # path for INSTALL within a source directory, because that will
+ # break other packages using the cache if that directory is
+ # removed, or if the path is relative.
+ INSTALL="$ac_install_sh"
+ fi
+fi
+echo "$ac_t""$INSTALL" 1>&6
+
+# Use test -z because SunOS4 sh mishandles braces in ${var-val}.
+# It thinks the first close brace ends the variable substitution.
+test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
+
+test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}'
+
+test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
+
+
+# Put a plausible default for CC_FOR_BUILD in Makefile.
+if test "x$cross_compiling" = "xno"; then
+ CC_FOR_BUILD='$(CC)'
+else
+ CC_FOR_BUILD=gcc
+fi
+
+
+
+
+AR=${AR-ar}
+
+# Extract the first word of "ranlib", so it can be a program name with args.
+set dummy ranlib; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2102: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if test -n "$RANLIB"; then
+ ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test.
+else
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":"
+ ac_dummy="$PATH"
+ for ac_dir in $ac_dummy; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ ac_cv_prog_RANLIB="ranlib"
+ break
+ fi
+ done
+ IFS="$ac_save_ifs"
+ test -z "$ac_cv_prog_RANLIB" && ac_cv_prog_RANLIB=":"
+fi
+fi
+RANLIB="$ac_cv_prog_RANLIB"
+if test -n "$RANLIB"; then
+ echo "$ac_t""$RANLIB" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+
+ALL_LINGUAS=
+
+ for ac_hdr in argz.h limits.h locale.h nl_types.h malloc.h string.h \
+unistd.h values.h sys/param.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:2137: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 2142 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2147: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=yes"
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+done
+
+ for ac_func in getcwd munmap putenv setenv setlocale strchr strcasecmp \
+__argz_count __argz_stringify __argz_next
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:2177: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 2182 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+ which can conflict with char $ac_func(); below. */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error. */
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+ to always fail with ENOSYS. Some functions are actually named
+ something starting with __ and the normal name is an alias. */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:2205: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ rm -rf conftest*
+ eval "ac_cv_func_$ac_func=yes"
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+done
+
+
+ if test "${ac_cv_func_stpcpy+set}" != "set"; then
+ for ac_func in stpcpy
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:2234: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 2239 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+ which can conflict with char $ac_func(); below. */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error. */
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+ to always fail with ENOSYS. Some functions are actually named
+ something starting with __ and the normal name is an alias. */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:2262: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ rm -rf conftest*
+ eval "ac_cv_func_$ac_func=yes"
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+done
+
+ fi
+ if test "${ac_cv_func_stpcpy}" = "yes"; then
+ cat >> confdefs.h <<\EOF
+#define HAVE_STPCPY 1
+EOF
+
+ fi
+
+ if test $ac_cv_header_locale_h = yes; then
+ echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6
+echo "configure:2296: checking for LC_MESSAGES" >&5
+if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 2301 "configure"
+#include "confdefs.h"
+#include <locale.h>
+int main() {
+return LC_MESSAGES
+; return 0; }
+EOF
+if { (eval echo configure:2308: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ rm -rf conftest*
+ am_cv_val_LC_MESSAGES=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ am_cv_val_LC_MESSAGES=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$am_cv_val_LC_MESSAGES" 1>&6
+ if test $am_cv_val_LC_MESSAGES = yes; then
+ cat >> confdefs.h <<\EOF
+#define HAVE_LC_MESSAGES 1
+EOF
+
+ fi
+ fi
+ echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6
+echo "configure:2329: checking whether NLS is requested" >&5
+ # Check whether --enable-nls or --disable-nls was given.
+if test "${enable_nls+set}" = set; then
+ enableval="$enable_nls"
+ USE_NLS=$enableval
+else
+ USE_NLS=yes
+fi
+
+ echo "$ac_t""$USE_NLS" 1>&6
+
+
+ USE_INCLUDED_LIBINTL=no
+
+ if test "$USE_NLS" = "yes"; then
+ cat >> confdefs.h <<\EOF
+#define ENABLE_NLS 1
+EOF
+
+ echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6
+echo "configure:2349: checking whether included gettext is requested" >&5
+ # Check whether --with-included-gettext or --without-included-gettext was given.
+if test "${with_included_gettext+set}" = set; then
+ withval="$with_included_gettext"
+ nls_cv_force_use_gnu_gettext=$withval
+else
+ nls_cv_force_use_gnu_gettext=no
+fi
+
+ echo "$ac_t""$nls_cv_force_use_gnu_gettext" 1>&6
+
+ nls_cv_use_gnu_gettext="$nls_cv_force_use_gnu_gettext"
+ if test "$nls_cv_force_use_gnu_gettext" != "yes"; then
+ nls_cv_header_intl=
+ nls_cv_header_libgt=
+ CATOBJEXT=NONE
+
+ ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for libintl.h""... $ac_c" 1>&6
+echo "configure:2368: checking for libintl.h" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 2373 "configure"
+#include "confdefs.h"
+#include <libintl.h>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2378: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=yes"
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6
+echo "configure:2395: checking for gettext in libc" >&5
+if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 2400 "configure"
+#include "confdefs.h"
+#include <libintl.h>
+int main() {
+return (int) gettext ("")
+; return 0; }
+EOF
+if { (eval echo configure:2407: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ rm -rf conftest*
+ gt_cv_func_gettext_libc=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ gt_cv_func_gettext_libc=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6
+
+ if test "$gt_cv_func_gettext_libc" != "yes"; then
+ echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6
+echo "configure:2423: checking for bindtextdomain in -lintl" >&5
+ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ ac_save_LIBS="$LIBS"
+LIBS="-lintl $LIBS"
+cat > conftest.$ac_ext <<EOF
+#line 2431 "configure"
+#include "confdefs.h"
+/* Override any gcc2 internal prototype to avoid an error. */
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char bindtextdomain();
+
+int main() {
+bindtextdomain()
+; return 0; }
+EOF
+if { (eval echo configure:2442: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ rm -rf conftest*
+ eval "ac_cv_lib_$ac_lib_var=yes"
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_lib_$ac_lib_var=no"
+fi
+rm -f conftest*
+LIBS="$ac_save_LIBS"
+
+fi
+if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6
+echo "configure:2458: checking for gettext in libintl" >&5
+if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 2463 "configure"
+#include "confdefs.h"
+
+int main() {
+return (int) gettext ("")
+; return 0; }
+EOF
+if { (eval echo configure:2470: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ rm -rf conftest*
+ gt_cv_func_gettext_libintl=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ gt_cv_func_gettext_libintl=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$gt_cv_func_gettext_libintl" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+ fi
+
+ if test "$gt_cv_func_gettext_libc" = "yes" \
+ || test "$gt_cv_func_gettext_libintl" = "yes"; then
+ cat >> confdefs.h <<\EOF
+#define HAVE_GETTEXT 1
+EOF
+
+ # Extract the first word of "msgfmt", so it can be a program name with args.
+set dummy msgfmt; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2498: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ case "$MSGFMT" in
+ /*)
+ ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
+ ;;
+ *)
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+ for ac_dir in $PATH; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
+ ac_cv_path_MSGFMT="$ac_dir/$ac_word"
+ break
+ fi
+ fi
+ done
+ IFS="$ac_save_ifs"
+ test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="no"
+ ;;
+esac
+fi
+MSGFMT="$ac_cv_path_MSGFMT"
+if test -n "$MSGFMT"; then
+ echo "$ac_t""$MSGFMT" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+ if test "$MSGFMT" != "no"; then
+ for ac_func in dcgettext
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:2532: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 2537 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+ which can conflict with char $ac_func(); below. */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error. */
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+ to always fail with ENOSYS. Some functions are actually named
+ something starting with __ and the normal name is an alias. */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:2560: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ rm -rf conftest*
+ eval "ac_cv_func_$ac_func=yes"
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+done
+
+ # Extract the first word of "gmsgfmt", so it can be a program name with args.
+set dummy gmsgfmt; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2587: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ case "$GMSGFMT" in
+ /*)
+ ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
+ ;;
+ ?:/*)
+ ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path.
+ ;;
+ *)
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":"
+ ac_dummy="$PATH"
+ for ac_dir in $ac_dummy; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ ac_cv_path_GMSGFMT="$ac_dir/$ac_word"
+ break
+ fi
+ done
+ IFS="$ac_save_ifs"
+ test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
+ ;;
+esac
+fi
+GMSGFMT="$ac_cv_path_GMSGFMT"
+if test -n "$GMSGFMT"; then
+ echo "$ac_t""$GMSGFMT" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+ # Extract the first word of "xgettext", so it can be a program name with args.
+set dummy xgettext; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2623: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ case "$XGETTEXT" in
+ /*)
+ ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
+ ;;
+ *)
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+ for ac_dir in $PATH; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
+ ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
+ break
+ fi
+ fi
+ done
+ IFS="$ac_save_ifs"
+ test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
+ ;;
+esac
+fi
+XGETTEXT="$ac_cv_path_XGETTEXT"
+if test -n "$XGETTEXT"; then
+ echo "$ac_t""$XGETTEXT" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+ cat > conftest.$ac_ext <<EOF
+#line 2655 "configure"
+#include "confdefs.h"
+
+int main() {
+extern int _nl_msg_cat_cntr;
+ return _nl_msg_cat_cntr
+; return 0; }
+EOF
+if { (eval echo configure:2663: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ rm -rf conftest*
+ CATOBJEXT=.gmo
+ DATADIRNAME=share
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ CATOBJEXT=.mo
+ DATADIRNAME=lib
+fi
+rm -f conftest*
+ INSTOBJEXT=.mo
+ fi
+ fi
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+
+
+ if test "$CATOBJEXT" = "NONE"; then
+ nls_cv_use_gnu_gettext=yes
+ fi
+ fi
+
+ if test "$nls_cv_use_gnu_gettext" = "yes"; then
+ INTLOBJS="\$(GETTOBJS)"
+ # Extract the first word of "msgfmt", so it can be a program name with args.
+set dummy msgfmt; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2695: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ case "$MSGFMT" in
+ /*)
+ ac_cv_path_MSGFMT="$MSGFMT" # Let the user override the test with a path.
+ ;;
+ *)
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+ for ac_dir in $PATH; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ if test -z "`$ac_dir/$ac_word -h 2>&1 | grep 'dv '`"; then
+ ac_cv_path_MSGFMT="$ac_dir/$ac_word"
+ break
+ fi
+ fi
+ done
+ IFS="$ac_save_ifs"
+ test -z "$ac_cv_path_MSGFMT" && ac_cv_path_MSGFMT="msgfmt"
+ ;;
+esac
+fi
+MSGFMT="$ac_cv_path_MSGFMT"
+if test -n "$MSGFMT"; then
+ echo "$ac_t""$MSGFMT" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+ # Extract the first word of "gmsgfmt", so it can be a program name with args.
+set dummy gmsgfmt; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2729: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ case "$GMSGFMT" in
+ /*)
+ ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a path.
+ ;;
+ ?:/*)
+ ac_cv_path_GMSGFMT="$GMSGFMT" # Let the user override the test with a dos path.
+ ;;
+ *)
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":"
+ ac_dummy="$PATH"
+ for ac_dir in $ac_dummy; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ ac_cv_path_GMSGFMT="$ac_dir/$ac_word"
+ break
+ fi
+ done
+ IFS="$ac_save_ifs"
+ test -z "$ac_cv_path_GMSGFMT" && ac_cv_path_GMSGFMT="$MSGFMT"
+ ;;
+esac
+fi
+GMSGFMT="$ac_cv_path_GMSGFMT"
+if test -n "$GMSGFMT"; then
+ echo "$ac_t""$GMSGFMT" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+ # Extract the first word of "xgettext", so it can be a program name with args.
+set dummy xgettext; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:2765: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ case "$XGETTEXT" in
+ /*)
+ ac_cv_path_XGETTEXT="$XGETTEXT" # Let the user override the test with a path.
+ ;;
+ *)
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+ for ac_dir in $PATH; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ if test -z "`$ac_dir/$ac_word -h 2>&1 | grep '(HELP)'`"; then
+ ac_cv_path_XGETTEXT="$ac_dir/$ac_word"
+ break
+ fi
+ fi
+ done
+ IFS="$ac_save_ifs"
+ test -z "$ac_cv_path_XGETTEXT" && ac_cv_path_XGETTEXT=":"
+ ;;
+esac
+fi
+XGETTEXT="$ac_cv_path_XGETTEXT"
+if test -n "$XGETTEXT"; then
+ echo "$ac_t""$XGETTEXT" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+
+ USE_INCLUDED_LIBINTL=yes
+ CATOBJEXT=.gmo
+ INSTOBJEXT=.mo
+ DATADIRNAME=share
+ INTLDEPS='$(top_builddir)/../intl/libintl.a'
+ INTLLIBS=$INTLDEPS
+ LIBS=`echo $LIBS | sed -e 's/-lintl//'`
+ nls_cv_header_intl=libintl.h
+ nls_cv_header_libgt=libgettext.h
+ fi
+
+ if test "$XGETTEXT" != ":"; then
+ if $XGETTEXT --omit-header /dev/null 2> /dev/null; then
+ : ;
+ else
+ echo "$ac_t""found xgettext programs is not GNU xgettext; ignore it" 1>&6
+ XGETTEXT=":"
+ fi
+ fi
+
+ # We need to process the po/ directory.
+ POSUB=po
+ else
+ DATADIRNAME=share
+ nls_cv_header_intl=libintl.h
+ nls_cv_header_libgt=libgettext.h
+ fi
+
+ # If this is used in GNU gettext we have to set USE_NLS to `yes'
+ # because some of the sources are only built for this goal.
+ if test "$PACKAGE" = gettext; then
+ USE_NLS=yes
+ USE_INCLUDED_LIBINTL=yes
+ fi
+
+ for lang in $ALL_LINGUAS; do
+ GMOFILES="$GMOFILES $lang.gmo"
+ POFILES="$POFILES $lang.po"
+ done
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ if test "x$CATOBJEXT" != "x"; then
+ if test "x$ALL_LINGUAS" = "x"; then
+ LINGUAS=
+ else
+ echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6
+echo "configure:2855: checking for catalogs to be installed" >&5
+ NEW_LINGUAS=
+ for lang in ${LINGUAS=$ALL_LINGUAS}; do
+ case "$ALL_LINGUAS" in
+ *$lang*) NEW_LINGUAS="$NEW_LINGUAS $lang" ;;
+ esac
+ done
+ LINGUAS=$NEW_LINGUAS
+ echo "$ac_t""$LINGUAS" 1>&6
+ fi
+
+ if test -n "$LINGUAS"; then
+ for lang in $LINGUAS; do CATALOGS="$CATALOGS $lang$CATOBJEXT"; done
+ fi
+ fi
+
+ if test $ac_cv_header_locale_h = yes; then
+ INCLUDE_LOCALE_H="#include <locale.h>"
+ else
+ INCLUDE_LOCALE_H="\
+/* The system does not provide the header <locale.h>. Take care yourself. */"
+ fi
+
+
+ if test -f $srcdir/po2tbl.sed.in; then
+ if test "$CATOBJEXT" = ".cat"; then
+ ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6
+echo "configure:2883: checking for linux/version.h" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 2888 "configure"
+#include "confdefs.h"
+#include <linux/version.h>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2893: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=yes"
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ msgformat=linux
+else
+ echo "$ac_t""no" 1>&6
+msgformat=xopen
+fi
+
+
+ sed -e '/^#/d' $srcdir/$msgformat-msg.sed > po2msg.sed
+ fi
+ sed -e '/^#.*[^\\]$/d' -e '/^#$/d' \
+ $srcdir/po2tbl.sed.in > po2tbl.sed
+ fi
+
+ if test "$PACKAGE" = "gettext"; then
+ GT_NO="#NO#"
+ GT_YES=
+ else
+ GT_NO=
+ GT_YES="#YES#"
+ fi
+
+
+
+ MKINSTALLDIRS="\$(srcdir)/../../mkinstalldirs"
+
+
+ l=
+
+
+ if test -d $srcdir/po; then
+ test -d po || mkdir po
+ if test "x$srcdir" != "x."; then
+ if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then
+ posrcprefix="$srcdir/"
+ else
+ posrcprefix="../$srcdir/"
+ fi
+ else
+ posrcprefix="../"
+ fi
+ rm -f po/POTFILES
+ sed -e "/^#/d" -e "/^\$/d" -e "s,.*, $posrcprefix& \\\\," -e "\$s/\(.*\) \\\\/\1/" \
+ < $srcdir/po/POTFILES.in > po/POTFILES
+ fi
+
+
+# Check for common headers.
+# FIXME: Seems to me this can cause problems for i386-windows hosts.
+# At one point there were hardcoded AC_DEFINE's if ${host} = i386-*-windows*.
+for ac_hdr in stdlib.h string.h strings.h unistd.h time.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:2962: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 2967 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:2972: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=yes"
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_hdr in sys/time.h sys/resource.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:3002: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 3007 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:3012: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=yes"
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_hdr in fcntl.h fpu_control.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:3042: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 3047 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:3052: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=yes"
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_hdr in dlfcn.h errno.h sys/stat.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:3082: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 3087 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:3092: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=yes"
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+done
+
+for ac_func in getrusage time sigaction __setfpucw
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:3121: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 3126 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+ which can conflict with char $ac_func(); below. */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error. */
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+ to always fail with ENOSYS. Some functions are actually named
+ something starting with __ and the normal name is an alias. */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:3149: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ rm -rf conftest*
+ eval "ac_cv_func_$ac_func=yes"
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+done
+
+
+# Check for socket libraries
+echo $ac_n "checking for bind in -lsocket""... $ac_c" 1>&6
+echo "configure:3176: checking for bind in -lsocket" >&5
+ac_lib_var=`echo socket'_'bind | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ ac_save_LIBS="$LIBS"
+LIBS="-lsocket $LIBS"
+cat > conftest.$ac_ext <<EOF
+#line 3184 "configure"
+#include "confdefs.h"
+/* Override any gcc2 internal prototype to avoid an error. */
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char bind();
+
+int main() {
+bind()
+; return 0; }
+EOF
+if { (eval echo configure:3195: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ rm -rf conftest*
+ eval "ac_cv_lib_$ac_lib_var=yes"
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_lib_$ac_lib_var=no"
+fi
+rm -f conftest*
+LIBS="$ac_save_LIBS"
+
+fi
+if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_lib=HAVE_LIB`echo socket | sed -e 's/[^a-zA-Z0-9_]/_/g' \
+ -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_lib 1
+EOF
+
+ LIBS="-lsocket $LIBS"
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+echo $ac_n "checking for gethostbyname in -lnsl""... $ac_c" 1>&6
+echo "configure:3223: checking for gethostbyname in -lnsl" >&5
+ac_lib_var=`echo nsl'_'gethostbyname | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ ac_save_LIBS="$LIBS"
+LIBS="-lnsl $LIBS"
+cat > conftest.$ac_ext <<EOF
+#line 3231 "configure"
+#include "confdefs.h"
+/* Override any gcc2 internal prototype to avoid an error. */
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char gethostbyname();
+
+int main() {
+gethostbyname()
+; return 0; }
+EOF
+if { (eval echo configure:3242: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ rm -rf conftest*
+ eval "ac_cv_lib_$ac_lib_var=yes"
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_lib_$ac_lib_var=no"
+fi
+rm -f conftest*
+LIBS="$ac_save_LIBS"
+
+fi
+if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_lib=HAVE_LIB`echo nsl | sed -e 's/[^a-zA-Z0-9_]/_/g' \
+ -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_lib 1
+EOF
+
+ LIBS="-lnsl $LIBS"
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+
+. ${srcdir}/../../bfd/configure.host
+
+
+
+USE_MAINTAINER_MODE=no
+# Check whether --enable-maintainer-mode or --disable-maintainer-mode was given.
+if test "${enable_maintainer_mode+set}" = set; then
+ enableval="$enable_maintainer_mode"
+ case "${enableval}" in
+ yes) MAINT="" USE_MAINTAINER_MODE=yes ;;
+ no) MAINT="#" ;;
+ *) { echo "configure: error: "--enable-maintainer-mode does not take a value"" 1>&2; exit 1; }; MAINT="#" ;;
+esac
+if test x"$silent" != x"yes" && test x"$MAINT" = x""; then
+ echo "Setting maintainer mode" 6>&1
+fi
+else
+ MAINT="#"
+fi
+
+
+
+# Check whether --enable-sim-bswap or --disable-sim-bswap was given.
+if test "${enable_sim_bswap+set}" = set; then
+ enableval="$enable_sim_bswap"
+ case "${enableval}" in
+ yes) sim_bswap="-DWITH_BSWAP=1 -DUSE_BSWAP=1";;
+ no) sim_bswap="-DWITH_BSWAP=0";;
+ *) { echo "configure: error: "--enable-sim-bswap does not take a value"" 1>&2; exit 1; }; sim_bswap="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_bswap" != x""; then
+ echo "Setting bswap flags = $sim_bswap" 6>&1
+fi
+else
+ sim_bswap=""
+fi
+
+
+
+# Check whether --enable-sim-cflags or --disable-sim-cflags was given.
+if test "${enable_sim_cflags+set}" = set; then
+ enableval="$enable_sim_cflags"
+ case "${enableval}" in
+ yes) sim_cflags="-O2 -fomit-frame-pointer";;
+ trace) { echo "configure: error: "Please use --enable-sim-debug instead."" 1>&2; exit 1; }; sim_cflags="";;
+ no) sim_cflags="";;
+ *) sim_cflags=`echo "${enableval}" | sed -e "s/,/ /g"`;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_cflags" != x""; then
+ echo "Setting sim cflags = $sim_cflags" 6>&1
+fi
+else
+ sim_cflags=""
+fi
+
+
+
+# Check whether --enable-sim-debug or --disable-sim-debug was given.
+if test "${enable_sim_debug+set}" = set; then
+ enableval="$enable_sim_debug"
+ case "${enableval}" in
+ yes) sim_debug="-DDEBUG=7 -DWITH_DEBUG=7";;
+ no) sim_debug="-DDEBUG=0 -DWITH_DEBUG=0";;
+ *) sim_debug="-DDEBUG='(${enableval})' -DWITH_DEBUG='(${enableval})'";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_debug" != x""; then
+ echo "Setting sim debug = $sim_debug" 6>&1
+fi
+else
+ sim_debug=""
+fi
+
+
+
+# Check whether --enable-sim-stdio or --disable-sim-stdio was given.
+if test "${enable_sim_stdio+set}" = set; then
+ enableval="$enable_sim_stdio"
+ case "${enableval}" in
+ yes) sim_stdio="-DWITH_STDIO=DO_USE_STDIO";;
+ no) sim_stdio="-DWITH_STDIO=DONT_USE_STDIO";;
+ *) { echo "configure: error: "Unknown value $enableval passed to --enable-sim-stdio"" 1>&2; exit 1; }; sim_stdio="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_stdio" != x""; then
+ echo "Setting stdio flags = $sim_stdio" 6>&1
+fi
+else
+ sim_stdio=""
+fi
+
+
+
+# Check whether --enable-sim-trace or --disable-sim-trace was given.
+if test "${enable_sim_trace+set}" = set; then
+ enableval="$enable_sim_trace"
+ case "${enableval}" in
+ yes) sim_trace="-DTRACE=1 -DWITH_TRACE=-1";;
+ no) sim_trace="-DTRACE=0 -DWITH_TRACE=0";;
+ [-0-9]*)
+ sim_trace="-DTRACE='(${enableval})' -DWITH_TRACE='(${enableval})'";;
+ [a-z]*)
+ sim_trace=""
+ for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+ if test x"$sim_trace" = x; then
+ sim_trace="-DWITH_TRACE='(TRACE_$x"
+ else
+ sim_trace="${sim_trace}|TRACE_$x"
+ fi
+ done
+ sim_trace="$sim_trace)'" ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_trace" != x""; then
+ echo "Setting sim trace = $sim_trace" 6>&1
+fi
+else
+ sim_trace=""
+fi
+
+
+
+# Check whether --enable-sim-profile or --disable-sim-profile was given.
+if test "${enable_sim_profile+set}" = set; then
+ enableval="$enable_sim_profile"
+ case "${enableval}" in
+ yes) sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1";;
+ no) sim_profile="-DPROFILE=0 -DWITH_PROFILE=0";;
+ [-0-9]*)
+ sim_profile="-DPROFILE='(${enableval})' -DWITH_PROFILE='(${enableval})'";;
+ [a-z]*)
+ sim_profile=""
+ for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+ if test x"$sim_profile" = x; then
+ sim_profile="-DWITH_PROFILE='(PROFILE_$x"
+ else
+ sim_profile="${sim_profile}|PROFILE_$x"
+ fi
+ done
+ sim_profile="$sim_profile)'" ;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_profile" != x""; then
+ echo "Setting sim profile = $sim_profile" 6>&1
+fi
+else
+ sim_profile="-DPROFILE=1 -DWITH_PROFILE=-1"
+fi
+
+
+
+echo $ac_n "checking return type of signal handlers""... $ac_c" 1>&6
+echo "configure:3418: checking return type of signal handlers" >&5
+if eval "test \"`echo '$''{'ac_cv_type_signal'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 3423 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#include <signal.h>
+#ifdef signal
+#undef signal
+#endif
+#ifdef __cplusplus
+extern "C" void (*signal (int, void (*)(int)))(int);
+#else
+void (*signal ()) ();
+#endif
+
+int main() {
+int i;
+; return 0; }
+EOF
+if { (eval echo configure:3440: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+ rm -rf conftest*
+ ac_cv_type_signal=void
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ ac_cv_type_signal=int
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_type_signal" 1>&6
+cat >> confdefs.h <<EOF
+#define RETSIGTYPE $ac_cv_type_signal
+EOF
+
+
+
+
+
+echo $ac_n "checking for executable suffix""... $ac_c" 1>&6
+echo "configure:3462: checking for executable suffix" >&5
+if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if test "$CYGWIN" = yes || test "$MINGW32" = yes; then
+ ac_cv_exeext=.exe
+else
+ rm -f conftest*
+ echo 'int main () { return 0; }' > conftest.$ac_ext
+ ac_cv_exeext=
+ if { (eval echo configure:3472: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then
+ for file in conftest.*; do
+ case $file in
+ *.c | *.o | *.obj | *.ilk | *.pdb) ;;
+ *) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;;
+ esac
+ done
+ else
+ { echo "configure: error: installation or configuration problem: compiler cannot create executables." 1>&2; exit 1; }
+ fi
+ rm -f conftest*
+ test x"${ac_cv_exeext}" = x && ac_cv_exeext=no
+fi
+fi
+
+EXEEXT=""
+test x"${ac_cv_exeext}" != xno && EXEEXT=${ac_cv_exeext}
+echo "$ac_t""${ac_cv_exeext}" 1>&6
+ac_exeext=$EXEEXT
+
+
+sim_link_files=
+sim_link_links=
+
+sim_link_links=tconfig.h
+if test -f ${srcdir}/tconfig.in
+then
+ sim_link_files=tconfig.in
+else
+ sim_link_files=../common/tconfig.in
+fi
+
+# targ-vals.def points to the libc macro description file.
+case "${target}" in
+*-*-*) TARG_VALS_DEF=../common/nltvals.def ;;
+esac
+sim_link_files="${sim_link_files} ${TARG_VALS_DEF}"
+sim_link_links="${sim_link_links} targ-vals.def"
+
+
+
+
+wire_endian=""
+default_endian="BIG_ENDIAN"
+# Check whether --enable-sim-endian or --disable-sim-endian was given.
+if test "${enable_sim_endian+set}" = set; then
+ enableval="$enable_sim_endian"
+ case "${enableval}" in
+ b*|B*) sim_endian="-DWITH_TARGET_BYTE_ORDER=BIG_ENDIAN";;
+ l*|L*) sim_endian="-DWITH_TARGET_BYTE_ORDER=LITTLE_ENDIAN";;
+ yes) if test x"$wire_endian" != x; then
+ sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
+ else
+ if test x"$default_endian" != x; then
+ sim_endian="-DWITH_TARGET_BYTE_ORDER=${default_endian}"
+ else
+ echo "No hard-wired endian for target $target" 1>&6
+ sim_endian="-DWITH_TARGET_BYTE_ORDER=0"
+ fi
+ fi;;
+ no) if test x"$default_endian" != x; then
+ sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
+ else
+ if test x"$wire_endian" != x; then
+ sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${wire_endian}"
+ else
+ echo "No default endian for target $target" 1>&6
+ sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=0"
+ fi
+ fi;;
+ *) { echo "configure: error: "Unknown value $enableval for --enable-sim-endian"" 1>&2; exit 1; }; sim_endian="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_endian" != x""; then
+ echo "Setting endian flags = $sim_endian" 6>&1
+fi
+else
+ if test x"$default_endian" != x; then
+ sim_endian="-DWITH_DEFAULT_TARGET_BYTE_ORDER=${default_endian}"
+else
+ if test x"$wire_endian" != x; then
+ sim_endian="-DWITH_TARGET_BYTE_ORDER=${wire_endian}"
+ else
+ sim_endian=
+ fi
+fi
+fi
+
+wire_alignment="STRICT_ALIGNMENT"
+default_alignment=""
+
+# Check whether --enable-sim-alignment or --disable-sim-alignment was given.
+if test "${enable_sim_alignment+set}" = set; then
+ enableval="$enable_sim_alignment"
+ case "${enableval}" in
+ strict | STRICT) sim_alignment="-DWITH_ALIGNMENT=STRICT_ALIGNMENT";;
+ nonstrict | NONSTRICT) sim_alignment="-DWITH_ALIGNMENT=NONSTRICT_ALIGNMENT";;
+ forced | FORCED) sim_alignment="-DWITH_ALIGNMENT=FORCED_ALIGNMENT";;
+ yes) if test x"$wire_alignment" != x; then
+ sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
+ else
+ if test x"$default_alignment" != x; then
+ sim_alignment="-DWITH_ALIGNMENT=${default_alignment}"
+ else
+ echo "No hard-wired alignment for target $target" 1>&6
+ sim_alignment="-DWITH_ALIGNMENT=0"
+ fi
+ fi;;
+ no) if test x"$default_alignment" != x; then
+ sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
+ else
+ if test x"$wire_alignment" != x; then
+ sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${wire_alignment}"
+ else
+ echo "No default alignment for target $target" 1>&6
+ sim_alignment="-DWITH_DEFAULT_ALIGNMENT=0"
+ fi
+ fi;;
+ *) { echo "configure: error: "Unknown value $enableval passed to --enable-sim-alignment"" 1>&2; exit 1; }; sim_alignment="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_alignment" != x""; then
+ echo "Setting alignment flags = $sim_alignment" 6>&1
+fi
+else
+ if test x"$default_alignment" != x; then
+ sim_alignment="-DWITH_DEFAULT_ALIGNMENT=${default_alignment}"
+else
+ if test x"$wire_alignment" != x; then
+ sim_alignment="-DWITH_ALIGNMENT=${wire_alignment}"
+ else
+ sim_alignment=
+ fi
+fi
+fi
+
+
+# Check whether --enable-sim-hostendian or --disable-sim-hostendian was given.
+if test "${enable_sim_hostendian+set}" = set; then
+ enableval="$enable_sim_hostendian"
+ case "${enableval}" in
+ no) sim_hostendian="-DWITH_HOST_BYTE_ORDER=0";;
+ b*|B*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN";;
+ l*|L*) sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN";;
+ *) { echo "configure: error: "Unknown value $enableval for --enable-sim-hostendian"" 1>&2; exit 1; }; sim_hostendian="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_hostendian" != x""; then
+ echo "Setting hostendian flags = $sim_hostendian" 6>&1
+fi
+else
+
+if test "x$cross_compiling" = "xno"; then
+ echo $ac_n "checking whether byte ordering is bigendian""... $ac_c" 1>&6
+echo "configure:3623: checking whether byte ordering is bigendian" >&5
+if eval "test \"`echo '$''{'ac_cv_c_bigendian'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ ac_cv_c_bigendian=unknown
+# See if sys/param.h defines the BYTE_ORDER macro.
+cat > conftest.$ac_ext <<EOF
+#line 3630 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#include <sys/param.h>
+int main() {
+
+#if !BYTE_ORDER || !BIG_ENDIAN || !LITTLE_ENDIAN
+ bogus endian macros
+#endif
+; return 0; }
+EOF
+if { (eval echo configure:3641: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+ rm -rf conftest*
+ # It does; now see whether it defined to BIG_ENDIAN or not.
+cat > conftest.$ac_ext <<EOF
+#line 3645 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#include <sys/param.h>
+int main() {
+
+#if BYTE_ORDER != BIG_ENDIAN
+ not big endian
+#endif
+; return 0; }
+EOF
+if { (eval echo configure:3656: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+ rm -rf conftest*
+ ac_cv_c_bigendian=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ ac_cv_c_bigendian=no
+fi
+rm -f conftest*
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+fi
+rm -f conftest*
+if test $ac_cv_c_bigendian = unknown; then
+if test "$cross_compiling" = yes; then
+ { echo "configure: error: can not run test program while cross compiling" 1>&2; exit 1; }
+else
+ cat > conftest.$ac_ext <<EOF
+#line 3676 "configure"
+#include "confdefs.h"
+main () {
+ /* Are we little or big endian? From Harbison&Steele. */
+ union
+ {
+ long l;
+ char c[sizeof (long)];
+ } u;
+ u.l = 1;
+ exit (u.c[sizeof (long) - 1] == 1);
+}
+EOF
+if { (eval echo configure:3689: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+ ac_cv_c_bigendian=no
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -fr conftest*
+ ac_cv_c_bigendian=yes
+fi
+rm -fr conftest*
+fi
+
+fi
+fi
+
+echo "$ac_t""$ac_cv_c_bigendian" 1>&6
+if test $ac_cv_c_bigendian = yes; then
+ cat >> confdefs.h <<\EOF
+#define WORDS_BIGENDIAN 1
+EOF
+
+fi
+
+ if test $ac_cv_c_bigendian = yes; then
+ sim_hostendian="-DWITH_HOST_BYTE_ORDER=BIG_ENDIAN"
+ else
+ sim_hostendian="-DWITH_HOST_BYTE_ORDER=LITTLE_ENDIAN"
+ fi
+else
+ sim_hostendian="-DWITH_HOST_BYTE_ORDER=0"
+fi
+fi
+
+
+default_sim_scache="16384"
+# Check whether --enable-sim-scache or --disable-sim-scache was given.
+if test "${enable_sim_scache+set}" = set; then
+ enableval="$enable_sim_scache"
+ case "${enableval}" in
+ yes) sim_scache="-DWITH_SCACHE=${default_sim_scache}";;
+ no) sim_scache="-DWITH_SCACHE=0" ;;
+ [0-9]*) sim_cache=${enableval};;
+ *) { echo "configure: error: "Bad value $enableval passed to --enable-sim-scache"" 1>&2; exit 1; };
+ sim_scache="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_scache" != x""; then
+ echo "Setting scache size = $sim_scache" 6>&1
+fi
+else
+ sim_scache="-DWITH_SCACHE=${default_sim_scache}"
+fi
+
+
+
+default_sim_default_model="sh5"
+# Check whether --enable-sim-default-model or --disable-sim-default-model was given.
+if test "${enable_sim_default_model+set}" = set; then
+ enableval="$enable_sim_default_model"
+ case "${enableval}" in
+ yes|no) { echo "configure: error: "Missing argument to --enable-sim-default-model"" 1>&2; exit 1; };;
+ *) sim_default_model="-DWITH_DEFAULT_MODEL='\"${enableval}\"'";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_default_model" != x""; then
+ echo "Setting default model = $sim_default_model" 6>&1
+fi
+else
+ sim_default_model="-DWITH_DEFAULT_MODEL='\"${default_sim_default_model}\"'"
+fi
+
+
+
+# Check whether --enable-sim-environment or --disable-sim-environment was given.
+if test "${enable_sim_environment+set}" = set; then
+ enableval="$enable_sim_environment"
+ case "${enableval}" in
+ all | ALL) sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT";;
+ user | USER) sim_environment="-DWITH_ENVIRONMENT=USER_ENVIRONMENT";;
+ virtual | VIRTUAL) sim_environment="-DWITH_ENVIRONMENT=VIRTUAL_ENVIRONMENT";;
+ operating | OPERATING) sim_environment="-DWITH_ENVIRONMENT=OPERATING_ENVIRONMENT";;
+ *) { echo "configure: error: "Unknown value $enableval passed to --enable-sim-environment"" 1>&2; exit 1; };
+ sim_environment="";;
+esac
+if test x"$silent" != x"yes" && test x"$sim_environment" != x""; then
+ echo "Setting sim environment = $sim_environment" 6>&1
+fi
+else
+ sim_environment="-DWITH_ENVIRONMENT=ALL_ENVIRONMENT"
+fi
+
+
+default_sim_inline=""
+# Check whether --enable-sim-inline or --disable-sim-inline was given.
+if test "${enable_sim_inline+set}" = set; then
+ enableval="$enable_sim_inline"
+ sim_inline=""
+case "$enableval" in
+ no) sim_inline="-DDEFAULT_INLINE=0";;
+ 0) sim_inline="-DDEFAULT_INLINE=0";;
+ yes | 2) sim_inline="-DDEFAULT_INLINE=ALL_C_INLINE";;
+ 1) sim_inline="-DDEFAULT_INLINE=INLINE_LOCALS";;
+ *) for x in `echo "$enableval" | sed -e "s/,/ /g"`; do
+ new_flag=""
+ case "$x" in
+ *_INLINE=*) new_flag="-D$x";;
+ *=*) new_flag=`echo "$x" | sed -e "s/=/_INLINE=/" -e "s/^/-D/"`;;
+ *_INLINE) new_flag="-D$x=ALL_C_INLINE";;
+ *) new_flag="-D$x""_INLINE=ALL_C_INLINE";;
+ esac
+ if test x"$sim_inline" = x""; then
+ sim_inline="$new_flag"
+ else
+ sim_inline="$sim_inline $new_flag"
+ fi
+ done;;
+esac
+if test x"$silent" != x"yes" && test x"$sim_inline" != x""; then
+ echo "Setting inline flags = $sim_inline" 6>&1
+fi
+else
+
+if test "x$cross_compiling" = "xno"; then
+ if test x"$GCC" != "x" -a x"${default_sim_inline}" != "x" ; then
+ sim_inline="${default_sim_inline}"
+ if test x"$silent" != x"yes"; then
+ echo "Setting inline flags = $sim_inline" 6>&1
+ fi
+ else
+ sim_inline=""
+ fi
+else
+ sim_inline="-DDEFAULT_INLINE=0"
+fi
+fi
+
+
+cgen_maint=no
+cgendir='$(srcdir)/../../cgen'
+
+# Check whether --enable-cgen-maint or --disable-cgen-maint was given.
+if test "${enable_cgen_maint+set}" = set; then
+ enableval="$enable_cgen_maint"
+ case "${enableval}" in
+ yes) cgen_maint=yes ;;
+ no) cgen_maint=no ;;
+ *)
+ # argument is cgen install directory (not implemented yet).
+ # Having a `share' directory might be more appropriate for the .scm,
+ # .cpu, etc. files.
+ cgendir=${cgen_maint}/lib/cgen
+ ;;
+esac
+fi
+if test x${cgen_maint} != xno ; then
+ CGEN_MAINT=''
+else
+ CGEN_MAINT='#'
+fi
+
+
+
+
+
+
+
+trap '' 1 2 15
+cat > confcache <<\EOF
+# This file is a shell script that caches the results of configure
+# tests run on this system so they can be shared between configure
+# scripts and configure runs. It is not useful on other systems.
+# If it contains results you don't want to keep, you may remove or edit it.
+#
+# By default, configure uses ./config.cache as the cache file,
+# creating it if it does not exist already. You can give configure
+# the --cache-file=FILE option to use a different cache file; that is
+# what configure does when it calls configure scripts in
+# subdirectories, so they share the cache.
+# Giving --cache-file=/dev/null disables caching, for debugging configure.
+# config.status only pays attention to the cache file if you give it the
+# --recheck option to rerun configure.
+#
+EOF
+# The following way of writing the cache mishandles newlines in values,
+# but we know of no workaround that is simple, portable, and efficient.
+# So, don't put newlines in cache variables' values.
+# Ultrix sh set writes to stderr and can't be redirected directly,
+# and sets the high bit in the cache file unless we assign to the vars.
+(set) 2>&1 |
+ case `(ac_space=' '; set | grep ac_space) 2>&1` in
+ *ac_space=\ *)
+ # `set' does not quote correctly, so add quotes (double-quote substitution
+ # turns \\\\ into \\, and sed turns \\ into \).
+ sed -n \
+ -e "s/'/'\\\\''/g" \
+ -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p"
+ ;;
+ *)
+ # `set' quotes correctly as required by POSIX, so do not add quotes.
+ sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p'
+ ;;
+ esac >> confcache
+if cmp -s $cache_file confcache; then
+ :
+else
+ if test -w $cache_file; then
+ echo "updating cache $cache_file"
+ cat confcache > $cache_file
+ else
+ echo "not updating unwritable cache $cache_file"
+ fi
+fi
+rm -f confcache
+
+trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
+
+test "x$prefix" = xNONE && prefix=$ac_default_prefix
+# Let make expand exec_prefix.
+test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
+
+# Any assignment to VPATH causes Sun make to only execute
+# the first set of double-colon rules, so remove it if not needed.
+# If there is a colon in the path, we need to keep it.
+if test "x$srcdir" = x.; then
+ ac_vpsub='/^[ ]*VPATH[ ]*=[^:]*$/d'
+fi
+
+trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15
+
+DEFS=-DHAVE_CONFIG_H
+
+# Without the "./", some shells look in PATH for config.status.
+: ${CONFIG_STATUS=./config.status}
+
+echo creating $CONFIG_STATUS
+rm -f $CONFIG_STATUS
+cat > $CONFIG_STATUS <<EOF
+#! /bin/sh
+# Generated automatically by configure.
+# Run this file to recreate the current configuration.
+# This directory was configured as follows,
+# on host `(hostname || uname -n) 2>/dev/null | sed 1q`:
+#
+# $0 $ac_configure_args
+#
+# Compiler output produced by configure, useful for debugging
+# configure, is in ./config.log if it exists.
+
+ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]"
+for ac_option
+do
+ case "\$ac_option" in
+ -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
+ echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion"
+ exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;;
+ -version | --version | --versio | --versi | --vers | --ver | --ve | --v)
+ echo "$CONFIG_STATUS generated by autoconf version 2.13"
+ exit 0 ;;
+ -help | --help | --hel | --he | --h)
+ echo "\$ac_cs_usage"; exit 0 ;;
+ *) echo "\$ac_cs_usage"; exit 1 ;;
+ esac
+done
+
+ac_given_srcdir=$srcdir
+ac_given_INSTALL="$INSTALL"
+
+trap 'rm -fr `echo "Makefile.sim:Makefile.in Make-common.sim:../common/Make-common.in .gdbinit:../common/gdbinit.in config.h:config.in" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15
+EOF
+cat >> $CONFIG_STATUS <<EOF
+
+# Protect against being on the right side of a sed subst in config.status.
+sed 's/%@/@@/; s/@%/@@/; s/%g\$/@g/; /@g\$/s/[\\\\&%]/\\\\&/g;
+ s/@@/%@/; s/@@/@%/; s/@g\$/%g/' > conftest.subs <<\\CEOF
+$ac_vpsub
+$extrasub
+s%@sim_environment@%$sim_environment%g
+s%@sim_alignment@%$sim_alignment%g
+s%@sim_assert@%$sim_assert%g
+s%@sim_bitsize@%$sim_bitsize%g
+s%@sim_endian@%$sim_endian%g
+s%@sim_hostendian@%$sim_hostendian%g
+s%@sim_float@%$sim_float%g
+s%@sim_scache@%$sim_scache%g
+s%@sim_default_model@%$sim_default_model%g
+s%@sim_hw_cflags@%$sim_hw_cflags%g
+s%@sim_hw_objs@%$sim_hw_objs%g
+s%@sim_hw@%$sim_hw%g
+s%@sim_inline@%$sim_inline%g
+s%@sim_packages@%$sim_packages%g
+s%@sim_regparm@%$sim_regparm%g
+s%@sim_reserved_bits@%$sim_reserved_bits%g
+s%@sim_smp@%$sim_smp%g
+s%@sim_stdcall@%$sim_stdcall%g
+s%@sim_xor_endian@%$sim_xor_endian%g
+s%@WARN_CFLAGS@%$WARN_CFLAGS%g
+s%@WERROR_CFLAGS@%$WERROR_CFLAGS%g
+s%@SHELL@%$SHELL%g
+s%@CFLAGS@%$CFLAGS%g
+s%@CPPFLAGS@%$CPPFLAGS%g
+s%@CXXFLAGS@%$CXXFLAGS%g
+s%@FFLAGS@%$FFLAGS%g
+s%@DEFS@%$DEFS%g
+s%@LDFLAGS@%$LDFLAGS%g
+s%@LIBS@%$LIBS%g
+s%@exec_prefix@%$exec_prefix%g
+s%@prefix@%$prefix%g
+s%@program_transform_name@%$program_transform_name%g
+s%@bindir@%$bindir%g
+s%@sbindir@%$sbindir%g
+s%@libexecdir@%$libexecdir%g
+s%@datadir@%$datadir%g
+s%@sysconfdir@%$sysconfdir%g
+s%@sharedstatedir@%$sharedstatedir%g
+s%@localstatedir@%$localstatedir%g
+s%@libdir@%$libdir%g
+s%@includedir@%$includedir%g
+s%@oldincludedir@%$oldincludedir%g
+s%@infodir@%$infodir%g
+s%@mandir@%$mandir%g
+s%@host@%$host%g
+s%@host_alias@%$host_alias%g
+s%@host_cpu@%$host_cpu%g
+s%@host_vendor@%$host_vendor%g
+s%@host_os@%$host_os%g
+s%@target@%$target%g
+s%@target_alias@%$target_alias%g
+s%@target_cpu@%$target_cpu%g
+s%@target_vendor@%$target_vendor%g
+s%@target_os@%$target_os%g
+s%@build@%$build%g
+s%@build_alias@%$build_alias%g
+s%@build_cpu@%$build_cpu%g
+s%@build_vendor@%$build_vendor%g
+s%@build_os@%$build_os%g
+s%@CC@%$CC%g
+s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g
+s%@INSTALL_SCRIPT@%$INSTALL_SCRIPT%g
+s%@INSTALL_DATA@%$INSTALL_DATA%g
+s%@CC_FOR_BUILD@%$CC_FOR_BUILD%g
+s%@HDEFINES@%$HDEFINES%g
+s%@AR@%$AR%g
+s%@RANLIB@%$RANLIB%g
+s%@SET_MAKE@%$SET_MAKE%g
+s%@CPP@%$CPP%g
+s%@ALLOCA@%$ALLOCA%g
+s%@USE_NLS@%$USE_NLS%g
+s%@MSGFMT@%$MSGFMT%g
+s%@GMSGFMT@%$GMSGFMT%g
+s%@XGETTEXT@%$XGETTEXT%g
+s%@USE_INCLUDED_LIBINTL@%$USE_INCLUDED_LIBINTL%g
+s%@CATALOGS@%$CATALOGS%g
+s%@CATOBJEXT@%$CATOBJEXT%g
+s%@DATADIRNAME@%$DATADIRNAME%g
+s%@GMOFILES@%$GMOFILES%g
+s%@INSTOBJEXT@%$INSTOBJEXT%g
+s%@INTLDEPS@%$INTLDEPS%g
+s%@INTLLIBS@%$INTLLIBS%g
+s%@INTLOBJS@%$INTLOBJS%g
+s%@POFILES@%$POFILES%g
+s%@POSUB@%$POSUB%g
+s%@INCLUDE_LOCALE_H@%$INCLUDE_LOCALE_H%g
+s%@GT_NO@%$GT_NO%g
+s%@GT_YES@%$GT_YES%g
+s%@MKINSTALLDIRS@%$MKINSTALLDIRS%g
+s%@l@%$l%g
+s%@MAINT@%$MAINT%g
+s%@sim_bswap@%$sim_bswap%g
+s%@sim_cflags@%$sim_cflags%g
+s%@sim_debug@%$sim_debug%g
+s%@sim_stdio@%$sim_stdio%g
+s%@sim_trace@%$sim_trace%g
+s%@sim_profile@%$sim_profile%g
+s%@EXEEXT@%$EXEEXT%g
+s%@CGEN_MAINT@%$CGEN_MAINT%g
+s%@cgendir@%$cgendir%g
+s%@cgen@%$cgen%g
+
+CEOF
+EOF
+
+cat >> $CONFIG_STATUS <<\EOF
+
+# Split the substitutions into bite-sized pieces for seds with
+# small command number limits, like on Digital OSF/1 and HP-UX.
+ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script.
+ac_file=1 # Number of current file.
+ac_beg=1 # First line for current file.
+ac_end=$ac_max_sed_cmds # Line after last line for current file.
+ac_more_lines=:
+ac_sed_cmds=""
+while $ac_more_lines; do
+ if test $ac_beg -gt 1; then
+ sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file
+ else
+ sed "${ac_end}q" conftest.subs > conftest.s$ac_file
+ fi
+ if test ! -s conftest.s$ac_file; then
+ ac_more_lines=false
+ rm -f conftest.s$ac_file
+ else
+ if test -z "$ac_sed_cmds"; then
+ ac_sed_cmds="sed -f conftest.s$ac_file"
+ else
+ ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file"
+ fi
+ ac_file=`expr $ac_file + 1`
+ ac_beg=$ac_end
+ ac_end=`expr $ac_end + $ac_max_sed_cmds`
+ fi
+done
+if test -z "$ac_sed_cmds"; then
+ ac_sed_cmds=cat
+fi
+EOF
+
+cat >> $CONFIG_STATUS <<EOF
+
+CONFIG_FILES=\${CONFIG_FILES-"Makefile.sim:Makefile.in Make-common.sim:../common/Make-common.in .gdbinit:../common/gdbinit.in"}
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then
+ # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+ case "$ac_file" in
+ *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
+ ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
+ *) ac_file_in="${ac_file}.in" ;;
+ esac
+
+ # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories.
+
+ # Remove last slash and all that follows it. Not all systems have dirname.
+ ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
+ if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
+ # The file is in a subdirectory.
+ test ! -d "$ac_dir" && mkdir "$ac_dir"
+ ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`"
+ # A "../" for each directory in $ac_dir_suffix.
+ ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'`
+ else
+ ac_dir_suffix= ac_dots=
+ fi
+
+ case "$ac_given_srcdir" in
+ .) srcdir=.
+ if test -z "$ac_dots"; then top_srcdir=.
+ else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;;
+ /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;;
+ *) # Relative path.
+ srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix"
+ top_srcdir="$ac_dots$ac_given_srcdir" ;;
+ esac
+
+ case "$ac_given_INSTALL" in
+ [/$]*) INSTALL="$ac_given_INSTALL" ;;
+ *) INSTALL="$ac_dots$ac_given_INSTALL" ;;
+ esac
+
+ echo creating "$ac_file"
+ rm -f "$ac_file"
+ configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure."
+ case "$ac_file" in
+ *Makefile*) ac_comsub="1i\\
+# $configure_input" ;;
+ *) ac_comsub= ;;
+ esac
+
+ ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
+ sed -e "$ac_comsub
+s%@configure_input@%$configure_input%g
+s%@srcdir@%$srcdir%g
+s%@top_srcdir@%$top_srcdir%g
+s%@INSTALL@%$INSTALL%g
+" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file
+fi; done
+rm -f conftest.s*
+
+# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where
+# NAME is the cpp macro being defined and VALUE is the value it is being given.
+#
+# ac_d sets the value in "#define NAME VALUE" lines.
+ac_dA='s%^\([ ]*\)#\([ ]*define[ ][ ]*\)'
+ac_dB='\([ ][ ]*\)[^ ]*%\1#\2'
+ac_dC='\3'
+ac_dD='%g'
+# ac_u turns "#undef NAME" with trailing blanks into "#define NAME VALUE".
+ac_uA='s%^\([ ]*\)#\([ ]*\)undef\([ ][ ]*\)'
+ac_uB='\([ ]\)%\1#\2define\3'
+ac_uC=' '
+ac_uD='\4%g'
+# ac_e turns "#undef NAME" without trailing blanks into "#define NAME VALUE".
+ac_eA='s%^\([ ]*\)#\([ ]*\)undef\([ ][ ]*\)'
+ac_eB='$%\1#\2define\3'
+ac_eC=' '
+ac_eD='%g'
+
+if test "${CONFIG_HEADERS+set}" != set; then
+EOF
+cat >> $CONFIG_STATUS <<EOF
+ CONFIG_HEADERS="config.h:config.in"
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+fi
+for ac_file in .. $CONFIG_HEADERS; do if test "x$ac_file" != x..; then
+ # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+ case "$ac_file" in
+ *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
+ ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
+ *) ac_file_in="${ac_file}.in" ;;
+ esac
+
+ echo creating $ac_file
+
+ rm -f conftest.frag conftest.in conftest.out
+ ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
+ cat $ac_file_inputs > conftest.in
+
+EOF
+
+# Transform confdefs.h into a sed script conftest.vals that substitutes
+# the proper values into config.h.in to produce config.h. And first:
+# Protect against being on the right side of a sed subst in config.status.
+# Protect against being in an unquoted here document in config.status.
+rm -f conftest.vals
+cat > conftest.hdr <<\EOF
+s/[\\&%]/\\&/g
+s%[\\$`]%\\&%g
+s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD}%gp
+s%ac_d%ac_u%gp
+s%ac_u%ac_e%gp
+EOF
+sed -n -f conftest.hdr confdefs.h > conftest.vals
+rm -f conftest.hdr
+
+# This sed command replaces #undef with comments. This is necessary, for
+# example, in the case of _POSIX_SOURCE, which is predefined and required
+# on some systems where configure will not decide to define it.
+cat >> conftest.vals <<\EOF
+s%^[ ]*#[ ]*undef[ ][ ]*[a-zA-Z_][a-zA-Z_0-9]*%/* & */%
+EOF
+
+# Break up conftest.vals because some shells have a limit on
+# the size of here documents, and old seds have small limits too.
+
+rm -f conftest.tail
+while :
+do
+ ac_lines=`grep -c . conftest.vals`
+ # grep -c gives empty output for an empty file on some AIX systems.
+ if test -z "$ac_lines" || test "$ac_lines" -eq 0; then break; fi
+ # Write a limited-size here document to conftest.frag.
+ echo ' cat > conftest.frag <<CEOF' >> $CONFIG_STATUS
+ sed ${ac_max_here_lines}q conftest.vals >> $CONFIG_STATUS
+ echo 'CEOF
+ sed -f conftest.frag conftest.in > conftest.out
+ rm -f conftest.in
+ mv conftest.out conftest.in
+' >> $CONFIG_STATUS
+ sed 1,${ac_max_here_lines}d conftest.vals > conftest.tail
+ rm -f conftest.vals
+ mv conftest.tail conftest.vals
+done
+rm -f conftest.vals
+
+cat >> $CONFIG_STATUS <<\EOF
+ rm -f conftest.frag conftest.h
+ echo "/* $ac_file. Generated automatically by configure. */" > conftest.h
+ cat conftest.in >> conftest.h
+ rm -f conftest.in
+ if cmp -s $ac_file conftest.h 2>/dev/null; then
+ echo "$ac_file is unchanged"
+ rm -f conftest.h
+ else
+ # Remove last slash and all that follows it. Not all systems have dirname.
+ ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
+ if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
+ # The file is in a subdirectory.
+ test ! -d "$ac_dir" && mkdir "$ac_dir"
+ fi
+ rm -f $ac_file
+ mv conftest.h $ac_file
+ fi
+fi; done
+
+EOF
+
+cat >> $CONFIG_STATUS <<EOF
+ac_sources="$sim_link_files"
+ac_dests="$sim_link_links"
+EOF
+
+cat >> $CONFIG_STATUS <<\EOF
+srcdir=$ac_given_srcdir
+while test -n "$ac_sources"; do
+ set $ac_dests; ac_dest=$1; shift; ac_dests=$*
+ set $ac_sources; ac_source=$1; shift; ac_sources=$*
+
+ echo "linking $srcdir/$ac_source to $ac_dest"
+
+ if test ! -r $srcdir/$ac_source; then
+ { echo "configure: error: $srcdir/$ac_source: File not found" 1>&2; exit 1; }
+ fi
+ rm -f $ac_dest
+
+ # Make relative symlinks.
+ # Remove last slash and all that follows it. Not all systems have dirname.
+ ac_dest_dir=`echo $ac_dest|sed 's%/[^/][^/]*$%%'`
+ if test "$ac_dest_dir" != "$ac_dest" && test "$ac_dest_dir" != .; then
+ # The dest file is in a subdirectory.
+ test ! -d "$ac_dest_dir" && mkdir "$ac_dest_dir"
+ ac_dest_dir_suffix="/`echo $ac_dest_dir|sed 's%^\./%%'`"
+ # A "../" for each directory in $ac_dest_dir_suffix.
+ ac_dots=`echo $ac_dest_dir_suffix|sed 's%/[^/]*%../%g'`
+ else
+ ac_dest_dir_suffix= ac_dots=
+ fi
+
+ case "$srcdir" in
+ [/$]*) ac_rel_source="$srcdir/$ac_source" ;;
+ *) ac_rel_source="$ac_dots$srcdir/$ac_source" ;;
+ esac
+
+ # Make a symlink if possible; otherwise try a hard link.
+ if ln -s $ac_rel_source $ac_dest 2>/dev/null ||
+ ln $srcdir/$ac_source $ac_dest; then :
+ else
+ { echo "configure: error: can not link $ac_dest to $srcdir/$ac_source" 1>&2; exit 1; }
+ fi
+done
+EOF
+cat >> $CONFIG_STATUS <<EOF
+
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+case "x$CONFIG_FILES" in
+ xMakefile*)
+ echo "Merging Makefile.sim+Make-common.sim into Makefile ..."
+ rm -f Makesim1.tmp Makesim2.tmp Makefile
+ sed -n -e '/^## COMMON_PRE_/,/^## End COMMON_PRE_/ p' <Make-common.sim >Makesim1.tmp
+ sed -n -e '/^## COMMON_POST_/,/^## End COMMON_POST_/ p' <Make-common.sim >Makesim2.tmp
+ sed -e '/^## COMMON_PRE_/ r Makesim1.tmp' \
+ -e '/^## COMMON_POST_/ r Makesim2.tmp' \
+ <Makefile.sim >Makefile
+ rm -f Makefile.sim Make-common.sim Makesim1.tmp Makesim2.tmp
+ ;;
+ esac
+ case "x$CONFIG_HEADERS" in xconfig.h:config.in) echo > stamp-h ;; esac
+
+exit 0
+EOF
+chmod +x $CONFIG_STATUS
+rm -fr confdefs* $ac_clean_files
+test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1
+
+
--- /dev/null
+dnl Process this file with autoconf to produce a configure script.
+sinclude(../common/aclocal.m4)
+AC_PREREQ(2.5)dnl
+AC_INIT(Makefile.in)
+
+SIM_AC_COMMON
+
+SIM_AC_OPTION_ENDIAN([], BIG_ENDIAN)
+SIM_AC_OPTION_ALIGNMENT(STRICT_ALIGNMENT)
+SIM_AC_OPTION_HOSTENDIAN
+SIM_AC_OPTION_SCACHE(16384)
+SIM_AC_OPTION_DEFAULT_MODEL(sh5)
+SIM_AC_OPTION_ENVIRONMENT
+SIM_AC_OPTION_INLINE()
+SIM_AC_OPTION_CGEN_MAINT
+
+SIM_AC_OUTPUT
--- /dev/null
+/* Misc. support for CPU family sh64.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU sh64
+#define WANT_CPU_SH64
+
+#include "sim-main.h"
+#include "cgen-ops.h"
+
+/* Get the value of h-pc. */
+
+UDI
+sh64_h_pc_get (SIM_CPU *current_cpu)
+{
+ return GET_H_PC ();
+}
+
+/* Set a value for h-pc. */
+
+void
+sh64_h_pc_set (SIM_CPU *current_cpu, UDI newval)
+{
+ SET_H_PC (newval);
+}
+
+/* Get the value of h-gr. */
+
+DI
+sh64_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_GR (regno);
+}
+
+/* Set a value for h-gr. */
+
+void
+sh64_h_gr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
+{
+ SET_H_GR (regno, newval);
+}
+
+/* Get the value of h-grc. */
+
+SI
+sh64_h_grc_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_GRC (regno);
+}
+
+/* Set a value for h-grc. */
+
+void
+sh64_h_grc_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+ SET_H_GRC (regno, newval);
+}
+
+/* Get the value of h-cr. */
+
+DI
+sh64_h_cr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_CR (regno);
+}
+
+/* Set a value for h-cr. */
+
+void
+sh64_h_cr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
+{
+ SET_H_CR (regno, newval);
+}
+
+/* Get the value of h-sr. */
+
+SI
+sh64_h_sr_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_sr);
+}
+
+/* Set a value for h-sr. */
+
+void
+sh64_h_sr_set (SIM_CPU *current_cpu, SI newval)
+{
+ CPU (h_sr) = newval;
+}
+
+/* Get the value of h-fpscr. */
+
+SI
+sh64_h_fpscr_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_fpscr);
+}
+
+/* Set a value for h-fpscr. */
+
+void
+sh64_h_fpscr_set (SIM_CPU *current_cpu, SI newval)
+{
+ CPU (h_fpscr) = newval;
+}
+
+/* Get the value of h-frbit. */
+
+BI
+sh64_h_frbit_get (SIM_CPU *current_cpu)
+{
+ return GET_H_FRBIT ();
+}
+
+/* Set a value for h-frbit. */
+
+void
+sh64_h_frbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_FRBIT (newval);
+}
+
+/* Get the value of h-szbit. */
+
+BI
+sh64_h_szbit_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SZBIT ();
+}
+
+/* Set a value for h-szbit. */
+
+void
+sh64_h_szbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_SZBIT (newval);
+}
+
+/* Get the value of h-prbit. */
+
+BI
+sh64_h_prbit_get (SIM_CPU *current_cpu)
+{
+ return GET_H_PRBIT ();
+}
+
+/* Set a value for h-prbit. */
+
+void
+sh64_h_prbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_PRBIT (newval);
+}
+
+/* Get the value of h-sbit. */
+
+BI
+sh64_h_sbit_get (SIM_CPU *current_cpu)
+{
+ return GET_H_SBIT ();
+}
+
+/* Set a value for h-sbit. */
+
+void
+sh64_h_sbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_SBIT (newval);
+}
+
+/* Get the value of h-mbit. */
+
+BI
+sh64_h_mbit_get (SIM_CPU *current_cpu)
+{
+ return GET_H_MBIT ();
+}
+
+/* Set a value for h-mbit. */
+
+void
+sh64_h_mbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_MBIT (newval);
+}
+
+/* Get the value of h-qbit. */
+
+BI
+sh64_h_qbit_get (SIM_CPU *current_cpu)
+{
+ return GET_H_QBIT ();
+}
+
+/* Set a value for h-qbit. */
+
+void
+sh64_h_qbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_QBIT (newval);
+}
+
+/* Get the value of h-fr. */
+
+SF
+sh64_h_fr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return CPU (h_fr[regno]);
+}
+
+/* Set a value for h-fr. */
+
+void
+sh64_h_fr_set (SIM_CPU *current_cpu, UINT regno, SF newval)
+{
+ CPU (h_fr[regno]) = newval;
+}
+
+/* Get the value of h-fp. */
+
+DF
+sh64_h_fp_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return CPU (h_fp[regno]);
+}
+
+/* Set a value for h-fp. */
+
+void
+sh64_h_fp_set (SIM_CPU *current_cpu, UINT regno, DF newval)
+{
+ CPU (h_fp[regno]) = newval;
+}
+
+/* Get the value of h-fv. */
+
+SF
+sh64_h_fv_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_FV (regno);
+}
+
+/* Set a value for h-fv. */
+
+void
+sh64_h_fv_set (SIM_CPU *current_cpu, UINT regno, SF newval)
+{
+ SET_H_FV (regno, newval);
+}
+
+/* Get the value of h-fmtx. */
+
+SF
+sh64_h_fmtx_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_FMTX (regno);
+}
+
+/* Set a value for h-fmtx. */
+
+void
+sh64_h_fmtx_set (SIM_CPU *current_cpu, UINT regno, SF newval)
+{
+ SET_H_FMTX (regno, newval);
+}
+
+/* Get the value of h-dr. */
+
+DF
+sh64_h_dr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_DR (regno);
+}
+
+/* Set a value for h-dr. */
+
+void
+sh64_h_dr_set (SIM_CPU *current_cpu, UINT regno, DF newval)
+{
+ SET_H_DR (regno, newval);
+}
+
+/* Get the value of h-tr. */
+
+DI
+sh64_h_tr_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return CPU (h_tr[regno]);
+}
+
+/* Set a value for h-tr. */
+
+void
+sh64_h_tr_set (SIM_CPU *current_cpu, UINT regno, DI newval)
+{
+ CPU (h_tr[regno]) = newval;
+}
+
+/* Get the value of h-endian. */
+
+BI
+sh64_h_endian_get (SIM_CPU *current_cpu)
+{
+ return GET_H_ENDIAN ();
+}
+
+/* Set a value for h-endian. */
+
+void
+sh64_h_endian_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_ENDIAN (newval);
+}
+
+/* Get the value of h-ism. */
+
+BI
+sh64_h_ism_get (SIM_CPU *current_cpu)
+{
+ return GET_H_ISM ();
+}
+
+/* Set a value for h-ism. */
+
+void
+sh64_h_ism_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_ISM (newval);
+}
+
+/* Get the value of h-frc. */
+
+SF
+sh64_h_frc_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_FRC (regno);
+}
+
+/* Set a value for h-frc. */
+
+void
+sh64_h_frc_set (SIM_CPU *current_cpu, UINT regno, SF newval)
+{
+ SET_H_FRC (regno, newval);
+}
+
+/* Get the value of h-drc. */
+
+DF
+sh64_h_drc_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_DRC (regno);
+}
+
+/* Set a value for h-drc. */
+
+void
+sh64_h_drc_set (SIM_CPU *current_cpu, UINT regno, DF newval)
+{
+ SET_H_DRC (regno, newval);
+}
+
+/* Get the value of h-xf. */
+
+SF
+sh64_h_xf_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_XF (regno);
+}
+
+/* Set a value for h-xf. */
+
+void
+sh64_h_xf_set (SIM_CPU *current_cpu, UINT regno, SF newval)
+{
+ SET_H_XF (regno, newval);
+}
+
+/* Get the value of h-xd. */
+
+DF
+sh64_h_xd_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_XD (regno);
+}
+
+/* Set a value for h-xd. */
+
+void
+sh64_h_xd_set (SIM_CPU *current_cpu, UINT regno, DF newval)
+{
+ SET_H_XD (regno, newval);
+}
+
+/* Get the value of h-fvc. */
+
+SF
+sh64_h_fvc_get (SIM_CPU *current_cpu, UINT regno)
+{
+ return GET_H_FVC (regno);
+}
+
+/* Set a value for h-fvc. */
+
+void
+sh64_h_fvc_set (SIM_CPU *current_cpu, UINT regno, SF newval)
+{
+ SET_H_FVC (regno, newval);
+}
+
+/* Get the value of h-fpccr. */
+
+SI
+sh64_h_fpccr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_FPCCR ();
+}
+
+/* Set a value for h-fpccr. */
+
+void
+sh64_h_fpccr_set (SIM_CPU *current_cpu, SI newval)
+{
+ SET_H_FPCCR (newval);
+}
+
+/* Get the value of h-gbr. */
+
+SI
+sh64_h_gbr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_GBR ();
+}
+
+/* Set a value for h-gbr. */
+
+void
+sh64_h_gbr_set (SIM_CPU *current_cpu, SI newval)
+{
+ SET_H_GBR (newval);
+}
+
+/* Get the value of h-pr. */
+
+SI
+sh64_h_pr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_PR ();
+}
+
+/* Set a value for h-pr. */
+
+void
+sh64_h_pr_set (SIM_CPU *current_cpu, SI newval)
+{
+ SET_H_PR (newval);
+}
+
+/* Get the value of h-macl. */
+
+SI
+sh64_h_macl_get (SIM_CPU *current_cpu)
+{
+ return GET_H_MACL ();
+}
+
+/* Set a value for h-macl. */
+
+void
+sh64_h_macl_set (SIM_CPU *current_cpu, SI newval)
+{
+ SET_H_MACL (newval);
+}
+
+/* Get the value of h-mach. */
+
+SI
+sh64_h_mach_get (SIM_CPU *current_cpu)
+{
+ return GET_H_MACH ();
+}
+
+/* Set a value for h-mach. */
+
+void
+sh64_h_mach_set (SIM_CPU *current_cpu, SI newval)
+{
+ SET_H_MACH (newval);
+}
+
+/* Get the value of h-tbit. */
+
+BI
+sh64_h_tbit_get (SIM_CPU *current_cpu)
+{
+ return GET_H_TBIT ();
+}
+
+/* Set a value for h-tbit. */
+
+void
+sh64_h_tbit_set (SIM_CPU *current_cpu, BI newval)
+{
+ SET_H_TBIT (newval);
+}
+
+/* Record trace results for INSN. */
+
+void
+sh64_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+ int *indices, TRACE_RECORD *tr)
+{
+}
--- /dev/null
+/* CPU family header for sh64.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef CPU_SH64_H
+#define CPU_SH64_H
+
+/* Maximum number of instructions that are fetched at a time.
+ This is for LIW type instructions sets (e.g. m32r). */
+#define MAX_LIW_INSNS 1
+
+/* Maximum number of instructions that can be executed in parallel. */
+#define MAX_PARALLEL_INSNS 1
+
+/* CPU state information. */
+typedef struct {
+ /* Hardware elements. */
+ struct {
+ /* Program counter */
+ UDI h_pc;
+#define GET_H_PC() CPU (h_pc)
+#define SET_H_PC(x) \
+do { \
+{\
+CPU (h_ism) = ANDDI ((x), 1);\
+CPU (h_pc) = ANDDI ((x), INVDI (1));\
+}\
+;} while (0)
+ /* General purpose integer registers */
+ DI h_gr[64];
+#define GET_H_GR(index) ((((index) == (63))) ? (0) : (CPU (h_gr[index])))
+#define SET_H_GR(index, x) \
+do { \
+if ((((index)) != (63))) {\
+CPU (h_gr[(index)]) = (x);\
+} else {\
+((void) 0); /*nop*/\
+}\
+;} while (0)
+ /* Control registers */
+ DI h_cr[64];
+#define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index])))
+#define SET_H_CR(index, x) \
+do { \
+if ((((index)) == (0))) {\
+CPU (h_sr) = (x);\
+} else {\
+CPU (h_cr[(index)]) = (x);\
+}\
+;} while (0)
+ /* Status register */
+ SI h_sr;
+#define GET_H_SR() CPU (h_sr)
+#define SET_H_SR(x) (CPU (h_sr) = (x))
+ /* Floating point status and control register */
+ SI h_fpscr;
+#define GET_H_FPSCR() CPU (h_fpscr)
+#define SET_H_FPSCR(x) (CPU (h_fpscr) = (x))
+ /* Single precision floating point registers */
+ SF h_fr[64];
+#define GET_H_FR(a1) CPU (h_fr)[a1]
+#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x))
+ /* Single precision floating point register pairs */
+ DF h_fp[32];
+#define GET_H_FP(a1) CPU (h_fp)[a1]
+#define SET_H_FP(a1, x) (CPU (h_fp)[a1] = (x))
+ /* Branch target registers */
+ DI h_tr[8];
+#define GET_H_TR(a1) CPU (h_tr)[a1]
+#define SET_H_TR(a1, x) (CPU (h_tr)[a1] = (x))
+ /* Current instruction set mode */
+ BI h_ism;
+#define GET_H_ISM() CPU (h_ism)
+#define SET_H_ISM(x) \
+do { \
+cgen_rtx_error (current_cpu, "cannot set ism directly");\
+;} while (0)
+ } hardware;
+#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
+} SH64_CPU_DATA;
+
+/* Virtual regs. */
+
+#define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff))
+#define SET_H_GRC(index, x) \
+do { \
+CPU (h_gr[(index)]) = EXTSIDI ((x));\
+;} while (0)
+#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_sr), 14), 1)
+#define SET_H_FRBIT(x) \
+do { \
+CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (14))))), SLLSI ((x), 14));\
+;} while (0)
+#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_sr), 13), 1)
+#define SET_H_SZBIT(x) \
+do { \
+CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (13))))), SLLSI ((x), 13));\
+;} while (0)
+#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_sr), 12), 1)
+#define SET_H_PRBIT(x) \
+do { \
+CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (12))))), SLLSI ((x), 12));\
+;} while (0)
+#define GET_H_SBIT() ANDSI (SRLSI (CPU (h_sr), 1), 1)
+#define SET_H_SBIT(x) \
+do { \
+CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (2))), SLLSI ((x), 1));\
+;} while (0)
+#define GET_H_MBIT() ANDSI (SRLSI (CPU (h_sr), 9), 1)
+#define SET_H_MBIT(x) \
+do { \
+CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (9))))), SLLSI ((x), 9));\
+;} while (0)
+#define GET_H_QBIT() ANDSI (SRLSI (CPU (h_sr), 8), 1)
+#define SET_H_QBIT(x) \
+do { \
+CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (8))))), SLLSI ((x), 8));\
+;} while (0)
+#define GET_H_FV(index) CPU (h_fr[MULQI (ANDQI (index, 15), 4)])
+#define SET_H_FV(index, x) \
+do { \
+CPU (h_fr[MULQI (ANDQI ((index), 15), 4)]) = (x);\
+;} while (0)
+#define GET_H_FMTX(index) CPU (h_fr[MULQI (ANDQI (index, 3), 16)])
+#define SET_H_FMTX(index, x) \
+do { \
+CPU (h_fr[MULQI (ANDQI ((index), 3), 16)]) = (x);\
+;} while (0)
+#define GET_H_DR(index) SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[index]))), 32), ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[((index) + (1))])))))
+#define SET_H_DR(index, x) \
+do { \
+{\
+CPU (h_fr[(index)]) = SUBWORDSISF (SUBWORDDFSI ((x), 0));\
+CPU (h_fr[(((index)) + (1))]) = SUBWORDSISF (SUBWORDDFSI ((x), 1));\
+}\
+;} while (0)
+#define GET_H_ENDIAN() sh64_endian (current_cpu)
+#define SET_H_ENDIAN(x) \
+do { \
+cgen_rtx_error (current_cpu, "cannot alter target byte order mid-program");\
+;} while (0)
+#define GET_H_FRC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
+#define SET_H_FRC(index, x) \
+do { \
+CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
+;} while (0)
+#define GET_H_DRC(index) GET_H_DR (((((16) * (GET_H_FRBIT ()))) + (index)))
+#define SET_H_DRC(index, x) \
+do { \
+SET_H_DR (((((16) * (GET_H_FRBIT ()))) + ((index))), (x));\
+;} while (0)
+#define GET_H_XF(index) CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))])
+#define SET_H_XF(index, x) \
+do { \
+CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index)))]) = (x);\
+;} while (0)
+#define GET_H_XD(index) GET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + (index)))
+#define SET_H_XD(index, x) \
+do { \
+SET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index))), (x));\
+;} while (0)
+#define GET_H_FVC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))])
+#define SET_H_FVC(index, x) \
+do { \
+CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\
+;} while (0)
+#define GET_H_FPCCR() ORSI (ORSI (ORSI (CPU (h_fpscr), SLLSI (GET_H_PRBIT (), 19)), SLLSI (GET_H_SZBIT (), 20)), SLLSI (GET_H_FRBIT (), 21))
+#define SET_H_FPCCR(x) \
+do { \
+{\
+CPU (h_fpscr) = (x);\
+SET_H_PRBIT (ANDSI (SRLSI ((x), 19), 1));\
+SET_H_SZBIT (ANDSI (SRLSI ((x), 20), 1));\
+SET_H_FRBIT (ANDSI (SRLSI ((x), 21), 1));\
+}\
+;} while (0)
+#define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1)
+#define SET_H_GBR(x) \
+do { \
+CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\
+;} while (0)
+#define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UINT) 18)]), 1)
+#define SET_H_PR(x) \
+do { \
+CPU (h_gr[((UINT) 18)]) = EXTSIDI ((x));\
+;} while (0)
+#define GET_H_MACL() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)
+#define SET_H_MACL(x) \
+do { \
+CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)), 32), ZEXTSIDI ((x)));\
+;} while (0)
+#define GET_H_MACH() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)
+#define SET_H_MACH(x) \
+do { \
+CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI ((x)), 32), ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)));\
+;} while (0)
+#define GET_H_TBIT() ANDBI (CPU (h_gr[((UINT) 19)]), 1)
+#define SET_H_TBIT(x) \
+do { \
+CPU (h_gr[((UINT) 19)]) = ORDI (ANDDI (CPU (h_gr[((UINT) 19)]), INVDI (1)), ZEXTBIDI ((x)));\
+;} while (0)
+
+/* Cover fns for register access. */
+UDI sh64_h_pc_get (SIM_CPU *);
+void sh64_h_pc_set (SIM_CPU *, UDI);
+DI sh64_h_gr_get (SIM_CPU *, UINT);
+void sh64_h_gr_set (SIM_CPU *, UINT, DI);
+SI sh64_h_grc_get (SIM_CPU *, UINT);
+void sh64_h_grc_set (SIM_CPU *, UINT, SI);
+DI sh64_h_cr_get (SIM_CPU *, UINT);
+void sh64_h_cr_set (SIM_CPU *, UINT, DI);
+SI sh64_h_sr_get (SIM_CPU *);
+void sh64_h_sr_set (SIM_CPU *, SI);
+SI sh64_h_fpscr_get (SIM_CPU *);
+void sh64_h_fpscr_set (SIM_CPU *, SI);
+BI sh64_h_frbit_get (SIM_CPU *);
+void sh64_h_frbit_set (SIM_CPU *, BI);
+BI sh64_h_szbit_get (SIM_CPU *);
+void sh64_h_szbit_set (SIM_CPU *, BI);
+BI sh64_h_prbit_get (SIM_CPU *);
+void sh64_h_prbit_set (SIM_CPU *, BI);
+BI sh64_h_sbit_get (SIM_CPU *);
+void sh64_h_sbit_set (SIM_CPU *, BI);
+BI sh64_h_mbit_get (SIM_CPU *);
+void sh64_h_mbit_set (SIM_CPU *, BI);
+BI sh64_h_qbit_get (SIM_CPU *);
+void sh64_h_qbit_set (SIM_CPU *, BI);
+SF sh64_h_fr_get (SIM_CPU *, UINT);
+void sh64_h_fr_set (SIM_CPU *, UINT, SF);
+DF sh64_h_fp_get (SIM_CPU *, UINT);
+void sh64_h_fp_set (SIM_CPU *, UINT, DF);
+SF sh64_h_fv_get (SIM_CPU *, UINT);
+void sh64_h_fv_set (SIM_CPU *, UINT, SF);
+SF sh64_h_fmtx_get (SIM_CPU *, UINT);
+void sh64_h_fmtx_set (SIM_CPU *, UINT, SF);
+DF sh64_h_dr_get (SIM_CPU *, UINT);
+void sh64_h_dr_set (SIM_CPU *, UINT, DF);
+DI sh64_h_tr_get (SIM_CPU *, UINT);
+void sh64_h_tr_set (SIM_CPU *, UINT, DI);
+BI sh64_h_endian_get (SIM_CPU *);
+void sh64_h_endian_set (SIM_CPU *, BI);
+BI sh64_h_ism_get (SIM_CPU *);
+void sh64_h_ism_set (SIM_CPU *, BI);
+SF sh64_h_frc_get (SIM_CPU *, UINT);
+void sh64_h_frc_set (SIM_CPU *, UINT, SF);
+DF sh64_h_drc_get (SIM_CPU *, UINT);
+void sh64_h_drc_set (SIM_CPU *, UINT, DF);
+SF sh64_h_xf_get (SIM_CPU *, UINT);
+void sh64_h_xf_set (SIM_CPU *, UINT, SF);
+DF sh64_h_xd_get (SIM_CPU *, UINT);
+void sh64_h_xd_set (SIM_CPU *, UINT, DF);
+SF sh64_h_fvc_get (SIM_CPU *, UINT);
+void sh64_h_fvc_set (SIM_CPU *, UINT, SF);
+SI sh64_h_fpccr_get (SIM_CPU *);
+void sh64_h_fpccr_set (SIM_CPU *, SI);
+SI sh64_h_gbr_get (SIM_CPU *);
+void sh64_h_gbr_set (SIM_CPU *, SI);
+SI sh64_h_pr_get (SIM_CPU *);
+void sh64_h_pr_set (SIM_CPU *, SI);
+SI sh64_h_macl_get (SIM_CPU *);
+void sh64_h_macl_set (SIM_CPU *, SI);
+SI sh64_h_mach_get (SIM_CPU *);
+void sh64_h_mach_set (SIM_CPU *, SI);
+BI sh64_h_tbit_get (SIM_CPU *);
+void sh64_h_tbit_set (SIM_CPU *, BI);
+
+/* These must be hand-written. */
+extern CPUREG_FETCH_FN sh64_fetch_register;
+extern CPUREG_STORE_FN sh64_store_register;
+
+typedef struct {
+ int empty;
+} MODEL_SH5_DATA;
+
+/* Collection of various things for the trace handler to use. */
+
+typedef struct trace_record {
+ IADDR pc;
+ /* FIXME:wip */
+} TRACE_RECORD;
+
+#endif /* CPU_SH64_H */
--- /dev/null
+/* Simulator CPU header for sh.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef SH_CPUALL_H
+#define SH_CPUALL_H
+
+/* Include files for each cpu family. */
+
+#ifdef WANT_CPU_SH64
+#include "eng.h"
+#include "cgen-engine.h"
+#include "cpu.h"
+#include "decode.h"
+#endif
+
+extern const MACH sh2_mach;
+extern const MACH sh3_mach;
+extern const MACH sh3e_mach;
+extern const MACH sh4_mach;
+extern const MACH sh5_mach;
+
+#ifndef WANT_CPU
+/* The ARGBUF struct. */
+struct argbuf {
+ /* These are the baseclass definitions. */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
+ /* cpu specific data follows */
+};
+#endif
+
+#ifndef WANT_CPU
+/* A cached insn.
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
+
+struct scache {
+ struct argbuf argbuf;
+};
+#endif
+
+#endif /* SH_CPUALL_H */
--- /dev/null
+/* Simulator instruction decoder for sh64_compact.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU sh64
+#define WANT_CPU_SH64
+
+#include "sim-main.h"
+#include "sim-assert.h"
+
+/* The instruction descriptor array.
+ This is computed at runtime. Space for it is not malloc'd to save a
+ teensy bit of cpu in the decoder. Moving it to malloc space is trivial
+ but won't be done until necessary (we don't currently support the runtime
+ addition of instructions nor an SMP machine with different cpus). */
+static IDESC sh64_compact_insn_data[SH64_COMPACT_INSN_MAX];
+
+/* Commas between elements are contained in the macros.
+ Some of these are conditionally compiled out. */
+
+static const struct insn_sem sh64_compact_insn_sem[] =
+{
+ { VIRTUAL_INSN_X_INVALID, SH64_COMPACT_INSN_X_INVALID, SH64_COMPACT_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_AFTER, SH64_COMPACT_INSN_X_AFTER, SH64_COMPACT_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEFORE, SH64_COMPACT_INSN_X_BEFORE, SH64_COMPACT_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CTI_CHAIN, SH64_COMPACT_INSN_X_CTI_CHAIN, SH64_COMPACT_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CHAIN, SH64_COMPACT_INSN_X_CHAIN, SH64_COMPACT_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEGIN, SH64_COMPACT_INSN_X_BEGIN, SH64_COMPACT_SFMT_EMPTY },
+ { SH_INSN_ADD_COMPACT, SH64_COMPACT_INSN_ADD_COMPACT, SH64_COMPACT_SFMT_ADD_COMPACT },
+ { SH_INSN_ADDI_COMPACT, SH64_COMPACT_INSN_ADDI_COMPACT, SH64_COMPACT_SFMT_ADDI_COMPACT },
+ { SH_INSN_ADDC_COMPACT, SH64_COMPACT_INSN_ADDC_COMPACT, SH64_COMPACT_SFMT_ADDC_COMPACT },
+ { SH_INSN_ADDV_COMPACT, SH64_COMPACT_INSN_ADDV_COMPACT, SH64_COMPACT_SFMT_ADDV_COMPACT },
+ { SH_INSN_AND_COMPACT, SH64_COMPACT_INSN_AND_COMPACT, SH64_COMPACT_SFMT_AND_COMPACT },
+ { SH_INSN_ANDI_COMPACT, SH64_COMPACT_INSN_ANDI_COMPACT, SH64_COMPACT_SFMT_ANDI_COMPACT },
+ { SH_INSN_ANDB_COMPACT, SH64_COMPACT_INSN_ANDB_COMPACT, SH64_COMPACT_SFMT_ANDB_COMPACT },
+ { SH_INSN_BF_COMPACT, SH64_COMPACT_INSN_BF_COMPACT, SH64_COMPACT_SFMT_BF_COMPACT },
+ { SH_INSN_BFS_COMPACT, SH64_COMPACT_INSN_BFS_COMPACT, SH64_COMPACT_SFMT_BF_COMPACT },
+ { SH_INSN_BRA_COMPACT, SH64_COMPACT_INSN_BRA_COMPACT, SH64_COMPACT_SFMT_BRA_COMPACT },
+ { SH_INSN_BRAF_COMPACT, SH64_COMPACT_INSN_BRAF_COMPACT, SH64_COMPACT_SFMT_BRAF_COMPACT },
+ { SH_INSN_BRK_COMPACT, SH64_COMPACT_INSN_BRK_COMPACT, SH64_COMPACT_SFMT_BRK_COMPACT },
+ { SH_INSN_BSR_COMPACT, SH64_COMPACT_INSN_BSR_COMPACT, SH64_COMPACT_SFMT_BSR_COMPACT },
+ { SH_INSN_BSRF_COMPACT, SH64_COMPACT_INSN_BSRF_COMPACT, SH64_COMPACT_SFMT_BSRF_COMPACT },
+ { SH_INSN_BT_COMPACT, SH64_COMPACT_INSN_BT_COMPACT, SH64_COMPACT_SFMT_BF_COMPACT },
+ { SH_INSN_BTS_COMPACT, SH64_COMPACT_INSN_BTS_COMPACT, SH64_COMPACT_SFMT_BF_COMPACT },
+ { SH_INSN_CLRMAC_COMPACT, SH64_COMPACT_INSN_CLRMAC_COMPACT, SH64_COMPACT_SFMT_CLRMAC_COMPACT },
+ { SH_INSN_CLRS_COMPACT, SH64_COMPACT_INSN_CLRS_COMPACT, SH64_COMPACT_SFMT_CLRS_COMPACT },
+ { SH_INSN_CLRT_COMPACT, SH64_COMPACT_INSN_CLRT_COMPACT, SH64_COMPACT_SFMT_CLRT_COMPACT },
+ { SH_INSN_CMPEQ_COMPACT, SH64_COMPACT_INSN_CMPEQ_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT },
+ { SH_INSN_CMPEQI_COMPACT, SH64_COMPACT_INSN_CMPEQI_COMPACT, SH64_COMPACT_SFMT_CMPEQI_COMPACT },
+ { SH_INSN_CMPGE_COMPACT, SH64_COMPACT_INSN_CMPGE_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT },
+ { SH_INSN_CMPGT_COMPACT, SH64_COMPACT_INSN_CMPGT_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT },
+ { SH_INSN_CMPHI_COMPACT, SH64_COMPACT_INSN_CMPHI_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT },
+ { SH_INSN_CMPHS_COMPACT, SH64_COMPACT_INSN_CMPHS_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT },
+ { SH_INSN_CMPPL_COMPACT, SH64_COMPACT_INSN_CMPPL_COMPACT, SH64_COMPACT_SFMT_CMPPL_COMPACT },
+ { SH_INSN_CMPPZ_COMPACT, SH64_COMPACT_INSN_CMPPZ_COMPACT, SH64_COMPACT_SFMT_CMPPL_COMPACT },
+ { SH_INSN_CMPSTR_COMPACT, SH64_COMPACT_INSN_CMPSTR_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT },
+ { SH_INSN_DIV0S_COMPACT, SH64_COMPACT_INSN_DIV0S_COMPACT, SH64_COMPACT_SFMT_DIV0S_COMPACT },
+ { SH_INSN_DIV0U_COMPACT, SH64_COMPACT_INSN_DIV0U_COMPACT, SH64_COMPACT_SFMT_DIV0U_COMPACT },
+ { SH_INSN_DIV1_COMPACT, SH64_COMPACT_INSN_DIV1_COMPACT, SH64_COMPACT_SFMT_DIV1_COMPACT },
+ { SH_INSN_DMULSL_COMPACT, SH64_COMPACT_INSN_DMULSL_COMPACT, SH64_COMPACT_SFMT_DMULSL_COMPACT },
+ { SH_INSN_DMULUL_COMPACT, SH64_COMPACT_INSN_DMULUL_COMPACT, SH64_COMPACT_SFMT_DMULSL_COMPACT },
+ { SH_INSN_DT_COMPACT, SH64_COMPACT_INSN_DT_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT },
+ { SH_INSN_EXTSB_COMPACT, SH64_COMPACT_INSN_EXTSB_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT },
+ { SH_INSN_EXTSW_COMPACT, SH64_COMPACT_INSN_EXTSW_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT },
+ { SH_INSN_EXTUB_COMPACT, SH64_COMPACT_INSN_EXTUB_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT },
+ { SH_INSN_EXTUW_COMPACT, SH64_COMPACT_INSN_EXTUW_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT },
+ { SH_INSN_FABS_COMPACT, SH64_COMPACT_INSN_FABS_COMPACT, SH64_COMPACT_SFMT_FABS_COMPACT },
+ { SH_INSN_FADD_COMPACT, SH64_COMPACT_INSN_FADD_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT },
+ { SH_INSN_FCMPEQ_COMPACT, SH64_COMPACT_INSN_FCMPEQ_COMPACT, SH64_COMPACT_SFMT_FCMPEQ_COMPACT },
+ { SH_INSN_FCMPGT_COMPACT, SH64_COMPACT_INSN_FCMPGT_COMPACT, SH64_COMPACT_SFMT_FCMPEQ_COMPACT },
+ { SH_INSN_FCNVDS_COMPACT, SH64_COMPACT_INSN_FCNVDS_COMPACT, SH64_COMPACT_SFMT_FCNVDS_COMPACT },
+ { SH_INSN_FCNVSD_COMPACT, SH64_COMPACT_INSN_FCNVSD_COMPACT, SH64_COMPACT_SFMT_FCNVSD_COMPACT },
+ { SH_INSN_FDIV_COMPACT, SH64_COMPACT_INSN_FDIV_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT },
+ { SH_INSN_FIPR_COMPACT, SH64_COMPACT_INSN_FIPR_COMPACT, SH64_COMPACT_SFMT_FIPR_COMPACT },
+ { SH_INSN_FLDS_COMPACT, SH64_COMPACT_INSN_FLDS_COMPACT, SH64_COMPACT_SFMT_FLDS_COMPACT },
+ { SH_INSN_FLDI0_COMPACT, SH64_COMPACT_INSN_FLDI0_COMPACT, SH64_COMPACT_SFMT_FLDI0_COMPACT },
+ { SH_INSN_FLDI1_COMPACT, SH64_COMPACT_INSN_FLDI1_COMPACT, SH64_COMPACT_SFMT_FLDI0_COMPACT },
+ { SH_INSN_FLOAT_COMPACT, SH64_COMPACT_INSN_FLOAT_COMPACT, SH64_COMPACT_SFMT_FLOAT_COMPACT },
+ { SH_INSN_FMAC_COMPACT, SH64_COMPACT_INSN_FMAC_COMPACT, SH64_COMPACT_SFMT_FMAC_COMPACT },
+ { SH_INSN_FMOV1_COMPACT, SH64_COMPACT_INSN_FMOV1_COMPACT, SH64_COMPACT_SFMT_FMOV1_COMPACT },
+ { SH_INSN_FMOV2_COMPACT, SH64_COMPACT_INSN_FMOV2_COMPACT, SH64_COMPACT_SFMT_FMOV2_COMPACT },
+ { SH_INSN_FMOV3_COMPACT, SH64_COMPACT_INSN_FMOV3_COMPACT, SH64_COMPACT_SFMT_FMOV3_COMPACT },
+ { SH_INSN_FMOV4_COMPACT, SH64_COMPACT_INSN_FMOV4_COMPACT, SH64_COMPACT_SFMT_FMOV4_COMPACT },
+ { SH_INSN_FMOV5_COMPACT, SH64_COMPACT_INSN_FMOV5_COMPACT, SH64_COMPACT_SFMT_FMOV5_COMPACT },
+ { SH_INSN_FMOV6_COMPACT, SH64_COMPACT_INSN_FMOV6_COMPACT, SH64_COMPACT_SFMT_FMOV6_COMPACT },
+ { SH_INSN_FMOV7_COMPACT, SH64_COMPACT_INSN_FMOV7_COMPACT, SH64_COMPACT_SFMT_FMOV7_COMPACT },
+ { SH_INSN_FMUL_COMPACT, SH64_COMPACT_INSN_FMUL_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT },
+ { SH_INSN_FNEG_COMPACT, SH64_COMPACT_INSN_FNEG_COMPACT, SH64_COMPACT_SFMT_FABS_COMPACT },
+ { SH_INSN_FRCHG_COMPACT, SH64_COMPACT_INSN_FRCHG_COMPACT, SH64_COMPACT_SFMT_FRCHG_COMPACT },
+ { SH_INSN_FSCHG_COMPACT, SH64_COMPACT_INSN_FSCHG_COMPACT, SH64_COMPACT_SFMT_FSCHG_COMPACT },
+ { SH_INSN_FSQRT_COMPACT, SH64_COMPACT_INSN_FSQRT_COMPACT, SH64_COMPACT_SFMT_FABS_COMPACT },
+ { SH_INSN_FSTS_COMPACT, SH64_COMPACT_INSN_FSTS_COMPACT, SH64_COMPACT_SFMT_FSTS_COMPACT },
+ { SH_INSN_FSUB_COMPACT, SH64_COMPACT_INSN_FSUB_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT },
+ { SH_INSN_FTRC_COMPACT, SH64_COMPACT_INSN_FTRC_COMPACT, SH64_COMPACT_SFMT_FTRC_COMPACT },
+ { SH_INSN_FTRV_COMPACT, SH64_COMPACT_INSN_FTRV_COMPACT, SH64_COMPACT_SFMT_FTRV_COMPACT },
+ { SH_INSN_JMP_COMPACT, SH64_COMPACT_INSN_JMP_COMPACT, SH64_COMPACT_SFMT_JMP_COMPACT },
+ { SH_INSN_JSR_COMPACT, SH64_COMPACT_INSN_JSR_COMPACT, SH64_COMPACT_SFMT_BSRF_COMPACT },
+ { SH_INSN_LDC_COMPACT, SH64_COMPACT_INSN_LDC_COMPACT, SH64_COMPACT_SFMT_LDC_COMPACT },
+ { SH_INSN_LDCL_COMPACT, SH64_COMPACT_INSN_LDCL_COMPACT, SH64_COMPACT_SFMT_LDCL_COMPACT },
+ { SH_INSN_LDS_FPSCR_COMPACT, SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, SH64_COMPACT_SFMT_LDS_FPSCR_COMPACT },
+ { SH_INSN_LDSL_FPSCR_COMPACT, SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, SH64_COMPACT_SFMT_LDSL_FPSCR_COMPACT },
+ { SH_INSN_LDS_FPUL_COMPACT, SH64_COMPACT_INSN_LDS_FPUL_COMPACT, SH64_COMPACT_SFMT_LDS_FPUL_COMPACT },
+ { SH_INSN_LDSL_FPUL_COMPACT, SH64_COMPACT_INSN_LDSL_FPUL_COMPACT, SH64_COMPACT_SFMT_LDSL_FPUL_COMPACT },
+ { SH_INSN_LDS_MACH_COMPACT, SH64_COMPACT_INSN_LDS_MACH_COMPACT, SH64_COMPACT_SFMT_LDS_MACH_COMPACT },
+ { SH_INSN_LDSL_MACH_COMPACT, SH64_COMPACT_INSN_LDSL_MACH_COMPACT, SH64_COMPACT_SFMT_LDSL_MACH_COMPACT },
+ { SH_INSN_LDS_MACL_COMPACT, SH64_COMPACT_INSN_LDS_MACL_COMPACT, SH64_COMPACT_SFMT_LDS_MACL_COMPACT },
+ { SH_INSN_LDSL_MACL_COMPACT, SH64_COMPACT_INSN_LDSL_MACL_COMPACT, SH64_COMPACT_SFMT_LDSL_MACL_COMPACT },
+ { SH_INSN_LDS_PR_COMPACT, SH64_COMPACT_INSN_LDS_PR_COMPACT, SH64_COMPACT_SFMT_LDS_PR_COMPACT },
+ { SH_INSN_LDSL_PR_COMPACT, SH64_COMPACT_INSN_LDSL_PR_COMPACT, SH64_COMPACT_SFMT_LDSL_PR_COMPACT },
+ { SH_INSN_MACL_COMPACT, SH64_COMPACT_INSN_MACL_COMPACT, SH64_COMPACT_SFMT_MACL_COMPACT },
+ { SH_INSN_MACW_COMPACT, SH64_COMPACT_INSN_MACW_COMPACT, SH64_COMPACT_SFMT_MACW_COMPACT },
+ { SH_INSN_MOV_COMPACT, SH64_COMPACT_INSN_MOV_COMPACT, SH64_COMPACT_SFMT_MOV_COMPACT },
+ { SH_INSN_MOVI_COMPACT, SH64_COMPACT_INSN_MOVI_COMPACT, SH64_COMPACT_SFMT_MOVI_COMPACT },
+ { SH_INSN_MOVB1_COMPACT, SH64_COMPACT_INSN_MOVB1_COMPACT, SH64_COMPACT_SFMT_MOVB1_COMPACT },
+ { SH_INSN_MOVB2_COMPACT, SH64_COMPACT_INSN_MOVB2_COMPACT, SH64_COMPACT_SFMT_MOVB2_COMPACT },
+ { SH_INSN_MOVB3_COMPACT, SH64_COMPACT_INSN_MOVB3_COMPACT, SH64_COMPACT_SFMT_MOVB3_COMPACT },
+ { SH_INSN_MOVB4_COMPACT, SH64_COMPACT_INSN_MOVB4_COMPACT, SH64_COMPACT_SFMT_MOVB4_COMPACT },
+ { SH_INSN_MOVB5_COMPACT, SH64_COMPACT_INSN_MOVB5_COMPACT, SH64_COMPACT_SFMT_MOVB5_COMPACT },
+ { SH_INSN_MOVB6_COMPACT, SH64_COMPACT_INSN_MOVB6_COMPACT, SH64_COMPACT_SFMT_MOVB6_COMPACT },
+ { SH_INSN_MOVB7_COMPACT, SH64_COMPACT_INSN_MOVB7_COMPACT, SH64_COMPACT_SFMT_MOVB7_COMPACT },
+ { SH_INSN_MOVB8_COMPACT, SH64_COMPACT_INSN_MOVB8_COMPACT, SH64_COMPACT_SFMT_MOVB8_COMPACT },
+ { SH_INSN_MOVB9_COMPACT, SH64_COMPACT_INSN_MOVB9_COMPACT, SH64_COMPACT_SFMT_MOVB9_COMPACT },
+ { SH_INSN_MOVB10_COMPACT, SH64_COMPACT_INSN_MOVB10_COMPACT, SH64_COMPACT_SFMT_MOVB10_COMPACT },
+ { SH_INSN_MOVL1_COMPACT, SH64_COMPACT_INSN_MOVL1_COMPACT, SH64_COMPACT_SFMT_MOVB1_COMPACT },
+ { SH_INSN_MOVL2_COMPACT, SH64_COMPACT_INSN_MOVL2_COMPACT, SH64_COMPACT_SFMT_MOVB2_COMPACT },
+ { SH_INSN_MOVL3_COMPACT, SH64_COMPACT_INSN_MOVL3_COMPACT, SH64_COMPACT_SFMT_MOVB3_COMPACT },
+ { SH_INSN_MOVL4_COMPACT, SH64_COMPACT_INSN_MOVL4_COMPACT, SH64_COMPACT_SFMT_MOVL4_COMPACT },
+ { SH_INSN_MOVL5_COMPACT, SH64_COMPACT_INSN_MOVL5_COMPACT, SH64_COMPACT_SFMT_MOVL5_COMPACT },
+ { SH_INSN_MOVL6_COMPACT, SH64_COMPACT_INSN_MOVL6_COMPACT, SH64_COMPACT_SFMT_MOVB6_COMPACT },
+ { SH_INSN_MOVL7_COMPACT, SH64_COMPACT_INSN_MOVL7_COMPACT, SH64_COMPACT_SFMT_MOVL7_COMPACT },
+ { SH_INSN_MOVL8_COMPACT, SH64_COMPACT_INSN_MOVL8_COMPACT, SH64_COMPACT_SFMT_MOVB8_COMPACT },
+ { SH_INSN_MOVL9_COMPACT, SH64_COMPACT_INSN_MOVL9_COMPACT, SH64_COMPACT_SFMT_MOVL9_COMPACT },
+ { SH_INSN_MOVL10_COMPACT, SH64_COMPACT_INSN_MOVL10_COMPACT, SH64_COMPACT_SFMT_MOVL10_COMPACT },
+ { SH_INSN_MOVL11_COMPACT, SH64_COMPACT_INSN_MOVL11_COMPACT, SH64_COMPACT_SFMT_MOVL11_COMPACT },
+ { SH_INSN_MOVW1_COMPACT, SH64_COMPACT_INSN_MOVW1_COMPACT, SH64_COMPACT_SFMT_MOVB1_COMPACT },
+ { SH_INSN_MOVW2_COMPACT, SH64_COMPACT_INSN_MOVW2_COMPACT, SH64_COMPACT_SFMT_MOVB2_COMPACT },
+ { SH_INSN_MOVW3_COMPACT, SH64_COMPACT_INSN_MOVW3_COMPACT, SH64_COMPACT_SFMT_MOVB3_COMPACT },
+ { SH_INSN_MOVW4_COMPACT, SH64_COMPACT_INSN_MOVW4_COMPACT, SH64_COMPACT_SFMT_MOVW4_COMPACT },
+ { SH_INSN_MOVW5_COMPACT, SH64_COMPACT_INSN_MOVW5_COMPACT, SH64_COMPACT_SFMT_MOVW5_COMPACT },
+ { SH_INSN_MOVW6_COMPACT, SH64_COMPACT_INSN_MOVW6_COMPACT, SH64_COMPACT_SFMT_MOVB6_COMPACT },
+ { SH_INSN_MOVW7_COMPACT, SH64_COMPACT_INSN_MOVW7_COMPACT, SH64_COMPACT_SFMT_MOVB7_COMPACT },
+ { SH_INSN_MOVW8_COMPACT, SH64_COMPACT_INSN_MOVW8_COMPACT, SH64_COMPACT_SFMT_MOVB8_COMPACT },
+ { SH_INSN_MOVW9_COMPACT, SH64_COMPACT_INSN_MOVW9_COMPACT, SH64_COMPACT_SFMT_MOVW9_COMPACT },
+ { SH_INSN_MOVW10_COMPACT, SH64_COMPACT_INSN_MOVW10_COMPACT, SH64_COMPACT_SFMT_MOVW10_COMPACT },
+ { SH_INSN_MOVW11_COMPACT, SH64_COMPACT_INSN_MOVW11_COMPACT, SH64_COMPACT_SFMT_MOVW11_COMPACT },
+ { SH_INSN_MOVA_COMPACT, SH64_COMPACT_INSN_MOVA_COMPACT, SH64_COMPACT_SFMT_MOVA_COMPACT },
+ { SH_INSN_MOVCAL_COMPACT, SH64_COMPACT_INSN_MOVCAL_COMPACT, SH64_COMPACT_SFMT_MOVCAL_COMPACT },
+ { SH_INSN_MOVT_COMPACT, SH64_COMPACT_INSN_MOVT_COMPACT, SH64_COMPACT_SFMT_MOVT_COMPACT },
+ { SH_INSN_MULL_COMPACT, SH64_COMPACT_INSN_MULL_COMPACT, SH64_COMPACT_SFMT_MULL_COMPACT },
+ { SH_INSN_MULSW_COMPACT, SH64_COMPACT_INSN_MULSW_COMPACT, SH64_COMPACT_SFMT_MULL_COMPACT },
+ { SH_INSN_MULUW_COMPACT, SH64_COMPACT_INSN_MULUW_COMPACT, SH64_COMPACT_SFMT_MULL_COMPACT },
+ { SH_INSN_NEG_COMPACT, SH64_COMPACT_INSN_NEG_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT },
+ { SH_INSN_NEGC_COMPACT, SH64_COMPACT_INSN_NEGC_COMPACT, SH64_COMPACT_SFMT_NEGC_COMPACT },
+ { SH_INSN_NOP_COMPACT, SH64_COMPACT_INSN_NOP_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT },
+ { SH_INSN_NOT_COMPACT, SH64_COMPACT_INSN_NOT_COMPACT, SH64_COMPACT_SFMT_MOV_COMPACT },
+ { SH_INSN_OCBI_COMPACT, SH64_COMPACT_INSN_OCBI_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT },
+ { SH_INSN_OCBP_COMPACT, SH64_COMPACT_INSN_OCBP_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT },
+ { SH_INSN_OCBWB_COMPACT, SH64_COMPACT_INSN_OCBWB_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT },
+ { SH_INSN_OR_COMPACT, SH64_COMPACT_INSN_OR_COMPACT, SH64_COMPACT_SFMT_AND_COMPACT },
+ { SH_INSN_ORI_COMPACT, SH64_COMPACT_INSN_ORI_COMPACT, SH64_COMPACT_SFMT_ANDI_COMPACT },
+ { SH_INSN_ORB_COMPACT, SH64_COMPACT_INSN_ORB_COMPACT, SH64_COMPACT_SFMT_ANDB_COMPACT },
+ { SH_INSN_PREF_COMPACT, SH64_COMPACT_INSN_PREF_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT },
+ { SH_INSN_ROTCL_COMPACT, SH64_COMPACT_INSN_ROTCL_COMPACT, SH64_COMPACT_SFMT_ROTCL_COMPACT },
+ { SH_INSN_ROTCR_COMPACT, SH64_COMPACT_INSN_ROTCR_COMPACT, SH64_COMPACT_SFMT_ROTCL_COMPACT },
+ { SH_INSN_ROTL_COMPACT, SH64_COMPACT_INSN_ROTL_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT },
+ { SH_INSN_ROTR_COMPACT, SH64_COMPACT_INSN_ROTR_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT },
+ { SH_INSN_RTS_COMPACT, SH64_COMPACT_INSN_RTS_COMPACT, SH64_COMPACT_SFMT_RTS_COMPACT },
+ { SH_INSN_SETS_COMPACT, SH64_COMPACT_INSN_SETS_COMPACT, SH64_COMPACT_SFMT_CLRS_COMPACT },
+ { SH_INSN_SETT_COMPACT, SH64_COMPACT_INSN_SETT_COMPACT, SH64_COMPACT_SFMT_CLRT_COMPACT },
+ { SH_INSN_SHAD_COMPACT, SH64_COMPACT_INSN_SHAD_COMPACT, SH64_COMPACT_SFMT_SHAD_COMPACT },
+ { SH_INSN_SHAL_COMPACT, SH64_COMPACT_INSN_SHAL_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT },
+ { SH_INSN_SHAR_COMPACT, SH64_COMPACT_INSN_SHAR_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT },
+ { SH_INSN_SHLD_COMPACT, SH64_COMPACT_INSN_SHLD_COMPACT, SH64_COMPACT_SFMT_SHAD_COMPACT },
+ { SH_INSN_SHLL_COMPACT, SH64_COMPACT_INSN_SHLL_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT },
+ { SH_INSN_SHLL2_COMPACT, SH64_COMPACT_INSN_SHLL2_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT },
+ { SH_INSN_SHLL8_COMPACT, SH64_COMPACT_INSN_SHLL8_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT },
+ { SH_INSN_SHLL16_COMPACT, SH64_COMPACT_INSN_SHLL16_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT },
+ { SH_INSN_SHLR_COMPACT, SH64_COMPACT_INSN_SHLR_COMPACT, SH64_COMPACT_SFMT_DT_COMPACT },
+ { SH_INSN_SHLR2_COMPACT, SH64_COMPACT_INSN_SHLR2_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT },
+ { SH_INSN_SHLR8_COMPACT, SH64_COMPACT_INSN_SHLR8_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT },
+ { SH_INSN_SHLR16_COMPACT, SH64_COMPACT_INSN_SHLR16_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT },
+ { SH_INSN_STC_GBR_COMPACT, SH64_COMPACT_INSN_STC_GBR_COMPACT, SH64_COMPACT_SFMT_STC_GBR_COMPACT },
+ { SH_INSN_STCL_GBR_COMPACT, SH64_COMPACT_INSN_STCL_GBR_COMPACT, SH64_COMPACT_SFMT_STCL_GBR_COMPACT },
+ { SH_INSN_STS_FPSCR_COMPACT, SH64_COMPACT_INSN_STS_FPSCR_COMPACT, SH64_COMPACT_SFMT_STS_FPSCR_COMPACT },
+ { SH_INSN_STSL_FPSCR_COMPACT, SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, SH64_COMPACT_SFMT_STSL_FPSCR_COMPACT },
+ { SH_INSN_STS_FPUL_COMPACT, SH64_COMPACT_INSN_STS_FPUL_COMPACT, SH64_COMPACT_SFMT_STS_FPUL_COMPACT },
+ { SH_INSN_STSL_FPUL_COMPACT, SH64_COMPACT_INSN_STSL_FPUL_COMPACT, SH64_COMPACT_SFMT_STSL_FPUL_COMPACT },
+ { SH_INSN_STS_MACH_COMPACT, SH64_COMPACT_INSN_STS_MACH_COMPACT, SH64_COMPACT_SFMT_STS_MACH_COMPACT },
+ { SH_INSN_STSL_MACH_COMPACT, SH64_COMPACT_INSN_STSL_MACH_COMPACT, SH64_COMPACT_SFMT_STSL_MACH_COMPACT },
+ { SH_INSN_STS_MACL_COMPACT, SH64_COMPACT_INSN_STS_MACL_COMPACT, SH64_COMPACT_SFMT_STS_MACL_COMPACT },
+ { SH_INSN_STSL_MACL_COMPACT, SH64_COMPACT_INSN_STSL_MACL_COMPACT, SH64_COMPACT_SFMT_STSL_MACL_COMPACT },
+ { SH_INSN_STS_PR_COMPACT, SH64_COMPACT_INSN_STS_PR_COMPACT, SH64_COMPACT_SFMT_STS_PR_COMPACT },
+ { SH_INSN_STSL_PR_COMPACT, SH64_COMPACT_INSN_STSL_PR_COMPACT, SH64_COMPACT_SFMT_STSL_PR_COMPACT },
+ { SH_INSN_SUB_COMPACT, SH64_COMPACT_INSN_SUB_COMPACT, SH64_COMPACT_SFMT_ADD_COMPACT },
+ { SH_INSN_SUBC_COMPACT, SH64_COMPACT_INSN_SUBC_COMPACT, SH64_COMPACT_SFMT_ADDC_COMPACT },
+ { SH_INSN_SUBV_COMPACT, SH64_COMPACT_INSN_SUBV_COMPACT, SH64_COMPACT_SFMT_ADDV_COMPACT },
+ { SH_INSN_SWAPB_COMPACT, SH64_COMPACT_INSN_SWAPB_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT },
+ { SH_INSN_SWAPW_COMPACT, SH64_COMPACT_INSN_SWAPW_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT },
+ { SH_INSN_TASB_COMPACT, SH64_COMPACT_INSN_TASB_COMPACT, SH64_COMPACT_SFMT_TASB_COMPACT },
+ { SH_INSN_TRAPA_COMPACT, SH64_COMPACT_INSN_TRAPA_COMPACT, SH64_COMPACT_SFMT_TRAPA_COMPACT },
+ { SH_INSN_TST_COMPACT, SH64_COMPACT_INSN_TST_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT },
+ { SH_INSN_TSTI_COMPACT, SH64_COMPACT_INSN_TSTI_COMPACT, SH64_COMPACT_SFMT_TSTI_COMPACT },
+ { SH_INSN_TSTB_COMPACT, SH64_COMPACT_INSN_TSTB_COMPACT, SH64_COMPACT_SFMT_TSTB_COMPACT },
+ { SH_INSN_XOR_COMPACT, SH64_COMPACT_INSN_XOR_COMPACT, SH64_COMPACT_SFMT_AND_COMPACT },
+ { SH_INSN_XORI_COMPACT, SH64_COMPACT_INSN_XORI_COMPACT, SH64_COMPACT_SFMT_XORI_COMPACT },
+ { SH_INSN_XORB_COMPACT, SH64_COMPACT_INSN_XORB_COMPACT, SH64_COMPACT_SFMT_ANDB_COMPACT },
+ { SH_INSN_XTRCT_COMPACT, SH64_COMPACT_INSN_XTRCT_COMPACT, SH64_COMPACT_SFMT_ADD_COMPACT },
+};
+
+static const struct insn_sem sh64_compact_insn_sem_invalid = {
+ VIRTUAL_INSN_X_INVALID, SH64_COMPACT_INSN_X_INVALID, SH64_COMPACT_SFMT_EMPTY
+};
+
+/* Initialize an IDESC from the compile-time computable parts. */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+ const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
+
+ id->num = t->index;
+ id->sfmt = t->sfmt;
+ if ((int) t->type <= 0)
+ id->idata = & cgen_virtual_insn_table[- (int) t->type];
+ else
+ id->idata = & insn_table[t->type];
+ id->attrs = CGEN_INSN_ATTRS (id->idata);
+ /* Oh my god, a magic number. */
+ id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
+
+#if WITH_PROFILE_MODEL_P
+ id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+ {
+ SIM_DESC sd = CPU_STATE (cpu);
+ SIM_ASSERT (t->index == id->timing->num);
+ }
+#endif
+
+ /* Semantic pointers are initialized elsewhere. */
+}
+
+/* Initialize the instruction descriptor table. */
+
+void
+sh64_compact_init_idesc_table (SIM_CPU *cpu)
+{
+ IDESC *id,*tabend;
+ const struct insn_sem *t,*tend;
+ int tabsize = SH64_COMPACT_INSN_MAX;
+ IDESC *table = sh64_compact_insn_data;
+
+ memset (table, 0, tabsize * sizeof (IDESC));
+
+ /* First set all entries to the `invalid insn'. */
+ t = & sh64_compact_insn_sem_invalid;
+ for (id = table, tabend = table + tabsize; id < tabend; ++id)
+ init_idesc (cpu, id, t);
+
+ /* Now fill in the values for the chosen cpu. */
+ for (t = sh64_compact_insn_sem, tend = t + sizeof (sh64_compact_insn_sem) / sizeof (*t);
+ t != tend; ++t)
+ {
+ init_idesc (cpu, & table[t->index], t);
+ }
+
+ /* Link the IDESC table into the cpu. */
+ CPU_IDESC (cpu) = table;
+}
+
+/* Given an instruction, return a pointer to its IDESC entry. */
+
+const IDESC *
+sh64_compact_decode (SIM_CPU *current_cpu, IADDR pc,
+ CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
+ ARGBUF *abuf)
+{
+ /* Result of decoder. */
+ SH64_COMPACT_INSN_TYPE itype;
+
+ {
+ CGEN_INSN_INT insn = base_insn;
+
+ {
+ unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 0) & (15 << 0)));
+ switch (val)
+ {
+ case 2 : itype = SH64_COMPACT_INSN_STC_GBR_COMPACT; goto extract_sfmt_stc_gbr_compact; case 3 :
+ {
+ unsigned int val = (((insn >> 4) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_BSRF_COMPACT; goto extract_sfmt_bsrf_compact; case 2 : itype = SH64_COMPACT_INSN_BRAF_COMPACT; goto extract_sfmt_braf_compact; case 8 : itype = SH64_COMPACT_INSN_PREF_COMPACT; goto extract_sfmt_nop_compact; case 9 : itype = SH64_COMPACT_INSN_OCBI_COMPACT; goto extract_sfmt_nop_compact; case 10 : itype = SH64_COMPACT_INSN_OCBP_COMPACT; goto extract_sfmt_nop_compact; case 11 : itype = SH64_COMPACT_INSN_OCBWB_COMPACT; goto extract_sfmt_nop_compact; case 12 : itype = SH64_COMPACT_INSN_MOVCAL_COMPACT; goto extract_sfmt_movcal_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 4 : itype = SH64_COMPACT_INSN_MOVB3_COMPACT; goto extract_sfmt_movb3_compact; case 5 : itype = SH64_COMPACT_INSN_MOVW3_COMPACT; goto extract_sfmt_movb3_compact; case 6 : itype = SH64_COMPACT_INSN_MOVL3_COMPACT; goto extract_sfmt_movb3_compact; case 7 : itype = SH64_COMPACT_INSN_MULL_COMPACT; goto extract_sfmt_mull_compact; case 8 :
+ {
+ unsigned int val = (((insn >> 4) & (7 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_CLRT_COMPACT; goto extract_sfmt_clrt_compact; case 1 : itype = SH64_COMPACT_INSN_SETT_COMPACT; goto extract_sfmt_clrt_compact; case 2 : itype = SH64_COMPACT_INSN_CLRMAC_COMPACT; goto extract_sfmt_clrmac_compact; case 4 : itype = SH64_COMPACT_INSN_CLRS_COMPACT; goto extract_sfmt_clrs_compact; case 5 : itype = SH64_COMPACT_INSN_SETS_COMPACT; goto extract_sfmt_clrs_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 9 :
+ {
+ unsigned int val = (((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_NOP_COMPACT; goto extract_sfmt_nop_compact; case 1 : itype = SH64_COMPACT_INSN_DIV0U_COMPACT; goto extract_sfmt_div0u_compact; case 2 : itype = SH64_COMPACT_INSN_MOVT_COMPACT; goto extract_sfmt_movt_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 10 :
+ {
+ unsigned int val = (((insn >> 4) & (7 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_STS_MACH_COMPACT; goto extract_sfmt_sts_mach_compact; case 1 : itype = SH64_COMPACT_INSN_STS_MACL_COMPACT; goto extract_sfmt_sts_macl_compact; case 2 : itype = SH64_COMPACT_INSN_STS_PR_COMPACT; goto extract_sfmt_sts_pr_compact; case 5 : itype = SH64_COMPACT_INSN_STS_FPUL_COMPACT; goto extract_sfmt_sts_fpul_compact; case 6 : itype = SH64_COMPACT_INSN_STS_FPSCR_COMPACT; goto extract_sfmt_sts_fpscr_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 11 :
+ {
+ unsigned int val = (((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_RTS_COMPACT; goto extract_sfmt_rts_compact; case 3 : itype = SH64_COMPACT_INSN_BRK_COMPACT; goto extract_sfmt_brk_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 12 : itype = SH64_COMPACT_INSN_MOVB8_COMPACT; goto extract_sfmt_movb8_compact; case 13 : itype = SH64_COMPACT_INSN_MOVW8_COMPACT; goto extract_sfmt_movb8_compact; case 14 : itype = SH64_COMPACT_INSN_MOVL8_COMPACT; goto extract_sfmt_movb8_compact; case 15 : itype = SH64_COMPACT_INSN_MACL_COMPACT; goto extract_sfmt_macl_compact; case 16 : /* fall through */
+ case 17 : /* fall through */
+ case 18 : /* fall through */
+ case 19 : /* fall through */
+ case 20 : /* fall through */
+ case 21 : /* fall through */
+ case 22 : /* fall through */
+ case 23 : /* fall through */
+ case 24 : /* fall through */
+ case 25 : /* fall through */
+ case 26 : /* fall through */
+ case 27 : /* fall through */
+ case 28 : /* fall through */
+ case 29 : /* fall through */
+ case 30 : /* fall through */
+ case 31 : itype = SH64_COMPACT_INSN_MOVL5_COMPACT; goto extract_sfmt_movl5_compact; case 32 : itype = SH64_COMPACT_INSN_MOVB1_COMPACT; goto extract_sfmt_movb1_compact; case 33 : itype = SH64_COMPACT_INSN_MOVW1_COMPACT; goto extract_sfmt_movb1_compact; case 34 : itype = SH64_COMPACT_INSN_MOVL1_COMPACT; goto extract_sfmt_movb1_compact; case 36 : itype = SH64_COMPACT_INSN_MOVB2_COMPACT; goto extract_sfmt_movb2_compact; case 37 : itype = SH64_COMPACT_INSN_MOVW2_COMPACT; goto extract_sfmt_movb2_compact; case 38 : itype = SH64_COMPACT_INSN_MOVL2_COMPACT; goto extract_sfmt_movb2_compact; case 39 : itype = SH64_COMPACT_INSN_DIV0S_COMPACT; goto extract_sfmt_div0s_compact; case 40 : itype = SH64_COMPACT_INSN_TST_COMPACT; goto extract_sfmt_cmpeq_compact; case 41 : itype = SH64_COMPACT_INSN_AND_COMPACT; goto extract_sfmt_and_compact; case 42 : itype = SH64_COMPACT_INSN_XOR_COMPACT; goto extract_sfmt_and_compact; case 43 : itype = SH64_COMPACT_INSN_OR_COMPACT; goto extract_sfmt_and_compact; case 44 : itype = SH64_COMPACT_INSN_CMPSTR_COMPACT; goto extract_sfmt_cmpeq_compact; case 45 : itype = SH64_COMPACT_INSN_XTRCT_COMPACT; goto extract_sfmt_add_compact; case 46 : itype = SH64_COMPACT_INSN_MULUW_COMPACT; goto extract_sfmt_mull_compact; case 47 : itype = SH64_COMPACT_INSN_MULSW_COMPACT; goto extract_sfmt_mull_compact; case 48 : itype = SH64_COMPACT_INSN_CMPEQ_COMPACT; goto extract_sfmt_cmpeq_compact; case 50 : itype = SH64_COMPACT_INSN_CMPHS_COMPACT; goto extract_sfmt_cmpeq_compact; case 51 : itype = SH64_COMPACT_INSN_CMPGE_COMPACT; goto extract_sfmt_cmpeq_compact; case 52 : itype = SH64_COMPACT_INSN_DIV1_COMPACT; goto extract_sfmt_div1_compact; case 53 : itype = SH64_COMPACT_INSN_DMULUL_COMPACT; goto extract_sfmt_dmulsl_compact; case 54 : itype = SH64_COMPACT_INSN_CMPHI_COMPACT; goto extract_sfmt_cmpeq_compact; case 55 : itype = SH64_COMPACT_INSN_CMPGT_COMPACT; goto extract_sfmt_cmpeq_compact; case 56 : itype = SH64_COMPACT_INSN_SUB_COMPACT; goto extract_sfmt_add_compact; case 58 : itype = SH64_COMPACT_INSN_SUBC_COMPACT; goto extract_sfmt_addc_compact; case 59 : itype = SH64_COMPACT_INSN_SUBV_COMPACT; goto extract_sfmt_addv_compact; case 60 : itype = SH64_COMPACT_INSN_ADD_COMPACT; goto extract_sfmt_add_compact; case 61 : itype = SH64_COMPACT_INSN_DMULSL_COMPACT; goto extract_sfmt_dmulsl_compact; case 62 : itype = SH64_COMPACT_INSN_ADDC_COMPACT; goto extract_sfmt_addc_compact; case 63 : itype = SH64_COMPACT_INSN_ADDV_COMPACT; goto extract_sfmt_addv_compact; case 64 :
+ {
+ unsigned int val = (((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_SHLL_COMPACT; goto extract_sfmt_dt_compact; case 1 : itype = SH64_COMPACT_INSN_DT_COMPACT; goto extract_sfmt_dt_compact; case 2 : itype = SH64_COMPACT_INSN_SHAL_COMPACT; goto extract_sfmt_dt_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 65 :
+ {
+ unsigned int val = (((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_SHLR_COMPACT; goto extract_sfmt_dt_compact; case 1 : itype = SH64_COMPACT_INSN_CMPPZ_COMPACT; goto extract_sfmt_cmppl_compact; case 2 : itype = SH64_COMPACT_INSN_SHAR_COMPACT; goto extract_sfmt_dt_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 66 :
+ {
+ unsigned int val = (((insn >> 4) & (7 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_STSL_MACH_COMPACT; goto extract_sfmt_stsl_mach_compact; case 1 : itype = SH64_COMPACT_INSN_STSL_MACL_COMPACT; goto extract_sfmt_stsl_macl_compact; case 2 : itype = SH64_COMPACT_INSN_STSL_PR_COMPACT; goto extract_sfmt_stsl_pr_compact; case 5 : itype = SH64_COMPACT_INSN_STSL_FPUL_COMPACT; goto extract_sfmt_stsl_fpul_compact; case 6 : itype = SH64_COMPACT_INSN_STSL_FPSCR_COMPACT; goto extract_sfmt_stsl_fpscr_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 67 : itype = SH64_COMPACT_INSN_STCL_GBR_COMPACT; goto extract_sfmt_stcl_gbr_compact; case 68 :
+ {
+ unsigned int val = (((insn >> 5) & (1 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_ROTL_COMPACT; goto extract_sfmt_dt_compact; case 1 : itype = SH64_COMPACT_INSN_ROTCL_COMPACT; goto extract_sfmt_rotcl_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 69 :
+ {
+ unsigned int val = (((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_ROTR_COMPACT; goto extract_sfmt_dt_compact; case 1 : itype = SH64_COMPACT_INSN_CMPPL_COMPACT; goto extract_sfmt_cmppl_compact; case 2 : itype = SH64_COMPACT_INSN_ROTCR_COMPACT; goto extract_sfmt_rotcl_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 70 :
+ {
+ unsigned int val = (((insn >> 4) & (7 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_LDSL_MACH_COMPACT; goto extract_sfmt_ldsl_mach_compact; case 1 : itype = SH64_COMPACT_INSN_LDSL_MACL_COMPACT; goto extract_sfmt_ldsl_macl_compact; case 2 : itype = SH64_COMPACT_INSN_LDSL_PR_COMPACT; goto extract_sfmt_ldsl_pr_compact; case 5 : itype = SH64_COMPACT_INSN_LDSL_FPUL_COMPACT; goto extract_sfmt_ldsl_fpul_compact; case 6 : itype = SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT; goto extract_sfmt_ldsl_fpscr_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 71 : itype = SH64_COMPACT_INSN_LDCL_COMPACT; goto extract_sfmt_ldcl_compact; case 72 :
+ {
+ unsigned int val = (((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_SHLL2_COMPACT; goto extract_sfmt_shll2_compact; case 1 : itype = SH64_COMPACT_INSN_SHLL8_COMPACT; goto extract_sfmt_shll2_compact; case 2 : itype = SH64_COMPACT_INSN_SHLL16_COMPACT; goto extract_sfmt_shll2_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 73 :
+ {
+ unsigned int val = (((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_SHLR2_COMPACT; goto extract_sfmt_shll2_compact; case 1 : itype = SH64_COMPACT_INSN_SHLR8_COMPACT; goto extract_sfmt_shll2_compact; case 2 : itype = SH64_COMPACT_INSN_SHLR16_COMPACT; goto extract_sfmt_shll2_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 74 :
+ {
+ unsigned int val = (((insn >> 4) & (7 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_LDS_MACH_COMPACT; goto extract_sfmt_lds_mach_compact; case 1 : itype = SH64_COMPACT_INSN_LDS_MACL_COMPACT; goto extract_sfmt_lds_macl_compact; case 2 : itype = SH64_COMPACT_INSN_LDS_PR_COMPACT; goto extract_sfmt_lds_pr_compact; case 5 : itype = SH64_COMPACT_INSN_LDS_FPUL_COMPACT; goto extract_sfmt_lds_fpul_compact; case 6 : itype = SH64_COMPACT_INSN_LDS_FPSCR_COMPACT; goto extract_sfmt_lds_fpscr_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 75 :
+ {
+ unsigned int val = (((insn >> 4) & (3 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_JSR_COMPACT; goto extract_sfmt_bsrf_compact; case 1 : itype = SH64_COMPACT_INSN_TASB_COMPACT; goto extract_sfmt_tasb_compact; case 2 : itype = SH64_COMPACT_INSN_JMP_COMPACT; goto extract_sfmt_jmp_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 76 : itype = SH64_COMPACT_INSN_SHAD_COMPACT; goto extract_sfmt_shad_compact; case 77 : itype = SH64_COMPACT_INSN_SHLD_COMPACT; goto extract_sfmt_shad_compact; case 78 : itype = SH64_COMPACT_INSN_LDC_COMPACT; goto extract_sfmt_ldc_compact; case 79 : itype = SH64_COMPACT_INSN_MACW_COMPACT; goto extract_sfmt_macw_compact; case 80 : /* fall through */
+ case 81 : /* fall through */
+ case 82 : /* fall through */
+ case 83 : /* fall through */
+ case 84 : /* fall through */
+ case 85 : /* fall through */
+ case 86 : /* fall through */
+ case 87 : /* fall through */
+ case 88 : /* fall through */
+ case 89 : /* fall through */
+ case 90 : /* fall through */
+ case 91 : /* fall through */
+ case 92 : /* fall through */
+ case 93 : /* fall through */
+ case 94 : /* fall through */
+ case 95 : itype = SH64_COMPACT_INSN_MOVL11_COMPACT; goto extract_sfmt_movl11_compact; case 96 : itype = SH64_COMPACT_INSN_MOVB6_COMPACT; goto extract_sfmt_movb6_compact; case 97 : itype = SH64_COMPACT_INSN_MOVW6_COMPACT; goto extract_sfmt_movb6_compact; case 98 : itype = SH64_COMPACT_INSN_MOVL6_COMPACT; goto extract_sfmt_movb6_compact; case 99 : itype = SH64_COMPACT_INSN_MOV_COMPACT; goto extract_sfmt_mov_compact; case 100 : itype = SH64_COMPACT_INSN_MOVB7_COMPACT; goto extract_sfmt_movb7_compact; case 101 : itype = SH64_COMPACT_INSN_MOVW7_COMPACT; goto extract_sfmt_movb7_compact; case 102 : itype = SH64_COMPACT_INSN_MOVL7_COMPACT; goto extract_sfmt_movl7_compact; case 103 : itype = SH64_COMPACT_INSN_NOT_COMPACT; goto extract_sfmt_mov_compact; case 104 : itype = SH64_COMPACT_INSN_SWAPB_COMPACT; goto extract_sfmt_extsb_compact; case 105 : itype = SH64_COMPACT_INSN_SWAPW_COMPACT; goto extract_sfmt_extsb_compact; case 106 : itype = SH64_COMPACT_INSN_NEGC_COMPACT; goto extract_sfmt_negc_compact; case 107 : itype = SH64_COMPACT_INSN_NEG_COMPACT; goto extract_sfmt_extsb_compact; case 108 : itype = SH64_COMPACT_INSN_EXTUB_COMPACT; goto extract_sfmt_extsb_compact; case 109 : itype = SH64_COMPACT_INSN_EXTUW_COMPACT; goto extract_sfmt_extsb_compact; case 110 : itype = SH64_COMPACT_INSN_EXTSB_COMPACT; goto extract_sfmt_extsb_compact; case 111 : itype = SH64_COMPACT_INSN_EXTSW_COMPACT; goto extract_sfmt_extsb_compact; case 112 : /* fall through */
+ case 113 : /* fall through */
+ case 114 : /* fall through */
+ case 115 : /* fall through */
+ case 116 : /* fall through */
+ case 117 : /* fall through */
+ case 118 : /* fall through */
+ case 119 : /* fall through */
+ case 120 : /* fall through */
+ case 121 : /* fall through */
+ case 122 : /* fall through */
+ case 123 : /* fall through */
+ case 124 : /* fall through */
+ case 125 : /* fall through */
+ case 126 : /* fall through */
+ case 127 : itype = SH64_COMPACT_INSN_ADDI_COMPACT; goto extract_sfmt_addi_compact; case 128 : /* fall through */
+ case 129 : /* fall through */
+ case 130 : /* fall through */
+ case 131 : /* fall through */
+ case 132 : /* fall through */
+ case 133 : /* fall through */
+ case 134 : /* fall through */
+ case 135 : /* fall through */
+ case 136 : /* fall through */
+ case 137 : /* fall through */
+ case 138 : /* fall through */
+ case 139 : /* fall through */
+ case 140 : /* fall through */
+ case 141 : /* fall through */
+ case 142 : /* fall through */
+ case 143 :
+ {
+ unsigned int val = (((insn >> 8) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_MOVB5_COMPACT; goto extract_sfmt_movb5_compact; case 1 : itype = SH64_COMPACT_INSN_MOVW5_COMPACT; goto extract_sfmt_movw5_compact; case 4 : itype = SH64_COMPACT_INSN_MOVB10_COMPACT; goto extract_sfmt_movb10_compact; case 5 : itype = SH64_COMPACT_INSN_MOVW11_COMPACT; goto extract_sfmt_movw11_compact; case 8 : itype = SH64_COMPACT_INSN_CMPEQI_COMPACT; goto extract_sfmt_cmpeqi_compact; case 9 : itype = SH64_COMPACT_INSN_BT_COMPACT; goto extract_sfmt_bf_compact; case 11 : itype = SH64_COMPACT_INSN_BF_COMPACT; goto extract_sfmt_bf_compact; case 13 : itype = SH64_COMPACT_INSN_BTS_COMPACT; goto extract_sfmt_bf_compact; case 15 : itype = SH64_COMPACT_INSN_BFS_COMPACT; goto extract_sfmt_bf_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 144 : /* fall through */
+ case 145 : /* fall through */
+ case 146 : /* fall through */
+ case 147 : /* fall through */
+ case 148 : /* fall through */
+ case 149 : /* fall through */
+ case 150 : /* fall through */
+ case 151 : /* fall through */
+ case 152 : /* fall through */
+ case 153 : /* fall through */
+ case 154 : /* fall through */
+ case 155 : /* fall through */
+ case 156 : /* fall through */
+ case 157 : /* fall through */
+ case 158 : /* fall through */
+ case 159 : itype = SH64_COMPACT_INSN_MOVW10_COMPACT; goto extract_sfmt_movw10_compact; case 160 : /* fall through */
+ case 161 : /* fall through */
+ case 162 : /* fall through */
+ case 163 : /* fall through */
+ case 164 : /* fall through */
+ case 165 : /* fall through */
+ case 166 : /* fall through */
+ case 167 : /* fall through */
+ case 168 : /* fall through */
+ case 169 : /* fall through */
+ case 170 : /* fall through */
+ case 171 : /* fall through */
+ case 172 : /* fall through */
+ case 173 : /* fall through */
+ case 174 : /* fall through */
+ case 175 : itype = SH64_COMPACT_INSN_BRA_COMPACT; goto extract_sfmt_bra_compact; case 176 : /* fall through */
+ case 177 : /* fall through */
+ case 178 : /* fall through */
+ case 179 : /* fall through */
+ case 180 : /* fall through */
+ case 181 : /* fall through */
+ case 182 : /* fall through */
+ case 183 : /* fall through */
+ case 184 : /* fall through */
+ case 185 : /* fall through */
+ case 186 : /* fall through */
+ case 187 : /* fall through */
+ case 188 : /* fall through */
+ case 189 : /* fall through */
+ case 190 : /* fall through */
+ case 191 : itype = SH64_COMPACT_INSN_BSR_COMPACT; goto extract_sfmt_bsr_compact; case 192 : /* fall through */
+ case 193 : /* fall through */
+ case 194 : /* fall through */
+ case 195 : /* fall through */
+ case 196 : /* fall through */
+ case 197 : /* fall through */
+ case 198 : /* fall through */
+ case 199 : /* fall through */
+ case 200 : /* fall through */
+ case 201 : /* fall through */
+ case 202 : /* fall through */
+ case 203 : /* fall through */
+ case 204 : /* fall through */
+ case 205 : /* fall through */
+ case 206 : /* fall through */
+ case 207 :
+ {
+ unsigned int val = (((insn >> 8) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_MOVB4_COMPACT; goto extract_sfmt_movb4_compact; case 1 : itype = SH64_COMPACT_INSN_MOVW4_COMPACT; goto extract_sfmt_movw4_compact; case 2 : itype = SH64_COMPACT_INSN_MOVL4_COMPACT; goto extract_sfmt_movl4_compact; case 3 : itype = SH64_COMPACT_INSN_TRAPA_COMPACT; goto extract_sfmt_trapa_compact; case 4 : itype = SH64_COMPACT_INSN_MOVB9_COMPACT; goto extract_sfmt_movb9_compact; case 5 : itype = SH64_COMPACT_INSN_MOVW9_COMPACT; goto extract_sfmt_movw9_compact; case 6 : itype = SH64_COMPACT_INSN_MOVL9_COMPACT; goto extract_sfmt_movl9_compact; case 7 : itype = SH64_COMPACT_INSN_MOVA_COMPACT; goto extract_sfmt_mova_compact; case 8 : itype = SH64_COMPACT_INSN_TSTI_COMPACT; goto extract_sfmt_tsti_compact; case 9 : itype = SH64_COMPACT_INSN_ANDI_COMPACT; goto extract_sfmt_andi_compact; case 10 : itype = SH64_COMPACT_INSN_XORI_COMPACT; goto extract_sfmt_xori_compact; case 11 : itype = SH64_COMPACT_INSN_ORI_COMPACT; goto extract_sfmt_andi_compact; case 12 : itype = SH64_COMPACT_INSN_TSTB_COMPACT; goto extract_sfmt_tstb_compact; case 13 : itype = SH64_COMPACT_INSN_ANDB_COMPACT; goto extract_sfmt_andb_compact; case 14 : itype = SH64_COMPACT_INSN_XORB_COMPACT; goto extract_sfmt_andb_compact; case 15 : itype = SH64_COMPACT_INSN_ORB_COMPACT; goto extract_sfmt_andb_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 208 : /* fall through */
+ case 209 : /* fall through */
+ case 210 : /* fall through */
+ case 211 : /* fall through */
+ case 212 : /* fall through */
+ case 213 : /* fall through */
+ case 214 : /* fall through */
+ case 215 : /* fall through */
+ case 216 : /* fall through */
+ case 217 : /* fall through */
+ case 218 : /* fall through */
+ case 219 : /* fall through */
+ case 220 : /* fall through */
+ case 221 : /* fall through */
+ case 222 : /* fall through */
+ case 223 : itype = SH64_COMPACT_INSN_MOVL10_COMPACT; goto extract_sfmt_movl10_compact; case 224 : /* fall through */
+ case 225 : /* fall through */
+ case 226 : /* fall through */
+ case 227 : /* fall through */
+ case 228 : /* fall through */
+ case 229 : /* fall through */
+ case 230 : /* fall through */
+ case 231 : /* fall through */
+ case 232 : /* fall through */
+ case 233 : /* fall through */
+ case 234 : /* fall through */
+ case 235 : /* fall through */
+ case 236 : /* fall through */
+ case 237 : /* fall through */
+ case 238 : /* fall through */
+ case 239 : itype = SH64_COMPACT_INSN_MOVI_COMPACT; goto extract_sfmt_movi_compact; case 240 : itype = SH64_COMPACT_INSN_FADD_COMPACT; goto extract_sfmt_fadd_compact; case 241 : itype = SH64_COMPACT_INSN_FSUB_COMPACT; goto extract_sfmt_fadd_compact; case 242 : itype = SH64_COMPACT_INSN_FMUL_COMPACT; goto extract_sfmt_fadd_compact; case 243 : itype = SH64_COMPACT_INSN_FDIV_COMPACT; goto extract_sfmt_fadd_compact; case 244 : itype = SH64_COMPACT_INSN_FCMPEQ_COMPACT; goto extract_sfmt_fcmpeq_compact; case 245 : itype = SH64_COMPACT_INSN_FCMPGT_COMPACT; goto extract_sfmt_fcmpeq_compact; case 246 : itype = SH64_COMPACT_INSN_FMOV4_COMPACT; goto extract_sfmt_fmov4_compact; case 247 : itype = SH64_COMPACT_INSN_FMOV7_COMPACT; goto extract_sfmt_fmov7_compact; case 248 : itype = SH64_COMPACT_INSN_FMOV2_COMPACT; goto extract_sfmt_fmov2_compact; case 249 : itype = SH64_COMPACT_INSN_FMOV3_COMPACT; goto extract_sfmt_fmov3_compact; case 250 : itype = SH64_COMPACT_INSN_FMOV5_COMPACT; goto extract_sfmt_fmov5_compact; case 251 : itype = SH64_COMPACT_INSN_FMOV6_COMPACT; goto extract_sfmt_fmov6_compact; case 252 : itype = SH64_COMPACT_INSN_FMOV1_COMPACT; goto extract_sfmt_fmov1_compact; case 253 :
+ {
+ unsigned int val = (((insn >> 4) & (15 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_FSTS_COMPACT; goto extract_sfmt_fsts_compact; case 1 : itype = SH64_COMPACT_INSN_FLDS_COMPACT; goto extract_sfmt_flds_compact; case 2 : itype = SH64_COMPACT_INSN_FLOAT_COMPACT; goto extract_sfmt_float_compact; case 3 : itype = SH64_COMPACT_INSN_FTRC_COMPACT; goto extract_sfmt_ftrc_compact; case 4 : itype = SH64_COMPACT_INSN_FNEG_COMPACT; goto extract_sfmt_fabs_compact; case 5 : itype = SH64_COMPACT_INSN_FABS_COMPACT; goto extract_sfmt_fabs_compact; case 6 : itype = SH64_COMPACT_INSN_FSQRT_COMPACT; goto extract_sfmt_fabs_compact; case 8 : itype = SH64_COMPACT_INSN_FLDI0_COMPACT; goto extract_sfmt_fldi0_compact; case 9 : itype = SH64_COMPACT_INSN_FLDI1_COMPACT; goto extract_sfmt_fldi0_compact; case 10 : itype = SH64_COMPACT_INSN_FCNVSD_COMPACT; goto extract_sfmt_fcnvsd_compact; case 11 : itype = SH64_COMPACT_INSN_FCNVDS_COMPACT; goto extract_sfmt_fcnvds_compact; case 14 : itype = SH64_COMPACT_INSN_FIPR_COMPACT; goto extract_sfmt_fipr_compact; case 15 :
+ {
+ unsigned int val = (((insn >> 9) & (1 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_FTRV_COMPACT; goto extract_sfmt_ftrv_compact; case 1 :
+ {
+ unsigned int val = (((insn >> 11) & (1 << 0)));
+ switch (val)
+ {
+ case 0 : itype = SH64_COMPACT_INSN_FSCHG_COMPACT; goto extract_sfmt_fschg_compact; case 1 : itype = SH64_COMPACT_INSN_FRCHG_COMPACT; goto extract_sfmt_frchg_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ case 254 : itype = SH64_COMPACT_INSN_FMAC_COMPACT; goto extract_sfmt_fmac_compact; default : itype = SH64_COMPACT_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ }
+
+ /* The instruction has been decoded, now extract the fields. */
+
+ extract_sfmt_empty:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addi_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ UINT f_rn;
+ UINT f_imm8;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8) = f_imm8;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi_compact", "f_imm8 0x%x", 'x', f_imm8, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addc_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addc_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addv_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_and_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_andi_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ UINT f_imm8;
+
+ f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8) = f_imm8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andi_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_andb_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ UINT f_imm8;
+
+ f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8) = f_imm8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_andb_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bf_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bf_compact.f
+ SI f_disp8;
+
+ f_disp8 = ((((EXTRACT_LSB0_INT (insn, 16, 7, 8)) << (1))) + (((pc) + (4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_disp8) = f_disp8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bf_compact", "disp8 0x%x", 'x', f_disp8, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bra_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bra_compact.f
+ SI f_disp12;
+
+ f_disp12 = ((((EXTRACT_LSB0_INT (insn, 16, 11, 12)) << (1))) + (((pc) + (4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_disp12) = f_disp12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra_compact", "disp12 0x%x", 'x', f_disp12, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_braf_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_braf_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_brk_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brk_compact", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bsr_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_bra_compact.f
+ SI f_disp12;
+
+ f_disp12 = ((((EXTRACT_LSB0_INT (insn, 16, 11, 12)) << (1))) + (((pc) + (4))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (i_disp12) = f_disp12;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bsr_compact", "disp12 0x%x", 'x', f_disp12, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_bsrf_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bsrf_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_clrmac_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrmac_compact", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_clrs_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrs_compact", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_clrt_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrt_compact", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmpeq_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpeq_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmpeqi_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ UINT f_imm8;
+
+ f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8) = f_imm8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpeqi_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmppl_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmppl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_div0s_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div0s_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_div0u_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div0u_compact", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_div1_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div1_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_dmulsl_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dmulsl_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_dt_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_dt_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_extsb_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_extsb_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fabs_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fabs_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fadd_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fadd_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fcmpeq_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcmpeq_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fcnvds_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f
+ SI f_dn;
+
+ f_dn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 3)) << (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dn) = f_dn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcnvds_compact", "f_dn 0x%x", 'x', f_dn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fcnvsd_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f
+ SI f_dn;
+
+ f_dn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 3)) << (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dn) = f_dn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcnvsd_compact", "f_dn 0x%x", 'x', f_dn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fipr_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fipr_compact.f
+ SI f_vn;
+ SI f_vm;
+
+ f_vn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 2)) << (2));
+ f_vm = ((EXTRACT_LSB0_UINT (insn, 16, 9, 2)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_vm) = f_vm;
+ FLD (f_vn) = f_vn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fipr_compact", "f_vm 0x%x", 'x', f_vm, "f_vn 0x%x", 'x', f_vn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flds_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flds_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fldi0_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldi0_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_float_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_float_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fmac_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmac_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fmov1_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov1_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fmov2_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ FLD (f_rm) = f_rm;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov2_compact", "f_rn 0x%x", 'x', f_rn, "f_rm 0x%x", 'x', f_rm, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fmov3_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ FLD (f_rm) = f_rm;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov3_compact", "f_rn 0x%x", 'x', f_rn, "f_rm 0x%x", 'x', f_rm, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fmov4_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ FLD (f_rm) = f_rm;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov4_compact", "f_rn 0x%x", 'x', f_rn, "f_rm 0x%x", 'x', f_rm, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fmov5_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov5_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fmov6_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov6_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fmov7_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmov7_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_frchg_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_frchg_compact", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fschg_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fschg_compact", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fsts_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fsts_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ftrc_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ftrc_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ftrv_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fipr_compact.f
+ SI f_vn;
+
+ f_vn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 2)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_vn) = f_vn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ftrv_compact", "f_vn 0x%x", 'x', f_vn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_jmp_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldc_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldc_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldcl_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldcl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lds_fpscr_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lds_fpscr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldsl_fpscr_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsl_fpscr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lds_fpul_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lds_fpul_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldsl_fpul_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsl_fpul_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lds_mach_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lds_mach_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldsl_mach_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsl_mach_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lds_macl_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lds_macl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldsl_macl_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsl_macl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lds_pr_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lds_pr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldsl_pr_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldsl_pr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_macl_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macl_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_macw_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macw_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mov_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mov_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movi_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ UINT f_rn;
+ UINT f_imm8;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8) = f_imm8;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movi_compact", "f_imm8 0x%x", 'x', f_imm8, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movb1_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb1_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movb2_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb2_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movb3_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb3_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movb4_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ UINT f_imm8;
+
+ f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8) = f_imm8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb4_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movb5_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movb5_compact.f
+ UINT f_rm;
+ UINT f_imm4;
+
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+ f_imm4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm4) = f_imm4;
+ FLD (f_rm) = f_rm;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb5_compact", "f_imm4 0x%x", 'x', f_imm4, "f_rm 0x%x", 'x', f_rm, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movb6_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb6_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movb7_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb7_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movb8_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb8_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movb9_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ UINT f_imm8;
+
+ f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8) = f_imm8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb9_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movb10_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movb5_compact.f
+ UINT f_rm;
+ UINT f_imm4;
+
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+ f_imm4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm4) = f_imm4;
+ FLD (f_rm) = f_rm;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movb10_compact", "f_imm4 0x%x", 'x', f_imm4, "f_rm 0x%x", 'x', f_rm, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movl4_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl10_compact.f
+ SI f_imm8x4;
+
+ f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8x4) = f_imm8x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl4_compact", "f_imm8x4 0x%x", 'x', f_imm8x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movl5_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+ SI f_imm4x4;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+ f_imm4x4 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm4x4) = f_imm4x4;
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl5_compact", "f_imm4x4 0x%x", 'x', f_imm4x4, "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movl7_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl7_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movl9_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl10_compact.f
+ SI f_imm8x4;
+
+ f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8x4) = f_imm8x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl9_compact", "f_imm8x4 0x%x", 'x', f_imm8x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movl10_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl10_compact.f
+ UINT f_rn;
+ SI f_imm8x4;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8x4) = f_imm8x4;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl10_compact", "f_imm8x4 0x%x", 'x', f_imm8x4, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movl11_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+ SI f_imm4x4;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+ f_imm4x4 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm4x4) = f_imm4x4;
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movl11_compact", "f_imm4x4 0x%x", 'x', f_imm4x4, "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movw4_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ SI f_imm8x2;
+
+ f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8x2) = f_imm8x2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw4_compact", "f_imm8x2 0x%x", 'x', f_imm8x2, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movw5_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw5_compact.f
+ UINT f_rn;
+ SI f_imm4x2;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_imm4x2 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm4x2) = f_imm4x2;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw5_compact", "f_imm4x2 0x%x", 'x', f_imm4x2, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movw9_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ SI f_imm8x2;
+
+ f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8x2) = f_imm8x2;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw9_compact", "f_imm8x2 0x%x", 'x', f_imm8x2, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movw10_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+ SI f_imm8x2;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8x2) = f_imm8x2;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw10_compact", "f_imm8x2 0x%x", 'x', f_imm8x2, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movw11_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw11_compact.f
+ UINT f_rm;
+ SI f_imm4x2;
+
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+ f_imm4x2 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm4x2) = f_imm4x2;
+ FLD (f_rm) = f_rm;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movw11_compact", "f_imm4x2 0x%x", 'x', f_imm4x2, "f_rm 0x%x", 'x', f_rm, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mova_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl10_compact.f
+ SI f_imm8x4;
+
+ f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8x4) = f_imm8x4;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mova_compact", "f_imm8x4 0x%x", 'x', f_imm8x4, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movcal_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movcal_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movt_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movt_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mull_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mull_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_negc_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_negc_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_nop_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop_compact", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rotcl_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rotcl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_rts_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rts_compact", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_shad_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ UINT f_rn;
+ UINT f_rm;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rm) = f_rm;
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_shad_compact", "f_rm 0x%x", 'x', f_rm, "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_shll2_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_shll2_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stc_gbr_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stc_gbr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stcl_gbr_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stcl_gbr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sts_fpscr_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sts_fpscr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stsl_fpscr_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stsl_fpscr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sts_fpul_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sts_fpul_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stsl_fpul_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stsl_fpul_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sts_mach_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sts_mach_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stsl_mach_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stsl_mach_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sts_macl_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sts_macl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stsl_macl_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stsl_macl_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sts_pr_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sts_pr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stsl_pr_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stsl_pr_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tasb_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ UINT f_rn;
+
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_rn) = f_rn;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tasb_compact", "f_rn 0x%x", 'x', f_rn, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_trapa_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ UINT f_imm8;
+
+ f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8) = f_imm8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trapa_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tsti_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ UINT f_imm8;
+
+ f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8) = f_imm8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tsti_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_tstb_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ UINT f_imm8;
+
+ f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8) = f_imm8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_tstb_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_xori_compact:
+ {
+ const IDESC *idesc = &sh64_compact_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ UINT f_imm8;
+
+ f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm8) = f_imm8;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_xori_compact", "f_imm8 0x%x", 'x', f_imm8, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+}
--- /dev/null
+/* Decode header for sh64_compact.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef SH64_COMPACT_DECODE_H
+#define SH64_COMPACT_DECODE_H
+
+extern const IDESC *sh64_compact_decode (SIM_CPU *, IADDR,
+ CGEN_INSN_INT, CGEN_INSN_INT,
+ ARGBUF *);
+extern void sh64_compact_init_idesc_table (SIM_CPU *);
+extern void sh64_compact_sem_init_idesc_table (SIM_CPU *);
+extern void sh64_compact_semf_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family sh64. */
+typedef enum sh64_compact_insn_type {
+ SH64_COMPACT_INSN_X_INVALID, SH64_COMPACT_INSN_X_AFTER, SH64_COMPACT_INSN_X_BEFORE, SH64_COMPACT_INSN_X_CTI_CHAIN
+ , SH64_COMPACT_INSN_X_CHAIN, SH64_COMPACT_INSN_X_BEGIN, SH64_COMPACT_INSN_ADD_COMPACT, SH64_COMPACT_INSN_ADDI_COMPACT
+ , SH64_COMPACT_INSN_ADDC_COMPACT, SH64_COMPACT_INSN_ADDV_COMPACT, SH64_COMPACT_INSN_AND_COMPACT, SH64_COMPACT_INSN_ANDI_COMPACT
+ , SH64_COMPACT_INSN_ANDB_COMPACT, SH64_COMPACT_INSN_BF_COMPACT, SH64_COMPACT_INSN_BFS_COMPACT, SH64_COMPACT_INSN_BRA_COMPACT
+ , SH64_COMPACT_INSN_BRAF_COMPACT, SH64_COMPACT_INSN_BRK_COMPACT, SH64_COMPACT_INSN_BSR_COMPACT, SH64_COMPACT_INSN_BSRF_COMPACT
+ , SH64_COMPACT_INSN_BT_COMPACT, SH64_COMPACT_INSN_BTS_COMPACT, SH64_COMPACT_INSN_CLRMAC_COMPACT, SH64_COMPACT_INSN_CLRS_COMPACT
+ , SH64_COMPACT_INSN_CLRT_COMPACT, SH64_COMPACT_INSN_CMPEQ_COMPACT, SH64_COMPACT_INSN_CMPEQI_COMPACT, SH64_COMPACT_INSN_CMPGE_COMPACT
+ , SH64_COMPACT_INSN_CMPGT_COMPACT, SH64_COMPACT_INSN_CMPHI_COMPACT, SH64_COMPACT_INSN_CMPHS_COMPACT, SH64_COMPACT_INSN_CMPPL_COMPACT
+ , SH64_COMPACT_INSN_CMPPZ_COMPACT, SH64_COMPACT_INSN_CMPSTR_COMPACT, SH64_COMPACT_INSN_DIV0S_COMPACT, SH64_COMPACT_INSN_DIV0U_COMPACT
+ , SH64_COMPACT_INSN_DIV1_COMPACT, SH64_COMPACT_INSN_DMULSL_COMPACT, SH64_COMPACT_INSN_DMULUL_COMPACT, SH64_COMPACT_INSN_DT_COMPACT
+ , SH64_COMPACT_INSN_EXTSB_COMPACT, SH64_COMPACT_INSN_EXTSW_COMPACT, SH64_COMPACT_INSN_EXTUB_COMPACT, SH64_COMPACT_INSN_EXTUW_COMPACT
+ , SH64_COMPACT_INSN_FABS_COMPACT, SH64_COMPACT_INSN_FADD_COMPACT, SH64_COMPACT_INSN_FCMPEQ_COMPACT, SH64_COMPACT_INSN_FCMPGT_COMPACT
+ , SH64_COMPACT_INSN_FCNVDS_COMPACT, SH64_COMPACT_INSN_FCNVSD_COMPACT, SH64_COMPACT_INSN_FDIV_COMPACT, SH64_COMPACT_INSN_FIPR_COMPACT
+ , SH64_COMPACT_INSN_FLDS_COMPACT, SH64_COMPACT_INSN_FLDI0_COMPACT, SH64_COMPACT_INSN_FLDI1_COMPACT, SH64_COMPACT_INSN_FLOAT_COMPACT
+ , SH64_COMPACT_INSN_FMAC_COMPACT, SH64_COMPACT_INSN_FMOV1_COMPACT, SH64_COMPACT_INSN_FMOV2_COMPACT, SH64_COMPACT_INSN_FMOV3_COMPACT
+ , SH64_COMPACT_INSN_FMOV4_COMPACT, SH64_COMPACT_INSN_FMOV5_COMPACT, SH64_COMPACT_INSN_FMOV6_COMPACT, SH64_COMPACT_INSN_FMOV7_COMPACT
+ , SH64_COMPACT_INSN_FMUL_COMPACT, SH64_COMPACT_INSN_FNEG_COMPACT, SH64_COMPACT_INSN_FRCHG_COMPACT, SH64_COMPACT_INSN_FSCHG_COMPACT
+ , SH64_COMPACT_INSN_FSQRT_COMPACT, SH64_COMPACT_INSN_FSTS_COMPACT, SH64_COMPACT_INSN_FSUB_COMPACT, SH64_COMPACT_INSN_FTRC_COMPACT
+ , SH64_COMPACT_INSN_FTRV_COMPACT, SH64_COMPACT_INSN_JMP_COMPACT, SH64_COMPACT_INSN_JSR_COMPACT, SH64_COMPACT_INSN_LDC_COMPACT
+ , SH64_COMPACT_INSN_LDCL_COMPACT, SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, SH64_COMPACT_INSN_LDS_FPUL_COMPACT
+ , SH64_COMPACT_INSN_LDSL_FPUL_COMPACT, SH64_COMPACT_INSN_LDS_MACH_COMPACT, SH64_COMPACT_INSN_LDSL_MACH_COMPACT, SH64_COMPACT_INSN_LDS_MACL_COMPACT
+ , SH64_COMPACT_INSN_LDSL_MACL_COMPACT, SH64_COMPACT_INSN_LDS_PR_COMPACT, SH64_COMPACT_INSN_LDSL_PR_COMPACT, SH64_COMPACT_INSN_MACL_COMPACT
+ , SH64_COMPACT_INSN_MACW_COMPACT, SH64_COMPACT_INSN_MOV_COMPACT, SH64_COMPACT_INSN_MOVI_COMPACT, SH64_COMPACT_INSN_MOVB1_COMPACT
+ , SH64_COMPACT_INSN_MOVB2_COMPACT, SH64_COMPACT_INSN_MOVB3_COMPACT, SH64_COMPACT_INSN_MOVB4_COMPACT, SH64_COMPACT_INSN_MOVB5_COMPACT
+ , SH64_COMPACT_INSN_MOVB6_COMPACT, SH64_COMPACT_INSN_MOVB7_COMPACT, SH64_COMPACT_INSN_MOVB8_COMPACT, SH64_COMPACT_INSN_MOVB9_COMPACT
+ , SH64_COMPACT_INSN_MOVB10_COMPACT, SH64_COMPACT_INSN_MOVL1_COMPACT, SH64_COMPACT_INSN_MOVL2_COMPACT, SH64_COMPACT_INSN_MOVL3_COMPACT
+ , SH64_COMPACT_INSN_MOVL4_COMPACT, SH64_COMPACT_INSN_MOVL5_COMPACT, SH64_COMPACT_INSN_MOVL6_COMPACT, SH64_COMPACT_INSN_MOVL7_COMPACT
+ , SH64_COMPACT_INSN_MOVL8_COMPACT, SH64_COMPACT_INSN_MOVL9_COMPACT, SH64_COMPACT_INSN_MOVL10_COMPACT, SH64_COMPACT_INSN_MOVL11_COMPACT
+ , SH64_COMPACT_INSN_MOVW1_COMPACT, SH64_COMPACT_INSN_MOVW2_COMPACT, SH64_COMPACT_INSN_MOVW3_COMPACT, SH64_COMPACT_INSN_MOVW4_COMPACT
+ , SH64_COMPACT_INSN_MOVW5_COMPACT, SH64_COMPACT_INSN_MOVW6_COMPACT, SH64_COMPACT_INSN_MOVW7_COMPACT, SH64_COMPACT_INSN_MOVW8_COMPACT
+ , SH64_COMPACT_INSN_MOVW9_COMPACT, SH64_COMPACT_INSN_MOVW10_COMPACT, SH64_COMPACT_INSN_MOVW11_COMPACT, SH64_COMPACT_INSN_MOVA_COMPACT
+ , SH64_COMPACT_INSN_MOVCAL_COMPACT, SH64_COMPACT_INSN_MOVT_COMPACT, SH64_COMPACT_INSN_MULL_COMPACT, SH64_COMPACT_INSN_MULSW_COMPACT
+ , SH64_COMPACT_INSN_MULUW_COMPACT, SH64_COMPACT_INSN_NEG_COMPACT, SH64_COMPACT_INSN_NEGC_COMPACT, SH64_COMPACT_INSN_NOP_COMPACT
+ , SH64_COMPACT_INSN_NOT_COMPACT, SH64_COMPACT_INSN_OCBI_COMPACT, SH64_COMPACT_INSN_OCBP_COMPACT, SH64_COMPACT_INSN_OCBWB_COMPACT
+ , SH64_COMPACT_INSN_OR_COMPACT, SH64_COMPACT_INSN_ORI_COMPACT, SH64_COMPACT_INSN_ORB_COMPACT, SH64_COMPACT_INSN_PREF_COMPACT
+ , SH64_COMPACT_INSN_ROTCL_COMPACT, SH64_COMPACT_INSN_ROTCR_COMPACT, SH64_COMPACT_INSN_ROTL_COMPACT, SH64_COMPACT_INSN_ROTR_COMPACT
+ , SH64_COMPACT_INSN_RTS_COMPACT, SH64_COMPACT_INSN_SETS_COMPACT, SH64_COMPACT_INSN_SETT_COMPACT, SH64_COMPACT_INSN_SHAD_COMPACT
+ , SH64_COMPACT_INSN_SHAL_COMPACT, SH64_COMPACT_INSN_SHAR_COMPACT, SH64_COMPACT_INSN_SHLD_COMPACT, SH64_COMPACT_INSN_SHLL_COMPACT
+ , SH64_COMPACT_INSN_SHLL2_COMPACT, SH64_COMPACT_INSN_SHLL8_COMPACT, SH64_COMPACT_INSN_SHLL16_COMPACT, SH64_COMPACT_INSN_SHLR_COMPACT
+ , SH64_COMPACT_INSN_SHLR2_COMPACT, SH64_COMPACT_INSN_SHLR8_COMPACT, SH64_COMPACT_INSN_SHLR16_COMPACT, SH64_COMPACT_INSN_STC_GBR_COMPACT
+ , SH64_COMPACT_INSN_STCL_GBR_COMPACT, SH64_COMPACT_INSN_STS_FPSCR_COMPACT, SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, SH64_COMPACT_INSN_STS_FPUL_COMPACT
+ , SH64_COMPACT_INSN_STSL_FPUL_COMPACT, SH64_COMPACT_INSN_STS_MACH_COMPACT, SH64_COMPACT_INSN_STSL_MACH_COMPACT, SH64_COMPACT_INSN_STS_MACL_COMPACT
+ , SH64_COMPACT_INSN_STSL_MACL_COMPACT, SH64_COMPACT_INSN_STS_PR_COMPACT, SH64_COMPACT_INSN_STSL_PR_COMPACT, SH64_COMPACT_INSN_SUB_COMPACT
+ , SH64_COMPACT_INSN_SUBC_COMPACT, SH64_COMPACT_INSN_SUBV_COMPACT, SH64_COMPACT_INSN_SWAPB_COMPACT, SH64_COMPACT_INSN_SWAPW_COMPACT
+ , SH64_COMPACT_INSN_TASB_COMPACT, SH64_COMPACT_INSN_TRAPA_COMPACT, SH64_COMPACT_INSN_TST_COMPACT, SH64_COMPACT_INSN_TSTI_COMPACT
+ , SH64_COMPACT_INSN_TSTB_COMPACT, SH64_COMPACT_INSN_XOR_COMPACT, SH64_COMPACT_INSN_XORI_COMPACT, SH64_COMPACT_INSN_XORB_COMPACT
+ , SH64_COMPACT_INSN_XTRCT_COMPACT, SH64_COMPACT_INSN_MAX
+} SH64_COMPACT_INSN_TYPE;
+
+/* Enum declaration for semantic formats in cpu family sh64. */
+typedef enum sh64_compact_sfmt_type {
+ SH64_COMPACT_SFMT_EMPTY, SH64_COMPACT_SFMT_ADD_COMPACT, SH64_COMPACT_SFMT_ADDI_COMPACT, SH64_COMPACT_SFMT_ADDC_COMPACT
+ , SH64_COMPACT_SFMT_ADDV_COMPACT, SH64_COMPACT_SFMT_AND_COMPACT, SH64_COMPACT_SFMT_ANDI_COMPACT, SH64_COMPACT_SFMT_ANDB_COMPACT
+ , SH64_COMPACT_SFMT_BF_COMPACT, SH64_COMPACT_SFMT_BRA_COMPACT, SH64_COMPACT_SFMT_BRAF_COMPACT, SH64_COMPACT_SFMT_BRK_COMPACT
+ , SH64_COMPACT_SFMT_BSR_COMPACT, SH64_COMPACT_SFMT_BSRF_COMPACT, SH64_COMPACT_SFMT_CLRMAC_COMPACT, SH64_COMPACT_SFMT_CLRS_COMPACT
+ , SH64_COMPACT_SFMT_CLRT_COMPACT, SH64_COMPACT_SFMT_CMPEQ_COMPACT, SH64_COMPACT_SFMT_CMPEQI_COMPACT, SH64_COMPACT_SFMT_CMPPL_COMPACT
+ , SH64_COMPACT_SFMT_DIV0S_COMPACT, SH64_COMPACT_SFMT_DIV0U_COMPACT, SH64_COMPACT_SFMT_DIV1_COMPACT, SH64_COMPACT_SFMT_DMULSL_COMPACT
+ , SH64_COMPACT_SFMT_DT_COMPACT, SH64_COMPACT_SFMT_EXTSB_COMPACT, SH64_COMPACT_SFMT_FABS_COMPACT, SH64_COMPACT_SFMT_FADD_COMPACT
+ , SH64_COMPACT_SFMT_FCMPEQ_COMPACT, SH64_COMPACT_SFMT_FCNVDS_COMPACT, SH64_COMPACT_SFMT_FCNVSD_COMPACT, SH64_COMPACT_SFMT_FIPR_COMPACT
+ , SH64_COMPACT_SFMT_FLDS_COMPACT, SH64_COMPACT_SFMT_FLDI0_COMPACT, SH64_COMPACT_SFMT_FLOAT_COMPACT, SH64_COMPACT_SFMT_FMAC_COMPACT
+ , SH64_COMPACT_SFMT_FMOV1_COMPACT, SH64_COMPACT_SFMT_FMOV2_COMPACT, SH64_COMPACT_SFMT_FMOV3_COMPACT, SH64_COMPACT_SFMT_FMOV4_COMPACT
+ , SH64_COMPACT_SFMT_FMOV5_COMPACT, SH64_COMPACT_SFMT_FMOV6_COMPACT, SH64_COMPACT_SFMT_FMOV7_COMPACT, SH64_COMPACT_SFMT_FRCHG_COMPACT
+ , SH64_COMPACT_SFMT_FSCHG_COMPACT, SH64_COMPACT_SFMT_FSTS_COMPACT, SH64_COMPACT_SFMT_FTRC_COMPACT, SH64_COMPACT_SFMT_FTRV_COMPACT
+ , SH64_COMPACT_SFMT_JMP_COMPACT, SH64_COMPACT_SFMT_LDC_COMPACT, SH64_COMPACT_SFMT_LDCL_COMPACT, SH64_COMPACT_SFMT_LDS_FPSCR_COMPACT
+ , SH64_COMPACT_SFMT_LDSL_FPSCR_COMPACT, SH64_COMPACT_SFMT_LDS_FPUL_COMPACT, SH64_COMPACT_SFMT_LDSL_FPUL_COMPACT, SH64_COMPACT_SFMT_LDS_MACH_COMPACT
+ , SH64_COMPACT_SFMT_LDSL_MACH_COMPACT, SH64_COMPACT_SFMT_LDS_MACL_COMPACT, SH64_COMPACT_SFMT_LDSL_MACL_COMPACT, SH64_COMPACT_SFMT_LDS_PR_COMPACT
+ , SH64_COMPACT_SFMT_LDSL_PR_COMPACT, SH64_COMPACT_SFMT_MACL_COMPACT, SH64_COMPACT_SFMT_MACW_COMPACT, SH64_COMPACT_SFMT_MOV_COMPACT
+ , SH64_COMPACT_SFMT_MOVI_COMPACT, SH64_COMPACT_SFMT_MOVB1_COMPACT, SH64_COMPACT_SFMT_MOVB2_COMPACT, SH64_COMPACT_SFMT_MOVB3_COMPACT
+ , SH64_COMPACT_SFMT_MOVB4_COMPACT, SH64_COMPACT_SFMT_MOVB5_COMPACT, SH64_COMPACT_SFMT_MOVB6_COMPACT, SH64_COMPACT_SFMT_MOVB7_COMPACT
+ , SH64_COMPACT_SFMT_MOVB8_COMPACT, SH64_COMPACT_SFMT_MOVB9_COMPACT, SH64_COMPACT_SFMT_MOVB10_COMPACT, SH64_COMPACT_SFMT_MOVL4_COMPACT
+ , SH64_COMPACT_SFMT_MOVL5_COMPACT, SH64_COMPACT_SFMT_MOVL7_COMPACT, SH64_COMPACT_SFMT_MOVL9_COMPACT, SH64_COMPACT_SFMT_MOVL10_COMPACT
+ , SH64_COMPACT_SFMT_MOVL11_COMPACT, SH64_COMPACT_SFMT_MOVW4_COMPACT, SH64_COMPACT_SFMT_MOVW5_COMPACT, SH64_COMPACT_SFMT_MOVW9_COMPACT
+ , SH64_COMPACT_SFMT_MOVW10_COMPACT, SH64_COMPACT_SFMT_MOVW11_COMPACT, SH64_COMPACT_SFMT_MOVA_COMPACT, SH64_COMPACT_SFMT_MOVCAL_COMPACT
+ , SH64_COMPACT_SFMT_MOVT_COMPACT, SH64_COMPACT_SFMT_MULL_COMPACT, SH64_COMPACT_SFMT_NEGC_COMPACT, SH64_COMPACT_SFMT_NOP_COMPACT
+ , SH64_COMPACT_SFMT_ROTCL_COMPACT, SH64_COMPACT_SFMT_RTS_COMPACT, SH64_COMPACT_SFMT_SHAD_COMPACT, SH64_COMPACT_SFMT_SHLL2_COMPACT
+ , SH64_COMPACT_SFMT_STC_GBR_COMPACT, SH64_COMPACT_SFMT_STCL_GBR_COMPACT, SH64_COMPACT_SFMT_STS_FPSCR_COMPACT, SH64_COMPACT_SFMT_STSL_FPSCR_COMPACT
+ , SH64_COMPACT_SFMT_STS_FPUL_COMPACT, SH64_COMPACT_SFMT_STSL_FPUL_COMPACT, SH64_COMPACT_SFMT_STS_MACH_COMPACT, SH64_COMPACT_SFMT_STSL_MACH_COMPACT
+ , SH64_COMPACT_SFMT_STS_MACL_COMPACT, SH64_COMPACT_SFMT_STSL_MACL_COMPACT, SH64_COMPACT_SFMT_STS_PR_COMPACT, SH64_COMPACT_SFMT_STSL_PR_COMPACT
+ , SH64_COMPACT_SFMT_TASB_COMPACT, SH64_COMPACT_SFMT_TRAPA_COMPACT, SH64_COMPACT_SFMT_TSTI_COMPACT, SH64_COMPACT_SFMT_TSTB_COMPACT
+ , SH64_COMPACT_SFMT_XORI_COMPACT
+} SH64_COMPACT_SFMT_TYPE;
+
+/* Function unit handlers (user written). */
+
+extern int sh64_model_sh5_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void sh64_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void sh64_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* SH64_COMPACT_DECODE_H */
--- /dev/null
+/* Simulator instruction decoder for sh64_media.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU sh64
+#define WANT_CPU_SH64
+
+#include "sim-main.h"
+#include "sim-assert.h"
+
+/* The instruction descriptor array.
+ This is computed at runtime. Space for it is not malloc'd to save a
+ teensy bit of cpu in the decoder. Moving it to malloc space is trivial
+ but won't be done until necessary (we don't currently support the runtime
+ addition of instructions nor an SMP machine with different cpus). */
+static IDESC sh64_media_insn_data[SH64_MEDIA_INSN_MAX];
+
+/* Commas between elements are contained in the macros.
+ Some of these are conditionally compiled out. */
+
+static const struct insn_sem sh64_media_insn_sem[] =
+{
+ { VIRTUAL_INSN_X_INVALID, SH64_MEDIA_INSN_X_INVALID, SH64_MEDIA_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_AFTER, SH64_MEDIA_INSN_X_AFTER, SH64_MEDIA_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEFORE, SH64_MEDIA_INSN_X_BEFORE, SH64_MEDIA_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CTI_CHAIN, SH64_MEDIA_INSN_X_CTI_CHAIN, SH64_MEDIA_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_CHAIN, SH64_MEDIA_INSN_X_CHAIN, SH64_MEDIA_SFMT_EMPTY },
+ { VIRTUAL_INSN_X_BEGIN, SH64_MEDIA_INSN_X_BEGIN, SH64_MEDIA_SFMT_EMPTY },
+ { SH_INSN_ADD, SH64_MEDIA_INSN_ADD, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_ADDL, SH64_MEDIA_INSN_ADDL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_ADDI, SH64_MEDIA_INSN_ADDI, SH64_MEDIA_SFMT_ADDI },
+ { SH_INSN_ADDIL, SH64_MEDIA_INSN_ADDIL, SH64_MEDIA_SFMT_ADDI },
+ { SH_INSN_ADDZL, SH64_MEDIA_INSN_ADDZL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_ALLOCO, SH64_MEDIA_INSN_ALLOCO, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_AND, SH64_MEDIA_INSN_AND, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_ANDC, SH64_MEDIA_INSN_ANDC, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_ANDI, SH64_MEDIA_INSN_ANDI, SH64_MEDIA_SFMT_ADDI },
+ { SH_INSN_BEQ, SH64_MEDIA_INSN_BEQ, SH64_MEDIA_SFMT_BEQ },
+ { SH_INSN_BEQI, SH64_MEDIA_INSN_BEQI, SH64_MEDIA_SFMT_BEQI },
+ { SH_INSN_BGE, SH64_MEDIA_INSN_BGE, SH64_MEDIA_SFMT_BEQ },
+ { SH_INSN_BGEU, SH64_MEDIA_INSN_BGEU, SH64_MEDIA_SFMT_BEQ },
+ { SH_INSN_BGT, SH64_MEDIA_INSN_BGT, SH64_MEDIA_SFMT_BEQ },
+ { SH_INSN_BGTU, SH64_MEDIA_INSN_BGTU, SH64_MEDIA_SFMT_BEQ },
+ { SH_INSN_BLINK, SH64_MEDIA_INSN_BLINK, SH64_MEDIA_SFMT_BLINK },
+ { SH_INSN_BNE, SH64_MEDIA_INSN_BNE, SH64_MEDIA_SFMT_BEQ },
+ { SH_INSN_BNEI, SH64_MEDIA_INSN_BNEI, SH64_MEDIA_SFMT_BEQI },
+ { SH_INSN_BRK, SH64_MEDIA_INSN_BRK, SH64_MEDIA_SFMT_BRK },
+ { SH_INSN_BYTEREV, SH64_MEDIA_INSN_BYTEREV, SH64_MEDIA_SFMT_BYTEREV },
+ { SH_INSN_CMPEQ, SH64_MEDIA_INSN_CMPEQ, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_CMPGT, SH64_MEDIA_INSN_CMPGT, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_CMPGTU, SH64_MEDIA_INSN_CMPGTU, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_CMVEQ, SH64_MEDIA_INSN_CMVEQ, SH64_MEDIA_SFMT_CMVEQ },
+ { SH_INSN_CMVNE, SH64_MEDIA_INSN_CMVNE, SH64_MEDIA_SFMT_CMVEQ },
+ { SH_INSN_FABSD, SH64_MEDIA_INSN_FABSD, SH64_MEDIA_SFMT_FABSD },
+ { SH_INSN_FABSS, SH64_MEDIA_INSN_FABSS, SH64_MEDIA_SFMT_FABSS },
+ { SH_INSN_FADDD, SH64_MEDIA_INSN_FADDD, SH64_MEDIA_SFMT_FADDD },
+ { SH_INSN_FADDS, SH64_MEDIA_INSN_FADDS, SH64_MEDIA_SFMT_FADDS },
+ { SH_INSN_FCMPEQD, SH64_MEDIA_INSN_FCMPEQD, SH64_MEDIA_SFMT_FCMPEQD },
+ { SH_INSN_FCMPEQS, SH64_MEDIA_INSN_FCMPEQS, SH64_MEDIA_SFMT_FCMPEQS },
+ { SH_INSN_FCMPGED, SH64_MEDIA_INSN_FCMPGED, SH64_MEDIA_SFMT_FCMPEQD },
+ { SH_INSN_FCMPGES, SH64_MEDIA_INSN_FCMPGES, SH64_MEDIA_SFMT_FCMPEQS },
+ { SH_INSN_FCMPGTD, SH64_MEDIA_INSN_FCMPGTD, SH64_MEDIA_SFMT_FCMPEQD },
+ { SH_INSN_FCMPGTS, SH64_MEDIA_INSN_FCMPGTS, SH64_MEDIA_SFMT_FCMPEQS },
+ { SH_INSN_FCMPUND, SH64_MEDIA_INSN_FCMPUND, SH64_MEDIA_SFMT_FCMPEQD },
+ { SH_INSN_FCMPUNS, SH64_MEDIA_INSN_FCMPUNS, SH64_MEDIA_SFMT_FCMPEQS },
+ { SH_INSN_FCNVDS, SH64_MEDIA_INSN_FCNVDS, SH64_MEDIA_SFMT_FCNVDS },
+ { SH_INSN_FCNVSD, SH64_MEDIA_INSN_FCNVSD, SH64_MEDIA_SFMT_FCNVSD },
+ { SH_INSN_FDIVD, SH64_MEDIA_INSN_FDIVD, SH64_MEDIA_SFMT_FADDD },
+ { SH_INSN_FDIVS, SH64_MEDIA_INSN_FDIVS, SH64_MEDIA_SFMT_FADDS },
+ { SH_INSN_FGETSCR, SH64_MEDIA_INSN_FGETSCR, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_FIPRS, SH64_MEDIA_INSN_FIPRS, SH64_MEDIA_SFMT_FIPRS },
+ { SH_INSN_FLDD, SH64_MEDIA_INSN_FLDD, SH64_MEDIA_SFMT_FLDD },
+ { SH_INSN_FLDP, SH64_MEDIA_INSN_FLDP, SH64_MEDIA_SFMT_FLDP },
+ { SH_INSN_FLDS, SH64_MEDIA_INSN_FLDS, SH64_MEDIA_SFMT_FLDS },
+ { SH_INSN_FLDXD, SH64_MEDIA_INSN_FLDXD, SH64_MEDIA_SFMT_FLDXD },
+ { SH_INSN_FLDXP, SH64_MEDIA_INSN_FLDXP, SH64_MEDIA_SFMT_FLDXP },
+ { SH_INSN_FLDXS, SH64_MEDIA_INSN_FLDXS, SH64_MEDIA_SFMT_FLDXS },
+ { SH_INSN_FLOATLD, SH64_MEDIA_INSN_FLOATLD, SH64_MEDIA_SFMT_FCNVSD },
+ { SH_INSN_FLOATLS, SH64_MEDIA_INSN_FLOATLS, SH64_MEDIA_SFMT_FABSS },
+ { SH_INSN_FLOATQD, SH64_MEDIA_INSN_FLOATQD, SH64_MEDIA_SFMT_FABSD },
+ { SH_INSN_FLOATQS, SH64_MEDIA_INSN_FLOATQS, SH64_MEDIA_SFMT_FCNVDS },
+ { SH_INSN_FMACS, SH64_MEDIA_INSN_FMACS, SH64_MEDIA_SFMT_FMACS },
+ { SH_INSN_FMOVD, SH64_MEDIA_INSN_FMOVD, SH64_MEDIA_SFMT_FABSD },
+ { SH_INSN_FMOVDQ, SH64_MEDIA_INSN_FMOVDQ, SH64_MEDIA_SFMT_FMOVDQ },
+ { SH_INSN_FMOVLS, SH64_MEDIA_INSN_FMOVLS, SH64_MEDIA_SFMT_FMOVLS },
+ { SH_INSN_FMOVQD, SH64_MEDIA_INSN_FMOVQD, SH64_MEDIA_SFMT_FMOVQD },
+ { SH_INSN_FMOVS, SH64_MEDIA_INSN_FMOVS, SH64_MEDIA_SFMT_FABSS },
+ { SH_INSN_FMOVSL, SH64_MEDIA_INSN_FMOVSL, SH64_MEDIA_SFMT_FMOVSL },
+ { SH_INSN_FMULD, SH64_MEDIA_INSN_FMULD, SH64_MEDIA_SFMT_FADDD },
+ { SH_INSN_FMULS, SH64_MEDIA_INSN_FMULS, SH64_MEDIA_SFMT_FADDS },
+ { SH_INSN_FNEGD, SH64_MEDIA_INSN_FNEGD, SH64_MEDIA_SFMT_FABSD },
+ { SH_INSN_FNEGS, SH64_MEDIA_INSN_FNEGS, SH64_MEDIA_SFMT_FABSS },
+ { SH_INSN_FPUTSCR, SH64_MEDIA_INSN_FPUTSCR, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_FSQRTD, SH64_MEDIA_INSN_FSQRTD, SH64_MEDIA_SFMT_FABSD },
+ { SH_INSN_FSQRTS, SH64_MEDIA_INSN_FSQRTS, SH64_MEDIA_SFMT_FABSS },
+ { SH_INSN_FSTD, SH64_MEDIA_INSN_FSTD, SH64_MEDIA_SFMT_FSTD },
+ { SH_INSN_FSTP, SH64_MEDIA_INSN_FSTP, SH64_MEDIA_SFMT_FSTP },
+ { SH_INSN_FSTS, SH64_MEDIA_INSN_FSTS, SH64_MEDIA_SFMT_FSTS },
+ { SH_INSN_FSTXD, SH64_MEDIA_INSN_FSTXD, SH64_MEDIA_SFMT_FSTXD },
+ { SH_INSN_FSTXP, SH64_MEDIA_INSN_FSTXP, SH64_MEDIA_SFMT_FSTXP },
+ { SH_INSN_FSTXS, SH64_MEDIA_INSN_FSTXS, SH64_MEDIA_SFMT_FSTXS },
+ { SH_INSN_FSUBD, SH64_MEDIA_INSN_FSUBD, SH64_MEDIA_SFMT_FADDD },
+ { SH_INSN_FSUBS, SH64_MEDIA_INSN_FSUBS, SH64_MEDIA_SFMT_FADDS },
+ { SH_INSN_FTRCDL, SH64_MEDIA_INSN_FTRCDL, SH64_MEDIA_SFMT_FCNVDS },
+ { SH_INSN_FTRCSL, SH64_MEDIA_INSN_FTRCSL, SH64_MEDIA_SFMT_FABSS },
+ { SH_INSN_FTRCDQ, SH64_MEDIA_INSN_FTRCDQ, SH64_MEDIA_SFMT_FABSD },
+ { SH_INSN_FTRCSQ, SH64_MEDIA_INSN_FTRCSQ, SH64_MEDIA_SFMT_FCNVSD },
+ { SH_INSN_FTRVS, SH64_MEDIA_INSN_FTRVS, SH64_MEDIA_SFMT_FTRVS },
+ { SH_INSN_GETCFG, SH64_MEDIA_INSN_GETCFG, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_GETCON, SH64_MEDIA_INSN_GETCON, SH64_MEDIA_SFMT_GETCON },
+ { SH_INSN_GETTR, SH64_MEDIA_INSN_GETTR, SH64_MEDIA_SFMT_GETTR },
+ { SH_INSN_ICBI, SH64_MEDIA_INSN_ICBI, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_LDB, SH64_MEDIA_INSN_LDB, SH64_MEDIA_SFMT_LDB },
+ { SH_INSN_LDL, SH64_MEDIA_INSN_LDL, SH64_MEDIA_SFMT_LDL },
+ { SH_INSN_LDQ, SH64_MEDIA_INSN_LDQ, SH64_MEDIA_SFMT_LDQ },
+ { SH_INSN_LDUB, SH64_MEDIA_INSN_LDUB, SH64_MEDIA_SFMT_LDB },
+ { SH_INSN_LDUW, SH64_MEDIA_INSN_LDUW, SH64_MEDIA_SFMT_LDUW },
+ { SH_INSN_LDW, SH64_MEDIA_INSN_LDW, SH64_MEDIA_SFMT_LDUW },
+ { SH_INSN_LDHIL, SH64_MEDIA_INSN_LDHIL, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_LDHIQ, SH64_MEDIA_INSN_LDHIQ, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_LDLOL, SH64_MEDIA_INSN_LDLOL, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_LDLOQ, SH64_MEDIA_INSN_LDLOQ, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_LDXB, SH64_MEDIA_INSN_LDXB, SH64_MEDIA_SFMT_LDXB },
+ { SH_INSN_LDXL, SH64_MEDIA_INSN_LDXL, SH64_MEDIA_SFMT_LDXB },
+ { SH_INSN_LDXQ, SH64_MEDIA_INSN_LDXQ, SH64_MEDIA_SFMT_LDXB },
+ { SH_INSN_LDXUB, SH64_MEDIA_INSN_LDXUB, SH64_MEDIA_SFMT_LDXB },
+ { SH_INSN_LDXUW, SH64_MEDIA_INSN_LDXUW, SH64_MEDIA_SFMT_LDXB },
+ { SH_INSN_LDXW, SH64_MEDIA_INSN_LDXW, SH64_MEDIA_SFMT_LDXB },
+ { SH_INSN_MABSL, SH64_MEDIA_INSN_MABSL, SH64_MEDIA_SFMT_BYTEREV },
+ { SH_INSN_MABSW, SH64_MEDIA_INSN_MABSW, SH64_MEDIA_SFMT_BYTEREV },
+ { SH_INSN_MADDL, SH64_MEDIA_INSN_MADDL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MADDW, SH64_MEDIA_INSN_MADDW, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MADDSL, SH64_MEDIA_INSN_MADDSL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MADDSUB, SH64_MEDIA_INSN_MADDSUB, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MADDSW, SH64_MEDIA_INSN_MADDSW, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MCMPEQB, SH64_MEDIA_INSN_MCMPEQB, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MCMPEQL, SH64_MEDIA_INSN_MCMPEQL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MCMPEQW, SH64_MEDIA_INSN_MCMPEQW, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MCMPGTL, SH64_MEDIA_INSN_MCMPGTL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MCMPGTUB, SH64_MEDIA_INSN_MCMPGTUB, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MCMPGTW, SH64_MEDIA_INSN_MCMPGTW, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MCMV, SH64_MEDIA_INSN_MCMV, SH64_MEDIA_SFMT_MCMV },
+ { SH_INSN_MCNVSLW, SH64_MEDIA_INSN_MCNVSLW, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MCNVSWB, SH64_MEDIA_INSN_MCNVSWB, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MCNVSWUB, SH64_MEDIA_INSN_MCNVSWUB, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MEXTR1, SH64_MEDIA_INSN_MEXTR1, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MEXTR2, SH64_MEDIA_INSN_MEXTR2, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MEXTR3, SH64_MEDIA_INSN_MEXTR3, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MEXTR4, SH64_MEDIA_INSN_MEXTR4, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MEXTR5, SH64_MEDIA_INSN_MEXTR5, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MEXTR6, SH64_MEDIA_INSN_MEXTR6, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MEXTR7, SH64_MEDIA_INSN_MEXTR7, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MMACFXWL, SH64_MEDIA_INSN_MMACFXWL, SH64_MEDIA_SFMT_MCMV },
+ { SH_INSN_MMACNFX_WL, SH64_MEDIA_INSN_MMACNFX_WL, SH64_MEDIA_SFMT_MCMV },
+ { SH_INSN_MMULL, SH64_MEDIA_INSN_MMULL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MMULW, SH64_MEDIA_INSN_MMULW, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MMULFXL, SH64_MEDIA_INSN_MMULFXL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MMULFXW, SH64_MEDIA_INSN_MMULFXW, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MMULFXRPW, SH64_MEDIA_INSN_MMULFXRPW, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MMULHIWL, SH64_MEDIA_INSN_MMULHIWL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MMULLOWL, SH64_MEDIA_INSN_MMULLOWL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MMULSUMWQ, SH64_MEDIA_INSN_MMULSUMWQ, SH64_MEDIA_SFMT_MCMV },
+ { SH_INSN_MOVI, SH64_MEDIA_INSN_MOVI, SH64_MEDIA_SFMT_MOVI },
+ { SH_INSN_MPERMW, SH64_MEDIA_INSN_MPERMW, SH64_MEDIA_SFMT_MPERMW },
+ { SH_INSN_MSADUBQ, SH64_MEDIA_INSN_MSADUBQ, SH64_MEDIA_SFMT_MCMV },
+ { SH_INSN_MSHALDSL, SH64_MEDIA_INSN_MSHALDSL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSHALDSW, SH64_MEDIA_INSN_MSHALDSW, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSHARDL, SH64_MEDIA_INSN_MSHARDL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSHARDW, SH64_MEDIA_INSN_MSHARDW, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSHARDSQ, SH64_MEDIA_INSN_MSHARDSQ, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSHFHIB, SH64_MEDIA_INSN_MSHFHIB, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSHFHIL, SH64_MEDIA_INSN_MSHFHIL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSHFHIW, SH64_MEDIA_INSN_MSHFHIW, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSHFLOB, SH64_MEDIA_INSN_MSHFLOB, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSHFLOL, SH64_MEDIA_INSN_MSHFLOL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSHFLOW, SH64_MEDIA_INSN_MSHFLOW, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSHLLDL, SH64_MEDIA_INSN_MSHLLDL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSHLLDW, SH64_MEDIA_INSN_MSHLLDW, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSHLRDL, SH64_MEDIA_INSN_MSHLRDL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSHLRDW, SH64_MEDIA_INSN_MSHLRDW, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSUBL, SH64_MEDIA_INSN_MSUBL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSUBW, SH64_MEDIA_INSN_MSUBW, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSUBSL, SH64_MEDIA_INSN_MSUBSL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSUBSUB, SH64_MEDIA_INSN_MSUBSUB, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MSUBSW, SH64_MEDIA_INSN_MSUBSW, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MULSL, SH64_MEDIA_INSN_MULSL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_MULUL, SH64_MEDIA_INSN_MULUL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_NOP, SH64_MEDIA_INSN_NOP, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_NSB, SH64_MEDIA_INSN_NSB, SH64_MEDIA_SFMT_BYTEREV },
+ { SH_INSN_OCBI, SH64_MEDIA_INSN_OCBI, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_OCBP, SH64_MEDIA_INSN_OCBP, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_OCBWB, SH64_MEDIA_INSN_OCBWB, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_OR, SH64_MEDIA_INSN_OR, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_ORI, SH64_MEDIA_INSN_ORI, SH64_MEDIA_SFMT_ORI },
+ { SH_INSN_PREFI, SH64_MEDIA_INSN_PREFI, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_PTA, SH64_MEDIA_INSN_PTA, SH64_MEDIA_SFMT_PTA },
+ { SH_INSN_PTABS, SH64_MEDIA_INSN_PTABS, SH64_MEDIA_SFMT_PTABS },
+ { SH_INSN_PTB, SH64_MEDIA_INSN_PTB, SH64_MEDIA_SFMT_PTA },
+ { SH_INSN_PTREL, SH64_MEDIA_INSN_PTREL, SH64_MEDIA_SFMT_PTREL },
+ { SH_INSN_PUTCFG, SH64_MEDIA_INSN_PUTCFG, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_PUTCON, SH64_MEDIA_INSN_PUTCON, SH64_MEDIA_SFMT_PUTCON },
+ { SH_INSN_RTE, SH64_MEDIA_INSN_RTE, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_SHARD, SH64_MEDIA_INSN_SHARD, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_SHARDL, SH64_MEDIA_INSN_SHARDL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_SHARI, SH64_MEDIA_INSN_SHARI, SH64_MEDIA_SFMT_SHARI },
+ { SH_INSN_SHARIL, SH64_MEDIA_INSN_SHARIL, SH64_MEDIA_SFMT_SHARIL },
+ { SH_INSN_SHLLD, SH64_MEDIA_INSN_SHLLD, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_SHLLDL, SH64_MEDIA_INSN_SHLLDL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_SHLLI, SH64_MEDIA_INSN_SHLLI, SH64_MEDIA_SFMT_SHARI },
+ { SH_INSN_SHLLIL, SH64_MEDIA_INSN_SHLLIL, SH64_MEDIA_SFMT_SHARIL },
+ { SH_INSN_SHLRD, SH64_MEDIA_INSN_SHLRD, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_SHLRDL, SH64_MEDIA_INSN_SHLRDL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_SHLRI, SH64_MEDIA_INSN_SHLRI, SH64_MEDIA_SFMT_SHARI },
+ { SH_INSN_SHLRIL, SH64_MEDIA_INSN_SHLRIL, SH64_MEDIA_SFMT_SHARIL },
+ { SH_INSN_SHORI, SH64_MEDIA_INSN_SHORI, SH64_MEDIA_SFMT_SHORI },
+ { SH_INSN_SLEEP, SH64_MEDIA_INSN_SLEEP, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_STB, SH64_MEDIA_INSN_STB, SH64_MEDIA_SFMT_STB },
+ { SH_INSN_STL, SH64_MEDIA_INSN_STL, SH64_MEDIA_SFMT_STL },
+ { SH_INSN_STQ, SH64_MEDIA_INSN_STQ, SH64_MEDIA_SFMT_STQ },
+ { SH_INSN_STW, SH64_MEDIA_INSN_STW, SH64_MEDIA_SFMT_STW },
+ { SH_INSN_STHIL, SH64_MEDIA_INSN_STHIL, SH64_MEDIA_SFMT_STHIL },
+ { SH_INSN_STHIQ, SH64_MEDIA_INSN_STHIQ, SH64_MEDIA_SFMT_STHIL },
+ { SH_INSN_STLOL, SH64_MEDIA_INSN_STLOL, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_STLOQ, SH64_MEDIA_INSN_STLOQ, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_STXB, SH64_MEDIA_INSN_STXB, SH64_MEDIA_SFMT_STXB },
+ { SH_INSN_STXL, SH64_MEDIA_INSN_STXL, SH64_MEDIA_SFMT_STXB },
+ { SH_INSN_STXQ, SH64_MEDIA_INSN_STXQ, SH64_MEDIA_SFMT_STXB },
+ { SH_INSN_STXW, SH64_MEDIA_INSN_STXW, SH64_MEDIA_SFMT_STXB },
+ { SH_INSN_SUB, SH64_MEDIA_INSN_SUB, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_SUBL, SH64_MEDIA_INSN_SUBL, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_SWAPQ, SH64_MEDIA_INSN_SWAPQ, SH64_MEDIA_SFMT_SWAPQ },
+ { SH_INSN_SYNCI, SH64_MEDIA_INSN_SYNCI, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_SYNCO, SH64_MEDIA_INSN_SYNCO, SH64_MEDIA_SFMT_ALLOCO },
+ { SH_INSN_TRAPA, SH64_MEDIA_INSN_TRAPA, SH64_MEDIA_SFMT_TRAPA },
+ { SH_INSN_XOR, SH64_MEDIA_INSN_XOR, SH64_MEDIA_SFMT_ADD },
+ { SH_INSN_XORI, SH64_MEDIA_INSN_XORI, SH64_MEDIA_SFMT_XORI },
+};
+
+static const struct insn_sem sh64_media_insn_sem_invalid = {
+ VIRTUAL_INSN_X_INVALID, SH64_MEDIA_INSN_X_INVALID, SH64_MEDIA_SFMT_EMPTY
+};
+
+/* Initialize an IDESC from the compile-time computable parts. */
+
+static INLINE void
+init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
+{
+ const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
+
+ id->num = t->index;
+ id->sfmt = t->sfmt;
+ if ((int) t->type <= 0)
+ id->idata = & cgen_virtual_insn_table[- (int) t->type];
+ else
+ id->idata = & insn_table[t->type];
+ id->attrs = CGEN_INSN_ATTRS (id->idata);
+ /* Oh my god, a magic number. */
+ id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
+
+#if WITH_PROFILE_MODEL_P
+ id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
+ {
+ SIM_DESC sd = CPU_STATE (cpu);
+ SIM_ASSERT (t->index == id->timing->num);
+ }
+#endif
+
+ /* Semantic pointers are initialized elsewhere. */
+}
+
+/* Initialize the instruction descriptor table. */
+
+void
+sh64_media_init_idesc_table (SIM_CPU *cpu)
+{
+ IDESC *id,*tabend;
+ const struct insn_sem *t,*tend;
+ int tabsize = SH64_MEDIA_INSN_MAX;
+ IDESC *table = sh64_media_insn_data;
+
+ memset (table, 0, tabsize * sizeof (IDESC));
+
+ /* First set all entries to the `invalid insn'. */
+ t = & sh64_media_insn_sem_invalid;
+ for (id = table, tabend = table + tabsize; id < tabend; ++id)
+ init_idesc (cpu, id, t);
+
+ /* Now fill in the values for the chosen cpu. */
+ for (t = sh64_media_insn_sem, tend = t + sizeof (sh64_media_insn_sem) / sizeof (*t);
+ t != tend; ++t)
+ {
+ init_idesc (cpu, & table[t->index], t);
+ }
+
+ /* Link the IDESC table into the cpu. */
+ CPU_IDESC (cpu) = table;
+}
+
+/* Given an instruction, return a pointer to its IDESC entry. */
+
+const IDESC *
+sh64_media_decode (SIM_CPU *current_cpu, IADDR pc,
+ CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
+ ARGBUF *abuf)
+{
+ /* Result of decoder. */
+ SH64_MEDIA_INSN_TYPE itype;
+
+ {
+ CGEN_INSN_INT insn = base_insn;
+
+ {
+ unsigned int val = (((insn >> 22) & (63 << 4)) | ((insn >> 16) & (15 << 0)));
+ switch (val)
+ {
+ case 1 : itype = SH64_MEDIA_INSN_CMPEQ; goto extract_sfmt_add; case 3 : itype = SH64_MEDIA_INSN_CMPGT; goto extract_sfmt_add; case 7 : itype = SH64_MEDIA_INSN_CMPGTU; goto extract_sfmt_add; case 8 : itype = SH64_MEDIA_INSN_ADDL; goto extract_sfmt_add; case 9 : itype = SH64_MEDIA_INSN_ADD; goto extract_sfmt_add; case 10 : itype = SH64_MEDIA_INSN_SUBL; goto extract_sfmt_add; case 11 : itype = SH64_MEDIA_INSN_SUB; goto extract_sfmt_add; case 12 : itype = SH64_MEDIA_INSN_ADDZL; goto extract_sfmt_add; case 13 : itype = SH64_MEDIA_INSN_NSB; goto extract_sfmt_byterev; case 14 : itype = SH64_MEDIA_INSN_MULUL; goto extract_sfmt_add; case 15 : itype = SH64_MEDIA_INSN_BYTEREV; goto extract_sfmt_byterev; case 16 : itype = SH64_MEDIA_INSN_SHLLDL; goto extract_sfmt_add; case 17 : itype = SH64_MEDIA_INSN_SHLLD; goto extract_sfmt_add; case 18 : itype = SH64_MEDIA_INSN_SHLRDL; goto extract_sfmt_add; case 19 : itype = SH64_MEDIA_INSN_SHLRD; goto extract_sfmt_add; case 22 : itype = SH64_MEDIA_INSN_SHARDL; goto extract_sfmt_add; case 23 : itype = SH64_MEDIA_INSN_SHARD; goto extract_sfmt_add; case 25 : itype = SH64_MEDIA_INSN_OR; goto extract_sfmt_add; case 27 : itype = SH64_MEDIA_INSN_AND; goto extract_sfmt_add; case 29 : itype = SH64_MEDIA_INSN_XOR; goto extract_sfmt_add; case 30 : itype = SH64_MEDIA_INSN_MULSL; goto extract_sfmt_add; case 31 : itype = SH64_MEDIA_INSN_ANDC; goto extract_sfmt_add; case 33 : itype = SH64_MEDIA_INSN_MADDW; goto extract_sfmt_add; case 34 : itype = SH64_MEDIA_INSN_MADDL; goto extract_sfmt_add; case 36 : itype = SH64_MEDIA_INSN_MADDSUB; goto extract_sfmt_add; case 37 : itype = SH64_MEDIA_INSN_MADDSW; goto extract_sfmt_add; case 38 : itype = SH64_MEDIA_INSN_MADDSL; goto extract_sfmt_add; case 41 : itype = SH64_MEDIA_INSN_MSUBW; goto extract_sfmt_add; case 42 : itype = SH64_MEDIA_INSN_MSUBL; goto extract_sfmt_add; case 44 : itype = SH64_MEDIA_INSN_MSUBSUB; goto extract_sfmt_add; case 45 : itype = SH64_MEDIA_INSN_MSUBSW; goto extract_sfmt_add; case 46 : itype = SH64_MEDIA_INSN_MSUBSL; goto extract_sfmt_add; case 49 : itype = SH64_MEDIA_INSN_MSHLLDW; goto extract_sfmt_add; case 50 : itype = SH64_MEDIA_INSN_MSHLLDL; goto extract_sfmt_add; case 53 : itype = SH64_MEDIA_INSN_MSHALDSW; goto extract_sfmt_add; case 54 : itype = SH64_MEDIA_INSN_MSHALDSL; goto extract_sfmt_add; case 57 : itype = SH64_MEDIA_INSN_MSHARDW; goto extract_sfmt_add; case 58 : itype = SH64_MEDIA_INSN_MSHARDL; goto extract_sfmt_add; case 59 : itype = SH64_MEDIA_INSN_MSHARDSQ; goto extract_sfmt_add; case 61 : itype = SH64_MEDIA_INSN_MSHLRDW; goto extract_sfmt_add; case 62 : itype = SH64_MEDIA_INSN_MSHLRDL; goto extract_sfmt_add; case 86 : itype = SH64_MEDIA_INSN_FIPRS; goto extract_sfmt_fiprs; case 94 : itype = SH64_MEDIA_INSN_FTRVS; goto extract_sfmt_ftrvs; case 96 : itype = SH64_MEDIA_INSN_FABSS; goto extract_sfmt_fabss; case 97 : itype = SH64_MEDIA_INSN_FABSD; goto extract_sfmt_fabsd; case 98 : itype = SH64_MEDIA_INSN_FNEGS; goto extract_sfmt_fabss; case 99 : itype = SH64_MEDIA_INSN_FNEGD; goto extract_sfmt_fabsd; case 112 : itype = SH64_MEDIA_INSN_FMOVLS; goto extract_sfmt_fmovls; case 113 : itype = SH64_MEDIA_INSN_FMOVQD; goto extract_sfmt_fmovqd; case 114 : itype = SH64_MEDIA_INSN_FGETSCR; goto extract_sfmt_alloco; case 120 : itype = SH64_MEDIA_INSN_FLDXS; goto extract_sfmt_fldxs; case 121 : itype = SH64_MEDIA_INSN_FLDXD; goto extract_sfmt_fldxd; case 125 : itype = SH64_MEDIA_INSN_FLDXP; goto extract_sfmt_fldxp; case 129 : itype = SH64_MEDIA_INSN_CMVEQ; goto extract_sfmt_cmveq; case 131 : itype = SH64_MEDIA_INSN_SWAPQ; goto extract_sfmt_swapq; case 133 : itype = SH64_MEDIA_INSN_CMVNE; goto extract_sfmt_cmveq; case 159 : itype = SH64_MEDIA_INSN_GETCON; goto extract_sfmt_getcon; case 160 : itype = SH64_MEDIA_INSN_MCMPEQB; goto extract_sfmt_add; case 161 : itype = SH64_MEDIA_INSN_MCMPEQW; goto extract_sfmt_add; case 162 : itype = SH64_MEDIA_INSN_MCMPEQL; goto extract_sfmt_add; case 164 : itype = SH64_MEDIA_INSN_MCMPGTUB; goto extract_sfmt_add; case 165 : itype = SH64_MEDIA_INSN_MCMPGTW; goto extract_sfmt_add; case 166 : itype = SH64_MEDIA_INSN_MCMPGTL; goto extract_sfmt_add; case 167 : itype = SH64_MEDIA_INSN_MEXTR1; goto extract_sfmt_add; case 169 : itype = SH64_MEDIA_INSN_MABSW; goto extract_sfmt_byterev; case 170 : itype = SH64_MEDIA_INSN_MABSL; goto extract_sfmt_byterev; case 171 : itype = SH64_MEDIA_INSN_MEXTR2; goto extract_sfmt_add; case 173 : itype = SH64_MEDIA_INSN_MPERMW; goto extract_sfmt_mpermw; case 175 : itype = SH64_MEDIA_INSN_MEXTR3; goto extract_sfmt_add; case 176 : itype = SH64_MEDIA_INSN_MSHFLOB; goto extract_sfmt_add; case 177 : itype = SH64_MEDIA_INSN_MSHFLOW; goto extract_sfmt_add; case 178 : itype = SH64_MEDIA_INSN_MSHFLOL; goto extract_sfmt_add; case 179 : itype = SH64_MEDIA_INSN_MEXTR4; goto extract_sfmt_add; case 180 : itype = SH64_MEDIA_INSN_MSHFHIB; goto extract_sfmt_add; case 181 : itype = SH64_MEDIA_INSN_MSHFHIW; goto extract_sfmt_add; case 182 : itype = SH64_MEDIA_INSN_MSHFHIL; goto extract_sfmt_add; case 183 : itype = SH64_MEDIA_INSN_MEXTR5; goto extract_sfmt_add; case 187 : itype = SH64_MEDIA_INSN_MEXTR6; goto extract_sfmt_add; case 191 : itype = SH64_MEDIA_INSN_MEXTR7; goto extract_sfmt_add; case 192 : itype = SH64_MEDIA_INSN_FMOVSL; goto extract_sfmt_fmovsl; case 193 : itype = SH64_MEDIA_INSN_FMOVDQ; goto extract_sfmt_fmovdq; case 194 : itype = SH64_MEDIA_INSN_FPUTSCR; goto extract_sfmt_alloco; case 200 : itype = SH64_MEDIA_INSN_FCMPEQS; goto extract_sfmt_fcmpeqs; case 201 : itype = SH64_MEDIA_INSN_FCMPEQD; goto extract_sfmt_fcmpeqd; case 202 : itype = SH64_MEDIA_INSN_FCMPUNS; goto extract_sfmt_fcmpeqs; case 203 : itype = SH64_MEDIA_INSN_FCMPUND; goto extract_sfmt_fcmpeqd; case 204 : itype = SH64_MEDIA_INSN_FCMPGTS; goto extract_sfmt_fcmpeqs; case 205 : itype = SH64_MEDIA_INSN_FCMPGTD; goto extract_sfmt_fcmpeqd; case 206 : itype = SH64_MEDIA_INSN_FCMPGES; goto extract_sfmt_fcmpeqs; case 207 : itype = SH64_MEDIA_INSN_FCMPGED; goto extract_sfmt_fcmpeqd; case 208 : itype = SH64_MEDIA_INSN_FADDS; goto extract_sfmt_fadds; case 209 : itype = SH64_MEDIA_INSN_FADDD; goto extract_sfmt_faddd; case 210 : itype = SH64_MEDIA_INSN_FSUBS; goto extract_sfmt_fadds; case 211 : itype = SH64_MEDIA_INSN_FSUBD; goto extract_sfmt_faddd; case 212 : itype = SH64_MEDIA_INSN_FDIVS; goto extract_sfmt_fadds; case 213 : itype = SH64_MEDIA_INSN_FDIVD; goto extract_sfmt_faddd; case 214 : itype = SH64_MEDIA_INSN_FMULS; goto extract_sfmt_fadds; case 215 : itype = SH64_MEDIA_INSN_FMULD; goto extract_sfmt_faddd; case 222 : itype = SH64_MEDIA_INSN_FMACS; goto extract_sfmt_fmacs; case 224 : itype = SH64_MEDIA_INSN_FMOVS; goto extract_sfmt_fabss; case 225 : itype = SH64_MEDIA_INSN_FMOVD; goto extract_sfmt_fabsd; case 228 : itype = SH64_MEDIA_INSN_FSQRTS; goto extract_sfmt_fabss; case 229 : itype = SH64_MEDIA_INSN_FSQRTD; goto extract_sfmt_fabsd; case 230 : itype = SH64_MEDIA_INSN_FCNVSD; goto extract_sfmt_fcnvsd; case 231 : itype = SH64_MEDIA_INSN_FCNVDS; goto extract_sfmt_fcnvds; case 232 : itype = SH64_MEDIA_INSN_FTRCSL; goto extract_sfmt_fabss; case 233 : itype = SH64_MEDIA_INSN_FTRCDQ; goto extract_sfmt_fabsd; case 234 : itype = SH64_MEDIA_INSN_FTRCSQ; goto extract_sfmt_fcnvsd; case 235 : itype = SH64_MEDIA_INSN_FTRCDL; goto extract_sfmt_fcnvds; case 236 : itype = SH64_MEDIA_INSN_FLOATLS; goto extract_sfmt_fabss; case 237 : itype = SH64_MEDIA_INSN_FLOATQD; goto extract_sfmt_fabsd; case 238 : itype = SH64_MEDIA_INSN_FLOATLD; goto extract_sfmt_fcnvsd; case 239 : itype = SH64_MEDIA_INSN_FLOATQS; goto extract_sfmt_fcnvds; case 248 : itype = SH64_MEDIA_INSN_FSTXS; goto extract_sfmt_fstxs; case 249 : itype = SH64_MEDIA_INSN_FSTXD; goto extract_sfmt_fstxd; case 253 : itype = SH64_MEDIA_INSN_FSTXP; goto extract_sfmt_fstxp; case 256 : itype = SH64_MEDIA_INSN_LDXB; goto extract_sfmt_ldxb; case 257 : itype = SH64_MEDIA_INSN_LDXW; goto extract_sfmt_ldxb; case 258 : itype = SH64_MEDIA_INSN_LDXL; goto extract_sfmt_ldxb; case 259 : itype = SH64_MEDIA_INSN_LDXQ; goto extract_sfmt_ldxb; case 260 : itype = SH64_MEDIA_INSN_LDXUB; goto extract_sfmt_ldxb; case 261 : itype = SH64_MEDIA_INSN_LDXUW; goto extract_sfmt_ldxb; case 273 : itype = SH64_MEDIA_INSN_BLINK; goto extract_sfmt_blink; case 277 : itype = SH64_MEDIA_INSN_GETTR; goto extract_sfmt_gettr; case 288 : itype = SH64_MEDIA_INSN_MSADUBQ; goto extract_sfmt_mcmv; case 289 : itype = SH64_MEDIA_INSN_MMACFXWL; goto extract_sfmt_mcmv; case 291 : itype = SH64_MEDIA_INSN_MCMV; goto extract_sfmt_mcmv; case 293 : itype = SH64_MEDIA_INSN_MMACNFX_WL; goto extract_sfmt_mcmv; case 297 : itype = SH64_MEDIA_INSN_MMULSUMWQ; goto extract_sfmt_mcmv; case 305 : itype = SH64_MEDIA_INSN_MMULW; goto extract_sfmt_add; case 306 : itype = SH64_MEDIA_INSN_MMULL; goto extract_sfmt_add; case 309 : itype = SH64_MEDIA_INSN_MMULFXW; goto extract_sfmt_add; case 310 : itype = SH64_MEDIA_INSN_MMULFXL; goto extract_sfmt_add; case 312 : itype = SH64_MEDIA_INSN_MCNVSWB; goto extract_sfmt_add; case 313 : itype = SH64_MEDIA_INSN_MMULFXRPW; goto extract_sfmt_add; case 314 : itype = SH64_MEDIA_INSN_MMULLOWL; goto extract_sfmt_add; case 316 : itype = SH64_MEDIA_INSN_MCNVSWUB; goto extract_sfmt_add; case 317 : itype = SH64_MEDIA_INSN_MCNVSLW; goto extract_sfmt_add; case 318 : itype = SH64_MEDIA_INSN_MMULHIWL; goto extract_sfmt_add; case 384 : itype = SH64_MEDIA_INSN_STXB; goto extract_sfmt_stxb; case 385 : itype = SH64_MEDIA_INSN_STXW; goto extract_sfmt_stxb; case 386 : itype = SH64_MEDIA_INSN_STXL; goto extract_sfmt_stxb; case 387 : itype = SH64_MEDIA_INSN_STXQ; goto extract_sfmt_stxb; case 401 : itype = SH64_MEDIA_INSN_BEQ; goto extract_sfmt_beq; case 403 : itype = SH64_MEDIA_INSN_BGE; goto extract_sfmt_beq; case 405 : itype = SH64_MEDIA_INSN_BNE; goto extract_sfmt_beq; case 407 : itype = SH64_MEDIA_INSN_BGT; goto extract_sfmt_beq; case 411 : itype = SH64_MEDIA_INSN_BGEU; goto extract_sfmt_beq; case 415 : itype = SH64_MEDIA_INSN_BGTU; goto extract_sfmt_beq; case 417 : itype = SH64_MEDIA_INSN_PTABS; goto extract_sfmt_ptabs; case 421 : itype = SH64_MEDIA_INSN_PTREL; goto extract_sfmt_ptrel; case 432 : itype = SH64_MEDIA_INSN_NOP; goto extract_sfmt_alloco; case 433 : itype = SH64_MEDIA_INSN_TRAPA; goto extract_sfmt_trapa; case 434 : itype = SH64_MEDIA_INSN_SYNCI; goto extract_sfmt_alloco; case 435 : itype = SH64_MEDIA_INSN_RTE; goto extract_sfmt_alloco; case 437 : itype = SH64_MEDIA_INSN_BRK; goto extract_sfmt_brk; case 438 : itype = SH64_MEDIA_INSN_SYNCO; goto extract_sfmt_alloco; case 439 : itype = SH64_MEDIA_INSN_SLEEP; goto extract_sfmt_alloco; case 447 : itype = SH64_MEDIA_INSN_PUTCON; goto extract_sfmt_putcon; case 512 : /* fall through */
+ case 513 : /* fall through */
+ case 514 : /* fall through */
+ case 515 : /* fall through */
+ case 516 : /* fall through */
+ case 517 : /* fall through */
+ case 518 : /* fall through */
+ case 519 : /* fall through */
+ case 520 : /* fall through */
+ case 521 : /* fall through */
+ case 522 : /* fall through */
+ case 523 : /* fall through */
+ case 524 : /* fall through */
+ case 525 : /* fall through */
+ case 526 : /* fall through */
+ case 527 : itype = SH64_MEDIA_INSN_LDB; goto extract_sfmt_ldb; case 528 : /* fall through */
+ case 529 : /* fall through */
+ case 530 : /* fall through */
+ case 531 : /* fall through */
+ case 532 : /* fall through */
+ case 533 : /* fall through */
+ case 534 : /* fall through */
+ case 535 : /* fall through */
+ case 536 : /* fall through */
+ case 537 : /* fall through */
+ case 538 : /* fall through */
+ case 539 : /* fall through */
+ case 540 : /* fall through */
+ case 541 : /* fall through */
+ case 542 : /* fall through */
+ case 543 : itype = SH64_MEDIA_INSN_LDW; goto extract_sfmt_lduw; case 544 : /* fall through */
+ case 545 : /* fall through */
+ case 546 : /* fall through */
+ case 547 : /* fall through */
+ case 548 : /* fall through */
+ case 549 : /* fall through */
+ case 550 : /* fall through */
+ case 551 : /* fall through */
+ case 552 : /* fall through */
+ case 553 : /* fall through */
+ case 554 : /* fall through */
+ case 555 : /* fall through */
+ case 556 : /* fall through */
+ case 557 : /* fall through */
+ case 558 : /* fall through */
+ case 559 : itype = SH64_MEDIA_INSN_LDL; goto extract_sfmt_ldl; case 560 : /* fall through */
+ case 561 : /* fall through */
+ case 562 : /* fall through */
+ case 563 : /* fall through */
+ case 564 : /* fall through */
+ case 565 : /* fall through */
+ case 566 : /* fall through */
+ case 567 : /* fall through */
+ case 568 : /* fall through */
+ case 569 : /* fall through */
+ case 570 : /* fall through */
+ case 571 : /* fall through */
+ case 572 : /* fall through */
+ case 573 : /* fall through */
+ case 574 : /* fall through */
+ case 575 : itype = SH64_MEDIA_INSN_LDQ; goto extract_sfmt_ldq; case 576 : /* fall through */
+ case 577 : /* fall through */
+ case 578 : /* fall through */
+ case 579 : /* fall through */
+ case 580 : /* fall through */
+ case 581 : /* fall through */
+ case 582 : /* fall through */
+ case 583 : /* fall through */
+ case 584 : /* fall through */
+ case 585 : /* fall through */
+ case 586 : /* fall through */
+ case 587 : /* fall through */
+ case 588 : /* fall through */
+ case 589 : /* fall through */
+ case 590 : /* fall through */
+ case 591 : itype = SH64_MEDIA_INSN_LDUB; goto extract_sfmt_ldb; case 592 : /* fall through */
+ case 593 : /* fall through */
+ case 594 : /* fall through */
+ case 595 : /* fall through */
+ case 596 : /* fall through */
+ case 597 : /* fall through */
+ case 598 : /* fall through */
+ case 599 : /* fall through */
+ case 600 : /* fall through */
+ case 601 : /* fall through */
+ case 602 : /* fall through */
+ case 603 : /* fall through */
+ case 604 : /* fall through */
+ case 605 : /* fall through */
+ case 606 : /* fall through */
+ case 607 : itype = SH64_MEDIA_INSN_FLDS; goto extract_sfmt_flds; case 608 : /* fall through */
+ case 609 : /* fall through */
+ case 610 : /* fall through */
+ case 611 : /* fall through */
+ case 612 : /* fall through */
+ case 613 : /* fall through */
+ case 614 : /* fall through */
+ case 615 : /* fall through */
+ case 616 : /* fall through */
+ case 617 : /* fall through */
+ case 618 : /* fall through */
+ case 619 : /* fall through */
+ case 620 : /* fall through */
+ case 621 : /* fall through */
+ case 622 : /* fall through */
+ case 623 : itype = SH64_MEDIA_INSN_FLDP; goto extract_sfmt_fldp; case 624 : /* fall through */
+ case 625 : /* fall through */
+ case 626 : /* fall through */
+ case 627 : /* fall through */
+ case 628 : /* fall through */
+ case 629 : /* fall through */
+ case 630 : /* fall through */
+ case 631 : /* fall through */
+ case 632 : /* fall through */
+ case 633 : /* fall through */
+ case 634 : /* fall through */
+ case 635 : /* fall through */
+ case 636 : /* fall through */
+ case 637 : /* fall through */
+ case 638 : /* fall through */
+ case 639 : itype = SH64_MEDIA_INSN_FLDD; goto extract_sfmt_fldd; case 640 : /* fall through */
+ case 641 : /* fall through */
+ case 642 : /* fall through */
+ case 643 : /* fall through */
+ case 644 : /* fall through */
+ case 645 : /* fall through */
+ case 646 : /* fall through */
+ case 647 : /* fall through */
+ case 648 : /* fall through */
+ case 649 : /* fall through */
+ case 650 : /* fall through */
+ case 651 : /* fall through */
+ case 652 : /* fall through */
+ case 653 : /* fall through */
+ case 654 : /* fall through */
+ case 655 : itype = SH64_MEDIA_INSN_STB; goto extract_sfmt_stb; case 656 : /* fall through */
+ case 657 : /* fall through */
+ case 658 : /* fall through */
+ case 659 : /* fall through */
+ case 660 : /* fall through */
+ case 661 : /* fall through */
+ case 662 : /* fall through */
+ case 663 : /* fall through */
+ case 664 : /* fall through */
+ case 665 : /* fall through */
+ case 666 : /* fall through */
+ case 667 : /* fall through */
+ case 668 : /* fall through */
+ case 669 : /* fall through */
+ case 670 : /* fall through */
+ case 671 : itype = SH64_MEDIA_INSN_STW; goto extract_sfmt_stw; case 672 : /* fall through */
+ case 673 : /* fall through */
+ case 674 : /* fall through */
+ case 675 : /* fall through */
+ case 676 : /* fall through */
+ case 677 : /* fall through */
+ case 678 : /* fall through */
+ case 679 : /* fall through */
+ case 680 : /* fall through */
+ case 681 : /* fall through */
+ case 682 : /* fall through */
+ case 683 : /* fall through */
+ case 684 : /* fall through */
+ case 685 : /* fall through */
+ case 686 : /* fall through */
+ case 687 : itype = SH64_MEDIA_INSN_STL; goto extract_sfmt_stl; case 688 : /* fall through */
+ case 689 : /* fall through */
+ case 690 : /* fall through */
+ case 691 : /* fall through */
+ case 692 : /* fall through */
+ case 693 : /* fall through */
+ case 694 : /* fall through */
+ case 695 : /* fall through */
+ case 696 : /* fall through */
+ case 697 : /* fall through */
+ case 698 : /* fall through */
+ case 699 : /* fall through */
+ case 700 : /* fall through */
+ case 701 : /* fall through */
+ case 702 : /* fall through */
+ case 703 : itype = SH64_MEDIA_INSN_STQ; goto extract_sfmt_stq; case 704 : /* fall through */
+ case 705 : /* fall through */
+ case 706 : /* fall through */
+ case 707 : /* fall through */
+ case 708 : /* fall through */
+ case 709 : /* fall through */
+ case 710 : /* fall through */
+ case 711 : /* fall through */
+ case 712 : /* fall through */
+ case 713 : /* fall through */
+ case 714 : /* fall through */
+ case 715 : /* fall through */
+ case 716 : /* fall through */
+ case 717 : /* fall through */
+ case 718 : /* fall through */
+ case 719 : itype = SH64_MEDIA_INSN_LDUW; goto extract_sfmt_lduw; case 720 : /* fall through */
+ case 721 : /* fall through */
+ case 722 : /* fall through */
+ case 723 : /* fall through */
+ case 724 : /* fall through */
+ case 725 : /* fall through */
+ case 726 : /* fall through */
+ case 727 : /* fall through */
+ case 728 : /* fall through */
+ case 729 : /* fall through */
+ case 730 : /* fall through */
+ case 731 : /* fall through */
+ case 732 : /* fall through */
+ case 733 : /* fall through */
+ case 734 : /* fall through */
+ case 735 : itype = SH64_MEDIA_INSN_FSTS; goto extract_sfmt_fsts; case 736 : /* fall through */
+ case 737 : /* fall through */
+ case 738 : /* fall through */
+ case 739 : /* fall through */
+ case 740 : /* fall through */
+ case 741 : /* fall through */
+ case 742 : /* fall through */
+ case 743 : /* fall through */
+ case 744 : /* fall through */
+ case 745 : /* fall through */
+ case 746 : /* fall through */
+ case 747 : /* fall through */
+ case 748 : /* fall through */
+ case 749 : /* fall through */
+ case 750 : /* fall through */
+ case 751 : itype = SH64_MEDIA_INSN_FSTP; goto extract_sfmt_fstp; case 752 : /* fall through */
+ case 753 : /* fall through */
+ case 754 : /* fall through */
+ case 755 : /* fall through */
+ case 756 : /* fall through */
+ case 757 : /* fall through */
+ case 758 : /* fall through */
+ case 759 : /* fall through */
+ case 760 : /* fall through */
+ case 761 : /* fall through */
+ case 762 : /* fall through */
+ case 763 : /* fall through */
+ case 764 : /* fall through */
+ case 765 : /* fall through */
+ case 766 : /* fall through */
+ case 767 : itype = SH64_MEDIA_INSN_FSTD; goto extract_sfmt_fstd; case 770 : itype = SH64_MEDIA_INSN_LDLOL; goto extract_sfmt_alloco; case 771 : itype = SH64_MEDIA_INSN_LDLOQ; goto extract_sfmt_alloco; case 774 : itype = SH64_MEDIA_INSN_LDHIL; goto extract_sfmt_alloco; case 775 : itype = SH64_MEDIA_INSN_LDHIQ; goto extract_sfmt_alloco; case 783 : itype = SH64_MEDIA_INSN_GETCFG; goto extract_sfmt_alloco; case 784 : itype = SH64_MEDIA_INSN_SHLLIL; goto extract_sfmt_sharil; case 785 : itype = SH64_MEDIA_INSN_SHLLI; goto extract_sfmt_shari; case 786 : itype = SH64_MEDIA_INSN_SHLRIL; goto extract_sfmt_sharil; case 787 : itype = SH64_MEDIA_INSN_SHLRI; goto extract_sfmt_shari; case 790 : itype = SH64_MEDIA_INSN_SHARIL; goto extract_sfmt_sharil; case 791 : itype = SH64_MEDIA_INSN_SHARI; goto extract_sfmt_shari; case 797 : itype = SH64_MEDIA_INSN_XORI; goto extract_sfmt_xori; case 800 : /* fall through */
+ case 801 : /* fall through */
+ case 802 : /* fall through */
+ case 803 : /* fall through */
+ case 804 : /* fall through */
+ case 805 : /* fall through */
+ case 806 : /* fall through */
+ case 807 : /* fall through */
+ case 808 : /* fall through */
+ case 809 : /* fall through */
+ case 810 : /* fall through */
+ case 811 : /* fall through */
+ case 812 : /* fall through */
+ case 813 : /* fall through */
+ case 814 : /* fall through */
+ case 815 : itype = SH64_MEDIA_INSN_SHORI; goto extract_sfmt_shori; case 816 : /* fall through */
+ case 817 : /* fall through */
+ case 818 : /* fall through */
+ case 819 : /* fall through */
+ case 820 : /* fall through */
+ case 821 : /* fall through */
+ case 822 : /* fall through */
+ case 823 : /* fall through */
+ case 824 : /* fall through */
+ case 825 : /* fall through */
+ case 826 : /* fall through */
+ case 827 : /* fall through */
+ case 828 : /* fall through */
+ case 829 : /* fall through */
+ case 830 : /* fall through */
+ case 831 : itype = SH64_MEDIA_INSN_MOVI; goto extract_sfmt_movi; case 832 : /* fall through */
+ case 833 : /* fall through */
+ case 834 : /* fall through */
+ case 835 : /* fall through */
+ case 836 : /* fall through */
+ case 837 : /* fall through */
+ case 838 : /* fall through */
+ case 839 : /* fall through */
+ case 840 : /* fall through */
+ case 841 : /* fall through */
+ case 842 : /* fall through */
+ case 843 : /* fall through */
+ case 844 : /* fall through */
+ case 845 : /* fall through */
+ case 846 : /* fall through */
+ case 847 : itype = SH64_MEDIA_INSN_ADDI; goto extract_sfmt_addi; case 848 : /* fall through */
+ case 849 : /* fall through */
+ case 850 : /* fall through */
+ case 851 : /* fall through */
+ case 852 : /* fall through */
+ case 853 : /* fall through */
+ case 854 : /* fall through */
+ case 855 : /* fall through */
+ case 856 : /* fall through */
+ case 857 : /* fall through */
+ case 858 : /* fall through */
+ case 859 : /* fall through */
+ case 860 : /* fall through */
+ case 861 : /* fall through */
+ case 862 : /* fall through */
+ case 863 : itype = SH64_MEDIA_INSN_ADDIL; goto extract_sfmt_addi; case 864 : /* fall through */
+ case 865 : /* fall through */
+ case 866 : /* fall through */
+ case 867 : /* fall through */
+ case 868 : /* fall through */
+ case 869 : /* fall through */
+ case 870 : /* fall through */
+ case 871 : /* fall through */
+ case 872 : /* fall through */
+ case 873 : /* fall through */
+ case 874 : /* fall through */
+ case 875 : /* fall through */
+ case 876 : /* fall through */
+ case 877 : /* fall through */
+ case 878 : /* fall through */
+ case 879 : itype = SH64_MEDIA_INSN_ANDI; goto extract_sfmt_addi; case 880 : /* fall through */
+ case 881 : /* fall through */
+ case 882 : /* fall through */
+ case 883 : /* fall through */
+ case 884 : /* fall through */
+ case 885 : /* fall through */
+ case 886 : /* fall through */
+ case 887 : /* fall through */
+ case 888 : /* fall through */
+ case 889 : /* fall through */
+ case 890 : /* fall through */
+ case 891 : /* fall through */
+ case 892 : /* fall through */
+ case 893 : /* fall through */
+ case 894 : /* fall through */
+ case 895 : itype = SH64_MEDIA_INSN_ORI; goto extract_sfmt_ori; case 897 : itype = SH64_MEDIA_INSN_PREFI; goto extract_sfmt_alloco; case 898 : itype = SH64_MEDIA_INSN_STLOL; goto extract_sfmt_alloco; case 899 : itype = SH64_MEDIA_INSN_STLOQ; goto extract_sfmt_alloco; case 900 : itype = SH64_MEDIA_INSN_ALLOCO; goto extract_sfmt_alloco; case 901 : itype = SH64_MEDIA_INSN_ICBI; goto extract_sfmt_alloco; case 902 : itype = SH64_MEDIA_INSN_STHIL; goto extract_sfmt_sthil; case 903 : itype = SH64_MEDIA_INSN_STHIQ; goto extract_sfmt_sthil; case 904 : itype = SH64_MEDIA_INSN_OCBP; goto extract_sfmt_alloco; case 905 : itype = SH64_MEDIA_INSN_OCBI; goto extract_sfmt_alloco; case 908 : itype = SH64_MEDIA_INSN_OCBWB; goto extract_sfmt_alloco; case 911 : itype = SH64_MEDIA_INSN_PUTCFG; goto extract_sfmt_alloco; case 913 : itype = SH64_MEDIA_INSN_BEQI; goto extract_sfmt_beqi; case 917 : itype = SH64_MEDIA_INSN_BNEI; goto extract_sfmt_beqi; case 928 : /* fall through */
+ case 929 : /* fall through */
+ case 930 : /* fall through */
+ case 931 : /* fall through */
+ case 932 : /* fall through */
+ case 933 : /* fall through */
+ case 934 : /* fall through */
+ case 935 : /* fall through */
+ case 936 : /* fall through */
+ case 937 : /* fall through */
+ case 938 : /* fall through */
+ case 939 : /* fall through */
+ case 940 : /* fall through */
+ case 941 : /* fall through */
+ case 942 : /* fall through */
+ case 943 : itype = SH64_MEDIA_INSN_PTA; goto extract_sfmt_pta; case 944 : /* fall through */
+ case 945 : /* fall through */
+ case 946 : /* fall through */
+ case 947 : /* fall through */
+ case 948 : /* fall through */
+ case 949 : /* fall through */
+ case 950 : /* fall through */
+ case 951 : /* fall through */
+ case 952 : /* fall through */
+ case 953 : /* fall through */
+ case 954 : /* fall through */
+ case 955 : /* fall through */
+ case 956 : /* fall through */
+ case 957 : /* fall through */
+ case 958 : /* fall through */
+ case 959 : itype = SH64_MEDIA_INSN_PTB; goto extract_sfmt_pta; default : itype = SH64_MEDIA_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
+ }
+
+ /* The instruction has been decoded, now extract the fields. */
+
+ extract_sfmt_empty:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_add:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_addi:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi.f
+ UINT f_left;
+ INT f_disp10;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_disp10 = EXTRACT_LSB0_INT (insn, 32, 19, 10);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp10) = f_disp10;
+ FLD (f_left) = f_left;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_disp10 0x%x", 'x', f_disp10, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_alloco:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_alloco", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_beq:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_beq.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_tra;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ FLD (f_tra) = f_tra;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_tra 0x%x", 'x', f_tra, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_beqi:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_beqi.f
+ UINT f_left;
+ INT f_imm6;
+ UINT f_tra;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_imm6 = EXTRACT_LSB0_INT (insn, 32, 15, 6);
+ f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm6) = f_imm6;
+ FLD (f_left) = f_left;
+ FLD (f_tra) = f_tra;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqi", "f_imm6 0x%x", 'x', f_imm6, "f_left 0x%x", 'x', f_left, "f_tra 0x%x", 'x', f_tra, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_blink:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_blink.f
+ UINT f_trb;
+ UINT f_dest;
+
+ f_trb = EXTRACT_LSB0_UINT (insn, 32, 22, 3);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_trb) = f_trb;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_blink", "f_trb 0x%x", 'x', f_trb, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_brk:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_brk", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_byterev:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_xori.f
+ UINT f_left;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_byterev", "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_cmveq:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmveq", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fabsd:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+ UINT f_left_right;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+ f_left_right = f_left;
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left_right) = f_left_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fabsd", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fabss:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+ UINT f_left_right;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+ f_left_right = f_left;
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left_right) = f_left_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fabss", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_faddd:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_faddd", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fadds:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fadds", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fcmpeqd:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcmpeqd", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fcmpeqs:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcmpeqs", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fcnvds:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+ UINT f_left_right;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+ f_left_right = f_left;
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left_right) = f_left_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcnvds", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fcnvsd:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+ UINT f_left_right;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+ f_left_right = f_left;
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left_right) = f_left_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fcnvsd", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fiprs:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fiprs", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fldd:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ UINT f_left;
+ SI f_disp10x8;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3));
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp10x8) = f_disp10x8;
+ FLD (f_left) = f_left;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldd", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fldp:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ UINT f_left;
+ SI f_disp10x8;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3));
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp10x8) = f_disp10x8;
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldp", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_flds:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_flds.f
+ UINT f_left;
+ SI f_disp10x4;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2));
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp10x4) = f_disp10x4;
+ FLD (f_left) = f_left;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_flds", "f_disp10x4 0x%x", 'x', f_disp10x4, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fldxd:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldxd", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fldxp:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldxp", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fldxs:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fldxs", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fmacs:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmacs", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fmovdq:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+ UINT f_left_right;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+ f_left_right = f_left;
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left_right) = f_left_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmovdq", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fmovls:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_xori.f
+ UINT f_left;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmovls", "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fmovqd:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_xori.f
+ UINT f_left;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmovqd", "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fmovsl:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+ UINT f_left_right;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+ f_left_right = f_left;
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left_right) = f_left_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fmovsl", "f_left_right 0x%x", 'x', f_left_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fstd:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ UINT f_left;
+ SI f_disp10x8;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3));
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp10x8) = f_disp10x8;
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstd", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fstp:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ UINT f_left;
+ SI f_disp10x8;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3));
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp10x8) = f_disp10x8;
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstp", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fsts:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_flds.f
+ UINT f_left;
+ SI f_disp10x4;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2));
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp10x4) = f_disp10x4;
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fsts", "f_disp10x4 0x%x", 'x', f_disp10x4, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fstxd:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstxd", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fstxp:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstxp", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_fstxs:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_fstxs", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ftrvs:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ftrvs", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_getcon:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_xori.f
+ UINT f_left;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_getcon", "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_gettr:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_blink.f
+ UINT f_trb;
+ UINT f_dest;
+
+ f_trb = EXTRACT_LSB0_UINT (insn, 32, 22, 3);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_trb) = f_trb;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_gettr", "f_trb 0x%x", 'x', f_trb, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldb:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi.f
+ UINT f_left;
+ INT f_disp10;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_disp10 = EXTRACT_LSB0_INT (insn, 32, 19, 10);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp10) = f_disp10;
+ FLD (f_left) = f_left;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_disp10 0x%x", 'x', f_disp10, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldl:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_flds.f
+ UINT f_left;
+ SI f_disp10x4;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2));
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp10x4) = f_disp10x4;
+ FLD (f_left) = f_left;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldl", "f_disp10x4 0x%x", 'x', f_disp10x4, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldq:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ UINT f_left;
+ SI f_disp10x8;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3));
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp10x8) = f_disp10x8;
+ FLD (f_left) = f_left;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldq", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_lduw:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lduw.f
+ UINT f_left;
+ SI f_disp10x2;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_disp10x2 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (1));
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp10x2) = f_disp10x2;
+ FLD (f_left) = f_left;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lduw", "f_disp10x2 0x%x", 'x', f_disp10x2, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ldxb:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldxb", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mcmv:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mcmv", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_movi:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_movi.f
+ INT f_imm16;
+ UINT f_dest;
+
+ f_imm16 = EXTRACT_LSB0_INT (insn, 32, 25, 16);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm16) = f_imm16;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_movi", "f_imm16 0x%x", 'x', f_imm16, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_mpermw:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mpermw", "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ori:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_ori.f
+ UINT f_left;
+ INT f_imm10;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_imm10 = EXTRACT_LSB0_INT (insn, 32, 19, 10);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm10) = f_imm10;
+ FLD (f_left) = f_left;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ori", "f_imm10 0x%x", 'x', f_imm10, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_pta:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_pta.f
+ DI f_disp16;
+ UINT f_tra;
+
+ f_disp16 = ((((EXTRACT_LSB0_INT (insn, 32, 25, 16)) << (2))) + (pc));
+ f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp16) = f_disp16;
+ FLD (f_tra) = f_tra;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_pta", "f_disp16 0x%x", 'x', f_disp16, "f_tra 0x%x", 'x', f_tra, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ptabs:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_beq.f
+ UINT f_right;
+ UINT f_tra;
+
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_right) = f_right;
+ FLD (f_tra) = f_tra;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ptabs", "f_right 0x%x", 'x', f_right, "f_tra 0x%x", 'x', f_tra, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_ptrel:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_beq.f
+ UINT f_right;
+ UINT f_tra;
+
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_right) = f_right;
+ FLD (f_tra) = f_tra;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ptrel", "f_right 0x%x", 'x', f_right, "f_tra 0x%x", 'x', f_tra, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_putcon:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_xori.f
+ UINT f_left;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_putcon", "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_shari:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_shari.f
+ UINT f_left;
+ UINT f_uimm6;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_uimm6 = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_uimm6) = f_uimm6;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_shari", "f_left 0x%x", 'x', f_left, "f_uimm6 0x%x", 'x', f_uimm6, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sharil:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_shari.f
+ UINT f_left;
+ UINT f_uimm6;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_uimm6 = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ FLD (f_uimm6) = f_uimm6;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sharil", "f_left 0x%x", 'x', f_left, "f_uimm6 0x%x", 'x', f_uimm6, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_shori:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_shori.f
+ UINT f_uimm16;
+ UINT f_dest;
+
+ f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 25, 16);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dest) = f_dest;
+ FLD (f_uimm16) = f_uimm16;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_shori", "f_dest 0x%x", 'x', f_dest, "f_uimm16 0x%x", 'x', f_uimm16, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stb:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_addi.f
+ UINT f_left;
+ INT f_disp10;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_disp10 = EXTRACT_LSB0_INT (insn, 32, 19, 10);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp10) = f_disp10;
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_disp10 0x%x", 'x', f_disp10, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stl:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_flds.f
+ UINT f_left;
+ SI f_disp10x4;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2));
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp10x4) = f_disp10x4;
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stl", "f_disp10x4 0x%x", 'x', f_disp10x4, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stq:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ UINT f_left;
+ SI f_disp10x8;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3));
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp10x8) = f_disp10x8;
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stq", "f_disp10x8 0x%x", 'x', f_disp10x8, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stw:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_lduw.f
+ UINT f_left;
+ SI f_disp10x2;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_disp10x2 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (1));
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp10x2) = f_disp10x2;
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stw", "f_disp10x2 0x%x", 'x', f_disp10x2, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_sthil:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_sthil.f
+ UINT f_left;
+ INT f_disp6;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_disp6 = EXTRACT_LSB0_INT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_disp6) = f_disp6;
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sthil", "f_disp6 0x%x", 'x', f_disp6, "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_stxb:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stxb", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_swapq:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_add.f
+ UINT f_left;
+ UINT f_right;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_dest) = f_dest;
+ FLD (f_left) = f_left;
+ FLD (f_right) = f_right;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_swapq", "f_dest 0x%x", 'x', f_dest, "f_left 0x%x", 'x', f_left, "f_right 0x%x", 'x', f_right, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_trapa:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_xori.f
+ UINT f_left;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_left) = f_left;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trapa", "f_left 0x%x", 'x', f_left, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+ extract_sfmt_xori:
+ {
+ const IDESC *idesc = &sh64_media_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_xori.f
+ UINT f_left;
+ INT f_imm6;
+ UINT f_dest;
+
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6);
+ f_imm6 = EXTRACT_LSB0_INT (insn, 32, 15, 6);
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_imm6) = f_imm6;
+ FLD (f_left) = f_left;
+ FLD (f_dest) = f_dest;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_xori", "f_imm6 0x%x", 'x', f_imm6, "f_left 0x%x", 'x', f_left, "f_dest 0x%x", 'x', f_dest, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
+}
--- /dev/null
+/* Decode header for sh64_media.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef SH64_MEDIA_DECODE_H
+#define SH64_MEDIA_DECODE_H
+
+extern const IDESC *sh64_media_decode (SIM_CPU *, IADDR,
+ CGEN_INSN_INT, CGEN_INSN_INT,
+ ARGBUF *);
+extern void sh64_media_init_idesc_table (SIM_CPU *);
+extern void sh64_media_sem_init_idesc_table (SIM_CPU *);
+extern void sh64_media_semf_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family sh64. */
+typedef enum sh64_media_insn_type {
+ SH64_MEDIA_INSN_X_INVALID, SH64_MEDIA_INSN_X_AFTER, SH64_MEDIA_INSN_X_BEFORE, SH64_MEDIA_INSN_X_CTI_CHAIN
+ , SH64_MEDIA_INSN_X_CHAIN, SH64_MEDIA_INSN_X_BEGIN, SH64_MEDIA_INSN_ADD, SH64_MEDIA_INSN_ADDL
+ , SH64_MEDIA_INSN_ADDI, SH64_MEDIA_INSN_ADDIL, SH64_MEDIA_INSN_ADDZL, SH64_MEDIA_INSN_ALLOCO
+ , SH64_MEDIA_INSN_AND, SH64_MEDIA_INSN_ANDC, SH64_MEDIA_INSN_ANDI, SH64_MEDIA_INSN_BEQ
+ , SH64_MEDIA_INSN_BEQI, SH64_MEDIA_INSN_BGE, SH64_MEDIA_INSN_BGEU, SH64_MEDIA_INSN_BGT
+ , SH64_MEDIA_INSN_BGTU, SH64_MEDIA_INSN_BLINK, SH64_MEDIA_INSN_BNE, SH64_MEDIA_INSN_BNEI
+ , SH64_MEDIA_INSN_BRK, SH64_MEDIA_INSN_BYTEREV, SH64_MEDIA_INSN_CMPEQ, SH64_MEDIA_INSN_CMPGT
+ , SH64_MEDIA_INSN_CMPGTU, SH64_MEDIA_INSN_CMVEQ, SH64_MEDIA_INSN_CMVNE, SH64_MEDIA_INSN_FABSD
+ , SH64_MEDIA_INSN_FABSS, SH64_MEDIA_INSN_FADDD, SH64_MEDIA_INSN_FADDS, SH64_MEDIA_INSN_FCMPEQD
+ , SH64_MEDIA_INSN_FCMPEQS, SH64_MEDIA_INSN_FCMPGED, SH64_MEDIA_INSN_FCMPGES, SH64_MEDIA_INSN_FCMPGTD
+ , SH64_MEDIA_INSN_FCMPGTS, SH64_MEDIA_INSN_FCMPUND, SH64_MEDIA_INSN_FCMPUNS, SH64_MEDIA_INSN_FCNVDS
+ , SH64_MEDIA_INSN_FCNVSD, SH64_MEDIA_INSN_FDIVD, SH64_MEDIA_INSN_FDIVS, SH64_MEDIA_INSN_FGETSCR
+ , SH64_MEDIA_INSN_FIPRS, SH64_MEDIA_INSN_FLDD, SH64_MEDIA_INSN_FLDP, SH64_MEDIA_INSN_FLDS
+ , SH64_MEDIA_INSN_FLDXD, SH64_MEDIA_INSN_FLDXP, SH64_MEDIA_INSN_FLDXS, SH64_MEDIA_INSN_FLOATLD
+ , SH64_MEDIA_INSN_FLOATLS, SH64_MEDIA_INSN_FLOATQD, SH64_MEDIA_INSN_FLOATQS, SH64_MEDIA_INSN_FMACS
+ , SH64_MEDIA_INSN_FMOVD, SH64_MEDIA_INSN_FMOVDQ, SH64_MEDIA_INSN_FMOVLS, SH64_MEDIA_INSN_FMOVQD
+ , SH64_MEDIA_INSN_FMOVS, SH64_MEDIA_INSN_FMOVSL, SH64_MEDIA_INSN_FMULD, SH64_MEDIA_INSN_FMULS
+ , SH64_MEDIA_INSN_FNEGD, SH64_MEDIA_INSN_FNEGS, SH64_MEDIA_INSN_FPUTSCR, SH64_MEDIA_INSN_FSQRTD
+ , SH64_MEDIA_INSN_FSQRTS, SH64_MEDIA_INSN_FSTD, SH64_MEDIA_INSN_FSTP, SH64_MEDIA_INSN_FSTS
+ , SH64_MEDIA_INSN_FSTXD, SH64_MEDIA_INSN_FSTXP, SH64_MEDIA_INSN_FSTXS, SH64_MEDIA_INSN_FSUBD
+ , SH64_MEDIA_INSN_FSUBS, SH64_MEDIA_INSN_FTRCDL, SH64_MEDIA_INSN_FTRCSL, SH64_MEDIA_INSN_FTRCDQ
+ , SH64_MEDIA_INSN_FTRCSQ, SH64_MEDIA_INSN_FTRVS, SH64_MEDIA_INSN_GETCFG, SH64_MEDIA_INSN_GETCON
+ , SH64_MEDIA_INSN_GETTR, SH64_MEDIA_INSN_ICBI, SH64_MEDIA_INSN_LDB, SH64_MEDIA_INSN_LDL
+ , SH64_MEDIA_INSN_LDQ, SH64_MEDIA_INSN_LDUB, SH64_MEDIA_INSN_LDUW, SH64_MEDIA_INSN_LDW
+ , SH64_MEDIA_INSN_LDHIL, SH64_MEDIA_INSN_LDHIQ, SH64_MEDIA_INSN_LDLOL, SH64_MEDIA_INSN_LDLOQ
+ , SH64_MEDIA_INSN_LDXB, SH64_MEDIA_INSN_LDXL, SH64_MEDIA_INSN_LDXQ, SH64_MEDIA_INSN_LDXUB
+ , SH64_MEDIA_INSN_LDXUW, SH64_MEDIA_INSN_LDXW, SH64_MEDIA_INSN_MABSL, SH64_MEDIA_INSN_MABSW
+ , SH64_MEDIA_INSN_MADDL, SH64_MEDIA_INSN_MADDW, SH64_MEDIA_INSN_MADDSL, SH64_MEDIA_INSN_MADDSUB
+ , SH64_MEDIA_INSN_MADDSW, SH64_MEDIA_INSN_MCMPEQB, SH64_MEDIA_INSN_MCMPEQL, SH64_MEDIA_INSN_MCMPEQW
+ , SH64_MEDIA_INSN_MCMPGTL, SH64_MEDIA_INSN_MCMPGTUB, SH64_MEDIA_INSN_MCMPGTW, SH64_MEDIA_INSN_MCMV
+ , SH64_MEDIA_INSN_MCNVSLW, SH64_MEDIA_INSN_MCNVSWB, SH64_MEDIA_INSN_MCNVSWUB, SH64_MEDIA_INSN_MEXTR1
+ , SH64_MEDIA_INSN_MEXTR2, SH64_MEDIA_INSN_MEXTR3, SH64_MEDIA_INSN_MEXTR4, SH64_MEDIA_INSN_MEXTR5
+ , SH64_MEDIA_INSN_MEXTR6, SH64_MEDIA_INSN_MEXTR7, SH64_MEDIA_INSN_MMACFXWL, SH64_MEDIA_INSN_MMACNFX_WL
+ , SH64_MEDIA_INSN_MMULL, SH64_MEDIA_INSN_MMULW, SH64_MEDIA_INSN_MMULFXL, SH64_MEDIA_INSN_MMULFXW
+ , SH64_MEDIA_INSN_MMULFXRPW, SH64_MEDIA_INSN_MMULHIWL, SH64_MEDIA_INSN_MMULLOWL, SH64_MEDIA_INSN_MMULSUMWQ
+ , SH64_MEDIA_INSN_MOVI, SH64_MEDIA_INSN_MPERMW, SH64_MEDIA_INSN_MSADUBQ, SH64_MEDIA_INSN_MSHALDSL
+ , SH64_MEDIA_INSN_MSHALDSW, SH64_MEDIA_INSN_MSHARDL, SH64_MEDIA_INSN_MSHARDW, SH64_MEDIA_INSN_MSHARDSQ
+ , SH64_MEDIA_INSN_MSHFHIB, SH64_MEDIA_INSN_MSHFHIL, SH64_MEDIA_INSN_MSHFHIW, SH64_MEDIA_INSN_MSHFLOB
+ , SH64_MEDIA_INSN_MSHFLOL, SH64_MEDIA_INSN_MSHFLOW, SH64_MEDIA_INSN_MSHLLDL, SH64_MEDIA_INSN_MSHLLDW
+ , SH64_MEDIA_INSN_MSHLRDL, SH64_MEDIA_INSN_MSHLRDW, SH64_MEDIA_INSN_MSUBL, SH64_MEDIA_INSN_MSUBW
+ , SH64_MEDIA_INSN_MSUBSL, SH64_MEDIA_INSN_MSUBSUB, SH64_MEDIA_INSN_MSUBSW, SH64_MEDIA_INSN_MULSL
+ , SH64_MEDIA_INSN_MULUL, SH64_MEDIA_INSN_NOP, SH64_MEDIA_INSN_NSB, SH64_MEDIA_INSN_OCBI
+ , SH64_MEDIA_INSN_OCBP, SH64_MEDIA_INSN_OCBWB, SH64_MEDIA_INSN_OR, SH64_MEDIA_INSN_ORI
+ , SH64_MEDIA_INSN_PREFI, SH64_MEDIA_INSN_PTA, SH64_MEDIA_INSN_PTABS, SH64_MEDIA_INSN_PTB
+ , SH64_MEDIA_INSN_PTREL, SH64_MEDIA_INSN_PUTCFG, SH64_MEDIA_INSN_PUTCON, SH64_MEDIA_INSN_RTE
+ , SH64_MEDIA_INSN_SHARD, SH64_MEDIA_INSN_SHARDL, SH64_MEDIA_INSN_SHARI, SH64_MEDIA_INSN_SHARIL
+ , SH64_MEDIA_INSN_SHLLD, SH64_MEDIA_INSN_SHLLDL, SH64_MEDIA_INSN_SHLLI, SH64_MEDIA_INSN_SHLLIL
+ , SH64_MEDIA_INSN_SHLRD, SH64_MEDIA_INSN_SHLRDL, SH64_MEDIA_INSN_SHLRI, SH64_MEDIA_INSN_SHLRIL
+ , SH64_MEDIA_INSN_SHORI, SH64_MEDIA_INSN_SLEEP, SH64_MEDIA_INSN_STB, SH64_MEDIA_INSN_STL
+ , SH64_MEDIA_INSN_STQ, SH64_MEDIA_INSN_STW, SH64_MEDIA_INSN_STHIL, SH64_MEDIA_INSN_STHIQ
+ , SH64_MEDIA_INSN_STLOL, SH64_MEDIA_INSN_STLOQ, SH64_MEDIA_INSN_STXB, SH64_MEDIA_INSN_STXL
+ , SH64_MEDIA_INSN_STXQ, SH64_MEDIA_INSN_STXW, SH64_MEDIA_INSN_SUB, SH64_MEDIA_INSN_SUBL
+ , SH64_MEDIA_INSN_SWAPQ, SH64_MEDIA_INSN_SYNCI, SH64_MEDIA_INSN_SYNCO, SH64_MEDIA_INSN_TRAPA
+ , SH64_MEDIA_INSN_XOR, SH64_MEDIA_INSN_XORI, SH64_MEDIA_INSN_MAX
+} SH64_MEDIA_INSN_TYPE;
+
+/* Enum declaration for semantic formats in cpu family sh64. */
+typedef enum sh64_media_sfmt_type {
+ SH64_MEDIA_SFMT_EMPTY, SH64_MEDIA_SFMT_ADD, SH64_MEDIA_SFMT_ADDI, SH64_MEDIA_SFMT_ALLOCO
+ , SH64_MEDIA_SFMT_BEQ, SH64_MEDIA_SFMT_BEQI, SH64_MEDIA_SFMT_BLINK, SH64_MEDIA_SFMT_BRK
+ , SH64_MEDIA_SFMT_BYTEREV, SH64_MEDIA_SFMT_CMVEQ, SH64_MEDIA_SFMT_FABSD, SH64_MEDIA_SFMT_FABSS
+ , SH64_MEDIA_SFMT_FADDD, SH64_MEDIA_SFMT_FADDS, SH64_MEDIA_SFMT_FCMPEQD, SH64_MEDIA_SFMT_FCMPEQS
+ , SH64_MEDIA_SFMT_FCNVDS, SH64_MEDIA_SFMT_FCNVSD, SH64_MEDIA_SFMT_FIPRS, SH64_MEDIA_SFMT_FLDD
+ , SH64_MEDIA_SFMT_FLDP, SH64_MEDIA_SFMT_FLDS, SH64_MEDIA_SFMT_FLDXD, SH64_MEDIA_SFMT_FLDXP
+ , SH64_MEDIA_SFMT_FLDXS, SH64_MEDIA_SFMT_FMACS, SH64_MEDIA_SFMT_FMOVDQ, SH64_MEDIA_SFMT_FMOVLS
+ , SH64_MEDIA_SFMT_FMOVQD, SH64_MEDIA_SFMT_FMOVSL, SH64_MEDIA_SFMT_FSTD, SH64_MEDIA_SFMT_FSTP
+ , SH64_MEDIA_SFMT_FSTS, SH64_MEDIA_SFMT_FSTXD, SH64_MEDIA_SFMT_FSTXP, SH64_MEDIA_SFMT_FSTXS
+ , SH64_MEDIA_SFMT_FTRVS, SH64_MEDIA_SFMT_GETCON, SH64_MEDIA_SFMT_GETTR, SH64_MEDIA_SFMT_LDB
+ , SH64_MEDIA_SFMT_LDL, SH64_MEDIA_SFMT_LDQ, SH64_MEDIA_SFMT_LDUW, SH64_MEDIA_SFMT_LDXB
+ , SH64_MEDIA_SFMT_MCMV, SH64_MEDIA_SFMT_MOVI, SH64_MEDIA_SFMT_MPERMW, SH64_MEDIA_SFMT_ORI
+ , SH64_MEDIA_SFMT_PTA, SH64_MEDIA_SFMT_PTABS, SH64_MEDIA_SFMT_PTREL, SH64_MEDIA_SFMT_PUTCON
+ , SH64_MEDIA_SFMT_SHARI, SH64_MEDIA_SFMT_SHARIL, SH64_MEDIA_SFMT_SHORI, SH64_MEDIA_SFMT_STB
+ , SH64_MEDIA_SFMT_STL, SH64_MEDIA_SFMT_STQ, SH64_MEDIA_SFMT_STW, SH64_MEDIA_SFMT_STHIL
+ , SH64_MEDIA_SFMT_STXB, SH64_MEDIA_SFMT_SWAPQ, SH64_MEDIA_SFMT_TRAPA, SH64_MEDIA_SFMT_XORI
+} SH64_MEDIA_SFMT_TYPE;
+
+/* Function unit handlers (user written). */
+
+extern int sh64_model_sh5_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void sh64_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void sh64_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* SH64_MEDIA_DECODE_H */
--- /dev/null
+#ifndef DECODE_H
+#define DECODE_H
+
+#undef WITH_PROFILE_MODEL_P
+
+#ifdef WANT_ISA_COMPACT
+#include "decode-compact.h"
+#include "defs-compact.h"
+#endif /* WANT_ISA_COMPACT */
+
+#ifdef WANT_ISA_MEDIA
+#include "decode-media.h"
+#include "defs-media.h"
+#endif /* WANT_ISA_MEDIA */
+
+#endif /* DECODE_H */
--- /dev/null
+/* ISA definitions header for compact.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef DEFS_SH64_COMPACT_H
+#define DEFS_SH64_COMPACT_H
+
+/* Instruction argument buffer. */
+
+union sem_fields {
+ struct { /* no operands */
+ int empty;
+ } fmt_empty;
+ struct { /* */
+ SI f_dn;
+ } sfmt_fcnvds_compact;
+ struct { /* */
+ IADDR i_disp12;
+ } sfmt_bra_compact;
+ struct { /* */
+ IADDR i_disp8;
+ } sfmt_bf_compact;
+ struct { /* */
+ SI f_imm4x2;
+ UINT f_rm;
+ } sfmt_movw11_compact;
+ struct { /* */
+ SI f_imm8x2;
+ UINT f_rn;
+ } sfmt_movw10_compact;
+ struct { /* */
+ SI f_imm4x2;
+ UINT f_rn;
+ } sfmt_movw5_compact;
+ struct { /* */
+ SI f_imm8x4;
+ UINT f_rn;
+ } sfmt_movl10_compact;
+ struct { /* */
+ UINT f_imm4;
+ UINT f_rm;
+ } sfmt_movb5_compact;
+ struct { /* */
+ SI f_vm;
+ SI f_vn;
+ } sfmt_fipr_compact;
+ struct { /* */
+ UINT f_imm8;
+ UINT f_rn;
+ } sfmt_addi_compact;
+ struct { /* */
+ SI f_imm4x4;
+ UINT f_rm;
+ UINT f_rn;
+ } sfmt_movl5_compact;
+#if WITH_SCACHE_PBB
+ /* Writeback handler. */
+ struct {
+ /* Pointer to argbuf entry for insn whose results need writing back. */
+ const struct argbuf *abuf;
+ } write;
+ /* x-before handler */
+ struct {
+ /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+ int first_p;
+ } before;
+ /* x-after handler */
+ struct {
+ int empty;
+ } after;
+ /* This entry is used to terminate each pbb. */
+ struct {
+ /* Number of insns in pbb. */
+ int insn_count;
+ /* Next pbb to execute. */
+ SCACHE *next;
+ SCACHE *branch_target;
+ } chain;
+#endif
+};
+
+/* The ARGBUF struct. */
+struct argbuf {
+ /* These are the baseclass definitions. */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
+ /* cpu specific data follows */
+ union sem semantic;
+ int written;
+ union sem_fields fields;
+};
+
+/* A cached insn.
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
+
+struct scache {
+ struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+ These define and assign the local vars that contain the insn's fields. */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+ unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+ length = 0; \
+
+#define EXTRACT_IFMT_ADD_COMPACT_VARS \
+ UINT f_op4; \
+ UINT f_rn; \
+ UINT f_rm; \
+ UINT f_sub4; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
+ f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_ADDI_COMPACT_VARS \
+ UINT f_op4; \
+ UINT f_rn; \
+ UINT f_imm8; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADDI_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
+ f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
+
+#define EXTRACT_IFMT_AND_COMPACT_VARS \
+ UINT f_op4; \
+ UINT f_rn; \
+ UINT f_rm; \
+ UINT f_sub4; \
+ unsigned int length;
+#define EXTRACT_IFMT_AND_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
+ f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_ANDI_COMPACT_VARS \
+ UINT f_op8; \
+ UINT f_imm8; \
+ unsigned int length;
+#define EXTRACT_IFMT_ANDI_COMPACT_CODE \
+ length = 2; \
+ f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
+ f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
+
+#define EXTRACT_IFMT_ANDB_COMPACT_VARS \
+ UINT f_op8; \
+ UINT f_imm8; \
+ unsigned int length;
+#define EXTRACT_IFMT_ANDB_COMPACT_CODE \
+ length = 2; \
+ f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
+ f_imm8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
+
+#define EXTRACT_IFMT_BF_COMPACT_VARS \
+ UINT f_op8; \
+ SI f_disp8; \
+ unsigned int length;
+#define EXTRACT_IFMT_BF_COMPACT_CODE \
+ length = 2; \
+ f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
+ f_disp8 = ((((EXTRACT_LSB0_INT (insn, 16, 7, 8)) << (1))) + (((pc) + (4)))); \
+
+#define EXTRACT_IFMT_BRA_COMPACT_VARS \
+ UINT f_op4; \
+ SI f_disp12; \
+ unsigned int length;
+#define EXTRACT_IFMT_BRA_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_disp12 = ((((EXTRACT_LSB0_INT (insn, 16, 11, 12)) << (1))) + (((pc) + (4)))); \
+
+#define EXTRACT_IFMT_BRAF_COMPACT_VARS \
+ UINT f_op4; \
+ UINT f_rn; \
+ UINT f_sub8; \
+ unsigned int length;
+#define EXTRACT_IFMT_BRAF_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
+ f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
+
+#define EXTRACT_IFMT_BRK_COMPACT_VARS \
+ UINT f_op16; \
+ unsigned int length;
+#define EXTRACT_IFMT_BRK_COMPACT_CODE \
+ length = 2; \
+ f_op16 = EXTRACT_LSB0_UINT (insn, 16, 15, 16); \
+
+#define EXTRACT_IFMT_FABS_COMPACT_VARS \
+ UINT f_op4; \
+ UINT f_rn; \
+ UINT f_sub8; \
+ unsigned int length;
+#define EXTRACT_IFMT_FABS_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
+ f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
+
+#define EXTRACT_IFMT_FADD_COMPACT_VARS \
+ UINT f_op4; \
+ UINT f_rn; \
+ UINT f_rm; \
+ UINT f_sub4; \
+ unsigned int length;
+#define EXTRACT_IFMT_FADD_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
+ f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_FCNVDS_COMPACT_VARS \
+ UINT f_op4; \
+ SI f_dn; \
+ UINT f_8_1; \
+ UINT f_sub8; \
+ unsigned int length;
+#define EXTRACT_IFMT_FCNVDS_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_dn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 3)) << (1)); \
+ f_8_1 = EXTRACT_LSB0_UINT (insn, 16, 8, 1); \
+ f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
+
+#define EXTRACT_IFMT_FIPR_COMPACT_VARS \
+ UINT f_op4; \
+ SI f_vn; \
+ SI f_vm; \
+ UINT f_sub8; \
+ unsigned int length;
+#define EXTRACT_IFMT_FIPR_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_vn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 2)) << (2)); \
+ f_vm = ((EXTRACT_LSB0_UINT (insn, 16, 9, 2)) << (2)); \
+ f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
+
+#define EXTRACT_IFMT_FLDS_COMPACT_VARS \
+ UINT f_op4; \
+ UINT f_rn; \
+ UINT f_sub8; \
+ unsigned int length;
+#define EXTRACT_IFMT_FLDS_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
+ f_sub8 = EXTRACT_LSB0_UINT (insn, 16, 7, 8); \
+
+#define EXTRACT_IFMT_FMAC_COMPACT_VARS \
+ UINT f_op4; \
+ UINT f_rn; \
+ UINT f_rm; \
+ UINT f_sub4; \
+ unsigned int length;
+#define EXTRACT_IFMT_FMAC_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
+ f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_FMOV2_COMPACT_VARS \
+ UINT f_op4; \
+ UINT f_rn; \
+ UINT f_rm; \
+ UINT f_sub4; \
+ unsigned int length;
+#define EXTRACT_IFMT_FMOV2_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
+ f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_FMOV5_COMPACT_VARS \
+ UINT f_op4; \
+ UINT f_rn; \
+ UINT f_rm; \
+ UINT f_sub4; \
+ unsigned int length;
+#define EXTRACT_IFMT_FMOV5_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
+ f_sub4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_FTRV_COMPACT_VARS \
+ UINT f_op4; \
+ SI f_vn; \
+ UINT f_sub10; \
+ unsigned int length;
+#define EXTRACT_IFMT_FTRV_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_vn = ((EXTRACT_LSB0_UINT (insn, 16, 11, 2)) << (2)); \
+ f_sub10 = EXTRACT_LSB0_UINT (insn, 16, 9, 10); \
+
+#define EXTRACT_IFMT_MOVB5_COMPACT_VARS \
+ UINT f_op8; \
+ UINT f_rm; \
+ UINT f_imm4; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVB5_COMPACT_CODE \
+ length = 2; \
+ f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
+ f_imm4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
+
+#define EXTRACT_IFMT_MOVL4_COMPACT_VARS \
+ UINT f_op8; \
+ SI f_imm8x4; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVL4_COMPACT_CODE \
+ length = 2; \
+ f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
+ f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2)); \
+
+#define EXTRACT_IFMT_MOVL5_COMPACT_VARS \
+ UINT f_op4; \
+ UINT f_rn; \
+ UINT f_rm; \
+ SI f_imm4x4; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVL5_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
+ f_imm4x4 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (2)); \
+
+#define EXTRACT_IFMT_MOVL10_COMPACT_VARS \
+ UINT f_op4; \
+ UINT f_rn; \
+ SI f_imm8x4; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVL10_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
+ f_imm8x4 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (2)); \
+
+#define EXTRACT_IFMT_MOVW4_COMPACT_VARS \
+ UINT f_op8; \
+ SI f_imm8x2; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVW4_COMPACT_CODE \
+ length = 2; \
+ f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
+ f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1)); \
+
+#define EXTRACT_IFMT_MOVW5_COMPACT_VARS \
+ UINT f_op8; \
+ UINT f_rn; \
+ SI f_imm4x2; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVW5_COMPACT_CODE \
+ length = 2; \
+ f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
+ f_imm4x2 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1)); \
+
+#define EXTRACT_IFMT_MOVW10_COMPACT_VARS \
+ UINT f_op4; \
+ UINT f_rn; \
+ SI f_imm8x2; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVW10_COMPACT_CODE \
+ length = 2; \
+ f_op4 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
+ f_rn = EXTRACT_LSB0_UINT (insn, 16, 11, 4); \
+ f_imm8x2 = ((EXTRACT_LSB0_UINT (insn, 16, 7, 8)) << (1)); \
+
+#define EXTRACT_IFMT_MOVW11_COMPACT_VARS \
+ UINT f_op8; \
+ UINT f_rm; \
+ SI f_imm4x2; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVW11_COMPACT_CODE \
+ length = 2; \
+ f_op8 = EXTRACT_LSB0_UINT (insn, 16, 15, 8); \
+ f_rm = EXTRACT_LSB0_UINT (insn, 16, 7, 4); \
+ f_imm4x2 = ((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1)); \
+
+#endif /* DEFS_SH64_COMPACT_H */
--- /dev/null
+/* ISA definitions header for media.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef DEFS_SH64_MEDIA_H
+#define DEFS_SH64_MEDIA_H
+
+/* Instruction argument buffer. */
+
+union sem_fields {
+ struct { /* no operands */
+ int empty;
+ } fmt_empty;
+ struct { /* */
+ UINT f_dest;
+ UINT f_uimm16;
+ } sfmt_shori;
+ struct { /* */
+ DI f_disp16;
+ UINT f_tra;
+ } sfmt_pta;
+ struct { /* */
+ INT f_imm16;
+ UINT f_dest;
+ } sfmt_movi;
+ struct { /* */
+ UINT f_dest;
+ UINT f_left_right;
+ } sfmt_fabsd;
+ struct { /* */
+ UINT f_dest;
+ UINT f_trb;
+ } sfmt_blink;
+ struct { /* */
+ INT f_imm6;
+ UINT f_dest;
+ UINT f_left;
+ } sfmt_xori;
+ struct { /* */
+ INT f_disp6;
+ UINT f_dest;
+ UINT f_left;
+ } sfmt_sthil;
+ struct { /* */
+ UINT f_dest;
+ UINT f_left;
+ UINT f_uimm6;
+ } sfmt_shari;
+ struct { /* */
+ INT f_imm10;
+ UINT f_dest;
+ UINT f_left;
+ } sfmt_ori;
+ struct { /* */
+ SI f_disp10x2;
+ UINT f_dest;
+ UINT f_left;
+ } sfmt_lduw;
+ struct { /* */
+ SI f_disp10x4;
+ UINT f_dest;
+ UINT f_left;
+ } sfmt_flds;
+ struct { /* */
+ SI f_disp10x8;
+ UINT f_dest;
+ UINT f_left;
+ } sfmt_fldd;
+ struct { /* */
+ INT f_imm6;
+ UINT f_left;
+ UINT f_tra;
+ } sfmt_beqi;
+ struct { /* */
+ UINT f_left;
+ UINT f_right;
+ UINT f_tra;
+ } sfmt_beq;
+ struct { /* */
+ INT f_disp10;
+ UINT f_dest;
+ UINT f_left;
+ } sfmt_addi;
+ struct { /* */
+ UINT f_dest;
+ UINT f_left;
+ UINT f_right;
+ } sfmt_add;
+#if WITH_SCACHE_PBB
+ /* Writeback handler. */
+ struct {
+ /* Pointer to argbuf entry for insn whose results need writing back. */
+ const struct argbuf *abuf;
+ } write;
+ /* x-before handler */
+ struct {
+ /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
+ int first_p;
+ } before;
+ /* x-after handler */
+ struct {
+ int empty;
+ } after;
+ /* This entry is used to terminate each pbb. */
+ struct {
+ /* Number of insns in pbb. */
+ int insn_count;
+ /* Next pbb to execute. */
+ SCACHE *next;
+ SCACHE *branch_target;
+ } chain;
+#endif
+};
+
+/* The ARGBUF struct. */
+struct argbuf {
+ /* These are the baseclass definitions. */
+ IADDR addr;
+ const IDESC *idesc;
+ char trace_p;
+ char profile_p;
+ /* ??? Temporary hack for skip insns. */
+ char skip_count;
+ char unused;
+ /* cpu specific data follows */
+ union sem semantic;
+ int written;
+ union sem_fields fields;
+};
+
+/* A cached insn.
+
+ ??? SCACHE used to contain more than just argbuf. We could delete the
+ type entirely and always just use ARGBUF, but for future concerns and as
+ a level of abstraction it is left in. */
+
+struct scache {
+ struct argbuf argbuf;
+};
+
+/* Macros to simplify extraction, reading and semantic code.
+ These define and assign the local vars that contain the insn's fields. */
+
+#define EXTRACT_IFMT_EMPTY_VARS \
+ unsigned int length;
+#define EXTRACT_IFMT_EMPTY_CODE \
+ length = 0; \
+
+#define EXTRACT_IFMT_ADD_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADD_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_ADDI_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ INT f_disp10; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_ADDI_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_disp10 = EXTRACT_LSB0_INT (insn, 32, 19, 10); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_ALLOCO_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ SI f_disp6x32; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_ALLOCO_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_disp6x32 = ((EXTRACT_LSB0_INT (insn, 32, 15, 6)) << (5)); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_BEQ_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_likely; \
+ UINT f_8_2; \
+ UINT f_tra; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_BEQ_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_likely = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
+ f_8_2 = EXTRACT_LSB0_UINT (insn, 32, 8, 2); \
+ f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_BEQI_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ INT f_imm6; \
+ UINT f_likely; \
+ UINT f_8_2; \
+ UINT f_tra; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_BEQI_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_imm6 = EXTRACT_LSB0_INT (insn, 32, 15, 6); \
+ f_likely = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
+ f_8_2 = EXTRACT_LSB0_UINT (insn, 32, 8, 2); \
+ f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_BLINK_VARS \
+ UINT f_op; \
+ UINT f_25; \
+ UINT f_trb; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_BLINK_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_25 = EXTRACT_LSB0_UINT (insn, 32, 25, 3); \
+ f_trb = EXTRACT_LSB0_UINT (insn, 32, 22, 3); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_BRK_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_BRK_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_BYTEREV_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_BYTEREV_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FABSD_VARS \
+ UINT f_op; \
+ UINT f_ext; \
+ UINT f_left; \
+ UINT f_right; \
+ UINT f_left_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FABSD_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_left_right = f_left;\
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FABSS_VARS \
+ UINT f_op; \
+ UINT f_ext; \
+ UINT f_left; \
+ UINT f_right; \
+ UINT f_left_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FABSS_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_left_right = f_left;\
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FADDD_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FADDD_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FADDS_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FADDS_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FCMPEQD_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FCMPEQD_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FCMPEQS_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FCMPEQS_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FCNVDS_VARS \
+ UINT f_op; \
+ UINT f_ext; \
+ UINT f_left; \
+ UINT f_right; \
+ UINT f_left_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FCNVDS_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_left_right = f_left;\
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FCNVSD_VARS \
+ UINT f_op; \
+ UINT f_ext; \
+ UINT f_left; \
+ UINT f_right; \
+ UINT f_left_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FCNVSD_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_left_right = f_left;\
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FGETSCR_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FGETSCR_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FIPRS_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FIPRS_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FLDD_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ SI f_disp10x8; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FLDD_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FLDP_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ SI f_disp10x8; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FLDP_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FLDS_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ SI f_disp10x4; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FLDS_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2)); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FLDXD_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FLDXD_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FLDXP_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FLDXP_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FMOVDQ_VARS \
+ UINT f_op; \
+ UINT f_ext; \
+ UINT f_left; \
+ UINT f_right; \
+ UINT f_left_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FMOVDQ_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_left_right = f_left;\
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FMOVLS_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FMOVLS_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FMOVSL_VARS \
+ UINT f_op; \
+ UINT f_ext; \
+ UINT f_left; \
+ UINT f_right; \
+ UINT f_left_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FMOVSL_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_left_right = f_left;\
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FPUTSCR_VARS \
+ UINT f_op; \
+ UINT f_ext; \
+ UINT f_left; \
+ UINT f_right; \
+ UINT f_left_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FPUTSCR_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_left_right = f_left;\
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FSTXD_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FSTXD_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_FTRVS_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_FTRVS_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_GETCFG_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ INT f_disp6; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_GETCFG_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_disp6 = EXTRACT_LSB0_INT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_GETCON_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_GETCON_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_LDL_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ SI f_disp10x4; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDL_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_disp10x4 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (2)); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_LDQ_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ SI f_disp10x8; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_LDQ_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_disp10x8 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (3)); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_MMACNFX_WL_VARS \
+ UINT f_op; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_MMACNFX_WL_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_MOVI_VARS \
+ UINT f_op; \
+ INT f_imm16; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_MOVI_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_imm16 = EXTRACT_LSB0_INT (insn, 32, 25, 16); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_ORI_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ INT f_imm10; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_ORI_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_imm10 = EXTRACT_LSB0_INT (insn, 32, 19, 10); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_PREFI_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ SI f_disp6x32; \
+ UINT f_right; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_PREFI_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_disp6x32 = ((EXTRACT_LSB0_INT (insn, 32, 15, 6)) << (5)); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_PTA_VARS \
+ UINT f_op; \
+ DI f_disp16; \
+ UINT f_likely; \
+ UINT f_8_2; \
+ UINT f_tra; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_PTA_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_disp16 = ((((EXTRACT_LSB0_INT (insn, 32, 25, 16)) << (2))) + (pc)); \
+ f_likely = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
+ f_8_2 = EXTRACT_LSB0_UINT (insn, 32, 8, 2); \
+ f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_PTABS_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_likely; \
+ UINT f_8_2; \
+ UINT f_tra; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_PTABS_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_likely = EXTRACT_LSB0_UINT (insn, 32, 9, 1); \
+ f_8_2 = EXTRACT_LSB0_UINT (insn, 32, 8, 2); \
+ f_tra = EXTRACT_LSB0_UINT (insn, 32, 6, 3); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_PUTCON_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_PUTCON_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_SHARI_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_uimm6; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_SHARI_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_uimm6 = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_SHORI_VARS \
+ UINT f_op; \
+ UINT f_uimm16; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_SHORI_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 25, 16); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_STW_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ SI f_disp10x2; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_STW_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_disp10x2 = ((EXTRACT_LSB0_INT (insn, 32, 19, 10)) << (1)); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#define EXTRACT_IFMT_TRAPA_VARS \
+ UINT f_op; \
+ UINT f_left; \
+ UINT f_ext; \
+ UINT f_right; \
+ UINT f_dest; \
+ UINT f_rsvd; \
+ unsigned int length;
+#define EXTRACT_IFMT_TRAPA_CODE \
+ length = 4; \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_left = EXTRACT_LSB0_UINT (insn, 32, 25, 6); \
+ f_ext = EXTRACT_LSB0_UINT (insn, 32, 19, 4); \
+ f_right = EXTRACT_LSB0_UINT (insn, 32, 15, 6); \
+ f_dest = EXTRACT_LSB0_UINT (insn, 32, 9, 6); \
+ f_rsvd = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
+
+#endif /* DEFS_SH64_MEDIA_H */
--- /dev/null
+/* engine configuration for sh64 */
+
+/* WITH_FAST: non-zero if a fast version of the engine is available
+ in addition to the full-featured version. */
+#define WITH_FAST 1
+
+/* WITH_SCACHE_PBB_SH64_COMPACT: non-zero if the pbb engine was selected. */
+#define WITH_SCACHE_PBB_SH64_COMPACT 1
+
+/* HAVE_PARALLEL_INSNS: non-zero if cpu can parallelly execute > 1 insn. */
+#define HAVE_PARALLEL_INSNS 0
+#define WITH_PARALLEL_READ 0
+#define WITH_PARALLEL_WRITE 0
+#define WITH_PARALLEL_GENWRITE 0
+
+/* WITH_SEM_SWITCH_FULL: non-zero if full-featured engine is
+ implemented as a switch(). */
+#define WITH_SEM_SWITCH_FULL 0
+
+/* WITH_SEM_SWITCH_FAST: non-zero if fast engine is
+ implemented as a switch(). */
+#define WITH_SEM_SWITCH_FAST 1
+
+/* Functions defined in the generated mainloop.c file
+ (which doesn't necessarily have that file name). */
+
+extern ENGINE_FN sh64_compact_engine_run_full;
+extern ENGINE_FN sh64_compact_engine_run_fast;
+
+extern SEM_PC sh64_compact_pbb_begin (SIM_CPU *, int);
+extern SEM_PC sh64_compact_pbb_chain (SIM_CPU *, SEM_ARG);
+extern SEM_PC sh64_compact_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_BRANCH_TYPE, PCADDR);
+extern void sh64_compact_pbb_before (SIM_CPU *, SCACHE *);
+extern void sh64_compact_pbb_after (SIM_CPU *, SCACHE *);
--- /dev/null
+/* engine configuration for sh64 */
+
+/* WITH_FAST: non-zero if a fast version of the engine is available
+ in addition to the full-featured version. */
+#define WITH_FAST 1
+
+/* WITH_SCACHE_PBB_SH64_MEDIA: non-zero if the pbb engine was selected. */
+#define WITH_SCACHE_PBB_SH64_MEDIA 1
+
+/* HAVE_PARALLEL_INSNS: non-zero if cpu can parallelly execute > 1 insn. */
+#define HAVE_PARALLEL_INSNS 0
+#define WITH_PARALLEL_READ 0
+#define WITH_PARALLEL_WRITE 0
+#define WITH_PARALLEL_GENWRITE 0
+
+/* WITH_SEM_SWITCH_FULL: non-zero if full-featured engine is
+ implemented as a switch(). */
+#define WITH_SEM_SWITCH_FULL 0
+
+/* WITH_SEM_SWITCH_FAST: non-zero if fast engine is
+ implemented as a switch(). */
+#define WITH_SEM_SWITCH_FAST 1
+
+/* Functions defined in the generated mainloop.c file
+ (which doesn't necessarily have that file name). */
+
+extern ENGINE_FN sh64_media_engine_run_full;
+extern ENGINE_FN sh64_media_engine_run_fast;
+
+extern SEM_PC sh64_media_pbb_begin (SIM_CPU *, int);
+extern SEM_PC sh64_media_pbb_chain (SIM_CPU *, SEM_ARG);
+extern SEM_PC sh64_media_pbb_cti_chain (SIM_CPU *, SEM_ARG, SEM_BRANCH_TYPE, PCADDR);
+extern void sh64_media_pbb_before (SIM_CPU *, SCACHE *);
+extern void sh64_media_pbb_after (SIM_CPU *, SCACHE *);
--- /dev/null
+/* Engine declarations.
+ Copyright (C) 2000 Free Software Foundation, Inc.
+ Contributed by Red Hat, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+/* Include declarations for SHmedia and SHcompact ISAs. */
+
+#include "eng-compact.h"
+#include "eng-media.h"
--- /dev/null
+/* This file is generated by the genmloop script. DO NOT EDIT! */
+
+/* Enable switch() support in cgen headers. */
+#define SEM_IN_SWITCH
+
+#define WANT_CPU sh64
+#define WANT_CPU_SH64
+
+#include "sim-main.h"
+#include "bfd.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+#include "sim-assert.h"
+
+/* Fill in the administrative ARGBUF fields required by all insns,
+ virtual and real. */
+
+static INLINE void
+sh64_compact_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
+ PCADDR pc, int fast_p)
+{
+#if WITH_SCACHE
+ SEM_SET_CODE (abuf, idesc, fast_p);
+ ARGBUF_ADDR (abuf) = pc;
+#endif
+ ARGBUF_IDESC (abuf) = idesc;
+}
+
+/* Fill in tracing/profiling fields of an ARGBUF. */
+
+static INLINE void
+sh64_compact_fill_argbuf_tp (const SIM_CPU *cpu, ARGBUF *abuf,
+ int trace_p, int profile_p)
+{
+ ARGBUF_TRACE_P (abuf) = trace_p;
+ ARGBUF_PROFILE_P (abuf) = profile_p;
+}
+
+#if WITH_SCACHE_PBB
+
+/* Emit the "x-before" handler.
+ x-before is emitted before each insn (serial or parallel).
+ This is as opposed to x-after which is only emitted at the end of a group
+ of parallel insns. */
+
+static INLINE void
+sh64_compact_emit_before (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc, int first_p)
+{
+ ARGBUF *abuf = &sc[0].argbuf;
+ const IDESC *id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEFORE];
+
+ abuf->fields.before.first_p = first_p;
+ sh64_compact_fill_argbuf (current_cpu, abuf, id, pc, 0);
+ /* no need to set trace_p,profile_p */
+}
+
+/* Emit the "x-after" handler.
+ x-after is emitted after a serial insn or at the end of a group of
+ parallel insns. */
+
+static INLINE void
+sh64_compact_emit_after (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc)
+{
+ ARGBUF *abuf = &sc[0].argbuf;
+ const IDESC *id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_AFTER];
+
+ sh64_compact_fill_argbuf (current_cpu, abuf, id, pc, 0);
+ /* no need to set trace_p,profile_p */
+}
+
+#endif /* WITH_SCACHE_PBB */
+
+
+static INLINE const IDESC *
+extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
+ int fast_p)
+{
+ const IDESC *id = sh64_compact_decode (current_cpu, pc, insn, insn, abuf);
+
+ sh64_compact_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+ if (! fast_p)
+ {
+ int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+ int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+ sh64_compact_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
+ }
+ return id;
+}
+
+static INLINE SEM_PC
+execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
+{
+ SEM_PC vpc;
+
+ if (fast_p)
+ {
+#if ! WITH_SEM_SWITCH_FAST
+#if WITH_SCACHE
+ vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
+#else
+ vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
+#endif
+#else
+ abort ();
+#endif /* WITH_SEM_SWITCH_FAST */
+ }
+ else
+ {
+#if ! WITH_SEM_SWITCH_FULL
+ ARGBUF *abuf = &sc->argbuf;
+ const IDESC *idesc = abuf->idesc;
+#if WITH_SCACHE_PBB
+ int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
+#else
+ int virtual_p = 0;
+#endif
+
+ if (! virtual_p)
+ {
+ /* FIXME: call x-before */
+ if (ARGBUF_PROFILE_P (abuf))
+ PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
+ /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (abuf))
+ sh64_compact_model_insn_before (current_cpu, 1 /*first_p*/);
+ TRACE_INSN_INIT (current_cpu, abuf, 1);
+ TRACE_INSN (current_cpu, idesc->idata,
+ (const struct argbuf *) abuf, abuf->addr);
+ }
+#if WITH_SCACHE
+ vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
+#else
+ vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
+#endif
+ if (! virtual_p)
+ {
+ /* FIXME: call x-after */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (abuf))
+ {
+ int cycles;
+
+ cycles = (*idesc->timing->model_fn) (current_cpu, sc);
+ sh64_compact_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
+ }
+ TRACE_INSN_FINI (current_cpu, abuf, 1);
+ }
+#else
+ abort ();
+#endif /* WITH_SEM_SWITCH_FULL */
+ }
+
+ return vpc;
+}
+
+
+/* Record address of cti terminating a pbb. */
+#define SET_CTI_VPC(sc) do { _cti_sc = (sc); } while (0)
+/* Record number of [real] insns in pbb. */
+#define SET_INSN_COUNT(n) do { _insn_count = (n); } while (0)
+
+/* Fetch and extract a pseudo-basic-block.
+ FAST_P is non-zero if no tracing/profiling/etc. is wanted. */
+
+INLINE SEM_PC
+sh64_compact_pbb_begin (SIM_CPU *current_cpu, int FAST_P)
+{
+ SEM_PC new_vpc;
+ PCADDR pc;
+ SCACHE *sc;
+ int max_insns = CPU_SCACHE_MAX_CHAIN_LENGTH (current_cpu);
+
+ pc = GET_H_PC ();
+
+ new_vpc = scache_lookup_or_alloc (current_cpu, pc, max_insns, &sc);
+ if (! new_vpc)
+ {
+ /* Leading '_' to avoid collision with mainloop.in. */
+ int _insn_count = 0;
+ SCACHE *orig_sc = sc;
+ SCACHE *_cti_sc = NULL;
+ int slice_insns = CPU_MAX_SLICE_INSNS (current_cpu);
+
+ /* First figure out how many instructions to compile.
+ MAX_INSNS is the size of the allocated buffer, which includes space
+ for before/after handlers if they're being used.
+ SLICE_INSNS is the maxinum number of real insns that can be
+ executed. Zero means "as many as we want". */
+ /* ??? max_insns is serving two incompatible roles.
+ 1) Number of slots available in scache buffer.
+ 2) Number of real insns to execute.
+ They're incompatible because there are virtual insns emitted too
+ (chain,cti-chain,before,after handlers). */
+
+ if (slice_insns == 1)
+ {
+ /* No need to worry about extra slots required for virtual insns
+ and parallel exec support because MAX_CHAIN_LENGTH is
+ guaranteed to be big enough to execute at least 1 insn! */
+ max_insns = 1;
+ }
+ else
+ {
+ /* Allow enough slop so that while compiling insns, if max_insns > 0
+ then there's guaranteed to be enough space to emit one real insn.
+ MAX_CHAIN_LENGTH is typically much longer than
+ the normal number of insns between cti's anyway. */
+ max_insns -= (1 /* one for the trailing chain insn */
+ + (FAST_P
+ ? 0
+ : (1 + MAX_PARALLEL_INSNS) /* before+after */)
+ + (MAX_PARALLEL_INSNS > 1
+ ? (MAX_PARALLEL_INSNS * 2)
+ : 0));
+
+ /* Account for before/after handlers. */
+ if (! FAST_P)
+ slice_insns *= 3;
+
+ if (slice_insns > 0
+ && slice_insns < max_insns)
+ max_insns = slice_insns;
+ }
+
+ new_vpc = sc;
+
+ /* SC,PC must be updated to point passed the last entry used.
+ SET_CTI_VPC must be called if pbb is terminated by a cti.
+ SET_INSN_COUNT must be called to record number of real insns in
+ pbb [could be computed by us of course, extra cpu but perhaps
+ negligible enough]. */
+
+/* begin extract-pbb */
+{
+ const IDESC *idesc;
+ int icount = 0;
+
+ while (max_insns > 0)
+ {
+ UHI insn = GETIMEMUHI (current_cpu, pc);
+
+ idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
+ SEM_SKIP_COMPILE (current_cpu, sc, 1);
+ ++sc;
+ --max_insns;
+ ++icount;
+ pc += idesc->length;
+
+ if (IDESC_CTI_P (idesc))
+ {
+ SET_CTI_VPC (sc - 1);
+
+ if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
+ {
+ USI insn = GETIMEMUHI (current_cpu, pc);
+ idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
+
+ if (IDESC_CTI_P (idesc) ||
+ CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_ILLSLOT))
+ {
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ sim_io_eprintf (CPU_STATE (current_cpu),
+ "malformed program, `%s' insn in delay slot\n",
+ CGEN_INSN_NAME (idesc->idata));
+ sim_engine_halt (sd, current_cpu, NULL, pc,
+ sim_stopped, SIM_SIGILL);
+ }
+ else
+ {
+ ++sc;
+ --max_insns;
+ ++icount;
+ pc += idesc->length;
+ }
+ }
+ break;
+ }
+ }
+
+ Finish:
+ SET_INSN_COUNT (icount);
+}
+/* end extract-pbb */
+
+ /* The last one is a pseudo-insn to link to the next chain.
+ It is also used to record the insn count for this chain. */
+ {
+ const IDESC *id;
+
+ /* Was pbb terminated by a cti? */
+ if (_cti_sc)
+ {
+ id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_CTI_CHAIN];
+ }
+ else
+ {
+ id = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_CHAIN];
+ }
+ SEM_SET_CODE (&sc->argbuf, id, FAST_P);
+ sc->argbuf.idesc = id;
+ sc->argbuf.addr = pc;
+ sc->argbuf.fields.chain.insn_count = _insn_count;
+ sc->argbuf.fields.chain.next = 0;
+ sc->argbuf.fields.chain.branch_target = 0;
+ ++sc;
+ }
+
+ /* Update the pointer to the next free entry, may not have used as
+ many entries as was asked for. */
+ CPU_SCACHE_NEXT_FREE (current_cpu) = sc;
+ /* Record length of chain if profiling.
+ This includes virtual insns since they count against
+ max_insns too. */
+ if (! FAST_P)
+ PROFILE_COUNT_SCACHE_CHAIN_LENGTH (current_cpu, sc - orig_sc);
+ }
+
+ return new_vpc;
+}
+
+/* Chain to the next block from a non-cti terminated previous block. */
+
+INLINE SEM_PC
+sh64_compact_pbb_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+
+ PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
+
+ SET_H_PC (abuf->addr);
+
+
+ /* If not running forever, exit back to main loop. */
+ if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
+ /* Also exit back to main loop if there's an event.
+ Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
+ at the "right" time, but then that was what was asked for.
+ There is no silver bullet for simulator engines.
+ ??? Clearly this needs a cleaner interface.
+ At present it's just so Ctrl-C works. */
+ || STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
+ CPU_RUNNING_P (current_cpu) = 0;
+
+ /* If chained to next block, go straight to it. */
+ if (abuf->fields.chain.next)
+ return abuf->fields.chain.next;
+ /* See if next block has already been compiled. */
+ abuf->fields.chain.next = scache_lookup (current_cpu, abuf->addr);
+ if (abuf->fields.chain.next)
+ return abuf->fields.chain.next;
+ /* Nope, so next insn is a virtual insn to invoke the compiler
+ (begin a pbb). */
+ return CPU_SCACHE_PBB_BEGIN (current_cpu);
+}
+
+/* Chain to the next block from a cti terminated previous block.
+ BR_TYPE indicates whether the branch was taken and whether we can cache
+ the vpc of the branch target.
+ NEW_PC is the target's branch address, and is only valid if
+ BR_TYPE != SEM_BRANCH_UNTAKEN. */
+
+INLINE SEM_PC
+sh64_compact_pbb_cti_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg,
+ SEM_BRANCH_TYPE br_type, PCADDR new_pc)
+{
+ SEM_PC *new_vpc_ptr;
+
+ PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
+
+ /* If we have switched ISAs, exit back to main loop.
+ Set idesc to 0 to cause the engine to point to the right insn table. */
+ if (new_pc & 1)
+ {
+ /* Switch to SHmedia. */
+ CPU_IDESC_SEM_INIT_P (current_cpu) = 0;
+ CPU_RUNNING_P (current_cpu) = 0;
+ }
+
+ /* If not running forever, exit back to main loop. */
+ if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
+ /* Also exit back to main loop if there's an event.
+ Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
+ at the "right" time, but then that was what was asked for.
+ There is no silver bullet for simulator engines.
+ ??? Clearly this needs a cleaner interface.
+ At present it's just so Ctrl-C works. */
+ || STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
+ CPU_RUNNING_P (current_cpu) = 0;
+
+ /* Restart compiler if we branched to an uncacheable address
+ (e.g. "j reg"). */
+ if (br_type == SEM_BRANCH_UNCACHEABLE)
+ {
+ SET_H_PC (new_pc);
+ return CPU_SCACHE_PBB_BEGIN (current_cpu);
+ }
+
+ /* If branch wasn't taken, update the pc and set BR_ADDR_PTR to our
+ next chain ptr. */
+ if (br_type == SEM_BRANCH_UNTAKEN)
+ {
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ new_pc = abuf->addr;
+ SET_H_PC (new_pc);
+ new_vpc_ptr = &abuf->fields.chain.next;
+ }
+ else
+ {
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ SET_H_PC (new_pc);
+ new_vpc_ptr = &abuf->fields.chain.branch_target;
+ }
+
+ /* If chained to next block, go straight to it. */
+ if (*new_vpc_ptr)
+ return *new_vpc_ptr;
+ /* See if next block has already been compiled. */
+ *new_vpc_ptr = scache_lookup (current_cpu, new_pc);
+ if (*new_vpc_ptr)
+ return *new_vpc_ptr;
+ /* Nope, so next insn is a virtual insn to invoke the compiler
+ (begin a pbb). */
+ return CPU_SCACHE_PBB_BEGIN (current_cpu);
+}
+
+/* x-before handler.
+ This is called before each insn. */
+
+void
+sh64_compact_pbb_before (SIM_CPU *current_cpu, SCACHE *sc)
+{
+ SEM_ARG sem_arg = sc;
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int first_p = abuf->fields.before.first_p;
+ const ARGBUF *cur_abuf = SEM_ARGBUF (sc + 1);
+ const IDESC *cur_idesc = cur_abuf->idesc;
+ PCADDR pc = cur_abuf->addr;
+
+ if (ARGBUF_PROFILE_P (cur_abuf))
+ PROFILE_COUNT_INSN (current_cpu, pc, cur_idesc->num);
+
+ /* If this isn't the first insn, finish up the previous one. */
+
+ if (! first_p)
+ {
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ const SEM_ARG prev_sem_arg = sc - 1;
+ const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
+ const IDESC *prev_idesc = prev_abuf->idesc;
+ int cycles;
+
+ /* ??? May want to measure all insns if doing insn tracing. */
+ if (ARGBUF_PROFILE_P (prev_abuf))
+ {
+ cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
+ sh64_compact_model_insn_after (current_cpu, 0 /*last_p*/, cycles);
+ }
+ }
+
+ TRACE_INSN_FINI (current_cpu, cur_abuf, 0 /*last_p*/);
+ }
+
+ /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (cur_abuf))
+ sh64_compact_model_insn_before (current_cpu, first_p);
+
+ TRACE_INSN_INIT (current_cpu, cur_abuf, first_p);
+ TRACE_INSN (current_cpu, cur_idesc->idata, cur_abuf, pc);
+}
+
+/* x-after handler.
+ This is called after a serial insn or at the end of a group of parallel
+ insns. */
+
+void
+sh64_compact_pbb_after (SIM_CPU *current_cpu, SCACHE *sc)
+{
+ SEM_ARG sem_arg = sc;
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ const SEM_ARG prev_sem_arg = sc - 1;
+ const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
+
+ /* ??? May want to measure all insns if doing insn tracing. */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (prev_abuf))
+ {
+ const IDESC *prev_idesc = prev_abuf->idesc;
+ int cycles;
+
+ cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
+ sh64_compact_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
+ }
+ TRACE_INSN_FINI (current_cpu, prev_abuf, 1 /*last_p*/);
+}
+
+#define FAST_P 0
+
+void
+sh64_compact_engine_run_full (SIM_CPU *current_cpu)
+{
+ SIM_DESC current_state = CPU_STATE (current_cpu);
+ SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
+ /* virtual program counter */
+ SEM_PC vpc;
+#if WITH_SEM_SWITCH_FULL
+ /* For communication between cti's and cti-chain. */
+ SEM_BRANCH_TYPE pbb_br_type;
+ PCADDR pbb_br_npc;
+#endif
+
+
+ if (! CPU_IDESC_SEM_INIT_P (current_cpu))
+ {
+ /* ??? 'twould be nice to move this up a level and only call it once.
+ On the other hand, in the "let's go fast" case the test is only done
+ once per pbb (since we only return to the main loop at the end of
+ a pbb). And in the "let's run until we're done" case we don't return
+ until the program exits. */
+
+#if WITH_SEM_SWITCH_FULL
+#if defined (__GNUC__)
+/* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
+#define DEFINE_LABELS
+#include "sem-compact-switch.c"
+#endif
+#else
+ sh64_compact_sem_init_idesc_table (current_cpu);
+#endif
+
+ /* Initialize the "begin (compile) a pbb" virtual insn. */
+ vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
+ SEM_SET_FULL_CODE (SEM_ARGBUF (vpc),
+ & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEGIN]);
+ vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEGIN];
+
+ CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
+ }
+
+ CPU_RUNNING_P (current_cpu) = 1;
+ /* ??? In the case where we're returning to the main loop after every
+ pbb we don't want to call pbb_begin each time (which hashes on the pc
+ and does a table lookup). A way to speed this up is to save vpc
+ between calls. */
+ vpc = sh64_compact_pbb_begin (current_cpu, FAST_P);
+
+ do
+ {
+/* begin full-exec-pbb */
+{
+#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
+#define DEFINE_SWITCH
+#include "sem-compact-switch.c"
+#else
+ vpc = execute (current_cpu, vpc, FAST_P);
+#endif
+}
+/* end full-exec-pbb */
+ }
+ while (CPU_RUNNING_P (current_cpu));
+}
+
+#undef FAST_P
+
+
+#define FAST_P 1
+
+void
+sh64_compact_engine_run_fast (SIM_CPU *current_cpu)
+{
+ SIM_DESC current_state = CPU_STATE (current_cpu);
+ SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
+ /* virtual program counter */
+ SEM_PC vpc;
+#if WITH_SEM_SWITCH_FAST
+ /* For communication between cti's and cti-chain. */
+ SEM_BRANCH_TYPE pbb_br_type;
+ PCADDR pbb_br_npc;
+#endif
+
+
+ if (! CPU_IDESC_SEM_INIT_P (current_cpu))
+ {
+ /* ??? 'twould be nice to move this up a level and only call it once.
+ On the other hand, in the "let's go fast" case the test is only done
+ once per pbb (since we only return to the main loop at the end of
+ a pbb). And in the "let's run until we're done" case we don't return
+ until the program exits. */
+
+#if WITH_SEM_SWITCH_FAST
+#if defined (__GNUC__)
+/* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
+#define DEFINE_LABELS
+#include "sem-compact-switch.c"
+#endif
+#else
+ sh64_compact_semf_init_idesc_table (current_cpu);
+#endif
+
+ /* Initialize the "begin (compile) a pbb" virtual insn. */
+ vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
+ SEM_SET_FAST_CODE (SEM_ARGBUF (vpc),
+ & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEGIN]);
+ vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [SH64_COMPACT_INSN_X_BEGIN];
+
+ CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
+ }
+
+ CPU_RUNNING_P (current_cpu) = 1;
+ /* ??? In the case where we're returning to the main loop after every
+ pbb we don't want to call pbb_begin each time (which hashes on the pc
+ and does a table lookup). A way to speed this up is to save vpc
+ between calls. */
+ vpc = sh64_compact_pbb_begin (current_cpu, FAST_P);
+
+ do
+ {
+/* begin fast-exec-pbb */
+{
+#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
+#define DEFINE_SWITCH
+#include "sem-compact-switch.c"
+#else
+ vpc = execute (current_cpu, vpc, FAST_P);
+#endif
+}
+/* end fast-exec-pbb */
+ }
+ while (CPU_RUNNING_P (current_cpu));
+}
+
+#undef FAST_P
+
--- /dev/null
+/* This file is generated by the genmloop script. DO NOT EDIT! */
+
+/* Enable switch() support in cgen headers. */
+#define SEM_IN_SWITCH
+
+#define WANT_CPU sh64
+#define WANT_CPU_SH64
+
+#include "sim-main.h"
+#include "bfd.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+#include "sim-assert.h"
+
+/* Fill in the administrative ARGBUF fields required by all insns,
+ virtual and real. */
+
+static INLINE void
+sh64_media_fill_argbuf (const SIM_CPU *cpu, ARGBUF *abuf, const IDESC *idesc,
+ PCADDR pc, int fast_p)
+{
+#if WITH_SCACHE
+ SEM_SET_CODE (abuf, idesc, fast_p);
+ ARGBUF_ADDR (abuf) = pc;
+#endif
+ ARGBUF_IDESC (abuf) = idesc;
+}
+
+/* Fill in tracing/profiling fields of an ARGBUF. */
+
+static INLINE void
+sh64_media_fill_argbuf_tp (const SIM_CPU *cpu, ARGBUF *abuf,
+ int trace_p, int profile_p)
+{
+ ARGBUF_TRACE_P (abuf) = trace_p;
+ ARGBUF_PROFILE_P (abuf) = profile_p;
+}
+
+#if WITH_SCACHE_PBB
+
+/* Emit the "x-before" handler.
+ x-before is emitted before each insn (serial or parallel).
+ This is as opposed to x-after which is only emitted at the end of a group
+ of parallel insns. */
+
+static INLINE void
+sh64_media_emit_before (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc, int first_p)
+{
+ ARGBUF *abuf = &sc[0].argbuf;
+ const IDESC *id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEFORE];
+
+ abuf->fields.before.first_p = first_p;
+ sh64_media_fill_argbuf (current_cpu, abuf, id, pc, 0);
+ /* no need to set trace_p,profile_p */
+}
+
+/* Emit the "x-after" handler.
+ x-after is emitted after a serial insn or at the end of a group of
+ parallel insns. */
+
+static INLINE void
+sh64_media_emit_after (SIM_CPU *current_cpu, SCACHE *sc, PCADDR pc)
+{
+ ARGBUF *abuf = &sc[0].argbuf;
+ const IDESC *id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_AFTER];
+
+ sh64_media_fill_argbuf (current_cpu, abuf, id, pc, 0);
+ /* no need to set trace_p,profile_p */
+}
+
+#endif /* WITH_SCACHE_PBB */
+
+
+static INLINE const IDESC *
+extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
+ int fast_p)
+{
+ const IDESC *id = sh64_media_decode (current_cpu, pc, insn, insn, abuf);
+
+ sh64_media_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+ if (! fast_p)
+ {
+ int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+ int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+ sh64_media_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
+ }
+ return id;
+}
+
+static INLINE SEM_PC
+execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
+{
+ SEM_PC vpc;
+
+ if (fast_p)
+ {
+#if ! WITH_SEM_SWITCH_FAST
+#if WITH_SCACHE
+ vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
+#else
+ vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
+#endif
+#else
+ abort ();
+#endif /* WITH_SEM_SWITCH_FAST */
+ }
+ else
+ {
+#if ! WITH_SEM_SWITCH_FULL
+ ARGBUF *abuf = &sc->argbuf;
+ const IDESC *idesc = abuf->idesc;
+#if WITH_SCACHE_PBB
+ int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
+#else
+ int virtual_p = 0;
+#endif
+
+ if (! virtual_p)
+ {
+ /* FIXME: call x-before */
+ if (ARGBUF_PROFILE_P (abuf))
+ PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
+ /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (abuf))
+ sh64_media_model_insn_before (current_cpu, 1 /*first_p*/);
+ TRACE_INSN_INIT (current_cpu, abuf, 1);
+ TRACE_INSN (current_cpu, idesc->idata,
+ (const struct argbuf *) abuf, abuf->addr);
+ }
+#if WITH_SCACHE
+ vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
+#else
+ vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
+#endif
+ if (! virtual_p)
+ {
+ /* FIXME: call x-after */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (abuf))
+ {
+ int cycles;
+
+ cycles = (*idesc->timing->model_fn) (current_cpu, sc);
+ sh64_media_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
+ }
+ TRACE_INSN_FINI (current_cpu, abuf, 1);
+ }
+#else
+ abort ();
+#endif /* WITH_SEM_SWITCH_FULL */
+ }
+
+ return vpc;
+}
+
+
+/* Record address of cti terminating a pbb. */
+#define SET_CTI_VPC(sc) do { _cti_sc = (sc); } while (0)
+/* Record number of [real] insns in pbb. */
+#define SET_INSN_COUNT(n) do { _insn_count = (n); } while (0)
+
+/* Fetch and extract a pseudo-basic-block.
+ FAST_P is non-zero if no tracing/profiling/etc. is wanted. */
+
+INLINE SEM_PC
+sh64_media_pbb_begin (SIM_CPU *current_cpu, int FAST_P)
+{
+ SEM_PC new_vpc;
+ PCADDR pc;
+ SCACHE *sc;
+ int max_insns = CPU_SCACHE_MAX_CHAIN_LENGTH (current_cpu);
+
+ pc = GET_H_PC ();
+
+ new_vpc = scache_lookup_or_alloc (current_cpu, pc, max_insns, &sc);
+ if (! new_vpc)
+ {
+ /* Leading '_' to avoid collision with mainloop.in. */
+ int _insn_count = 0;
+ SCACHE *orig_sc = sc;
+ SCACHE *_cti_sc = NULL;
+ int slice_insns = CPU_MAX_SLICE_INSNS (current_cpu);
+
+ /* First figure out how many instructions to compile.
+ MAX_INSNS is the size of the allocated buffer, which includes space
+ for before/after handlers if they're being used.
+ SLICE_INSNS is the maxinum number of real insns that can be
+ executed. Zero means "as many as we want". */
+ /* ??? max_insns is serving two incompatible roles.
+ 1) Number of slots available in scache buffer.
+ 2) Number of real insns to execute.
+ They're incompatible because there are virtual insns emitted too
+ (chain,cti-chain,before,after handlers). */
+
+ if (slice_insns == 1)
+ {
+ /* No need to worry about extra slots required for virtual insns
+ and parallel exec support because MAX_CHAIN_LENGTH is
+ guaranteed to be big enough to execute at least 1 insn! */
+ max_insns = 1;
+ }
+ else
+ {
+ /* Allow enough slop so that while compiling insns, if max_insns > 0
+ then there's guaranteed to be enough space to emit one real insn.
+ MAX_CHAIN_LENGTH is typically much longer than
+ the normal number of insns between cti's anyway. */
+ max_insns -= (1 /* one for the trailing chain insn */
+ + (FAST_P
+ ? 0
+ : (1 + MAX_PARALLEL_INSNS) /* before+after */)
+ + (MAX_PARALLEL_INSNS > 1
+ ? (MAX_PARALLEL_INSNS * 2)
+ : 0));
+
+ /* Account for before/after handlers. */
+ if (! FAST_P)
+ slice_insns *= 3;
+
+ if (slice_insns > 0
+ && slice_insns < max_insns)
+ max_insns = slice_insns;
+ }
+
+ new_vpc = sc;
+
+ /* SC,PC must be updated to point passed the last entry used.
+ SET_CTI_VPC must be called if pbb is terminated by a cti.
+ SET_INSN_COUNT must be called to record number of real insns in
+ pbb [could be computed by us of course, extra cpu but perhaps
+ negligible enough]. */
+
+/* begin extract-pbb */
+{
+ const IDESC *idesc;
+ int icount = 0;
+
+ while (max_insns > 0)
+ {
+ USI insn = GETIMEMUSI (current_cpu, pc);
+
+ idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
+ SEM_SKIP_COMPILE (current_cpu, sc, 1);
+ ++sc;
+ --max_insns;
+ ++icount;
+ pc += idesc->length;
+
+ if (IDESC_CTI_P (idesc))
+ {
+ SET_CTI_VPC (sc - 1);
+
+ if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
+ {
+ USI insn = GETIMEMUSI (current_cpu, pc);
+ idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
+
+ ++sc;
+ --max_insns;
+ ++icount;
+ pc += idesc->length;
+ }
+ break;
+ }
+ }
+
+ Finish:
+ SET_INSN_COUNT (icount);
+}
+/* end extract-pbb */
+
+ /* The last one is a pseudo-insn to link to the next chain.
+ It is also used to record the insn count for this chain. */
+ {
+ const IDESC *id;
+
+ /* Was pbb terminated by a cti? */
+ if (_cti_sc)
+ {
+ id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_CTI_CHAIN];
+ }
+ else
+ {
+ id = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_CHAIN];
+ }
+ SEM_SET_CODE (&sc->argbuf, id, FAST_P);
+ sc->argbuf.idesc = id;
+ sc->argbuf.addr = pc;
+ sc->argbuf.fields.chain.insn_count = _insn_count;
+ sc->argbuf.fields.chain.next = 0;
+ sc->argbuf.fields.chain.branch_target = 0;
+ ++sc;
+ }
+
+ /* Update the pointer to the next free entry, may not have used as
+ many entries as was asked for. */
+ CPU_SCACHE_NEXT_FREE (current_cpu) = sc;
+ /* Record length of chain if profiling.
+ This includes virtual insns since they count against
+ max_insns too. */
+ if (! FAST_P)
+ PROFILE_COUNT_SCACHE_CHAIN_LENGTH (current_cpu, sc - orig_sc);
+ }
+
+ return new_vpc;
+}
+
+/* Chain to the next block from a non-cti terminated previous block. */
+
+INLINE SEM_PC
+sh64_media_pbb_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+
+ PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
+
+ SET_H_PC (abuf->addr | 1);
+
+ /* If not running forever, exit back to main loop. */
+ if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
+ /* Also exit back to main loop if there's an event.
+ Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
+ at the "right" time, but then that was what was asked for.
+ There is no silver bullet for simulator engines.
+ ??? Clearly this needs a cleaner interface.
+ At present it's just so Ctrl-C works. */
+ || STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
+ CPU_RUNNING_P (current_cpu) = 0;
+
+ /* If chained to next block, go straight to it. */
+ if (abuf->fields.chain.next)
+ return abuf->fields.chain.next;
+ /* See if next block has already been compiled. */
+ abuf->fields.chain.next = scache_lookup (current_cpu, abuf->addr);
+ if (abuf->fields.chain.next)
+ return abuf->fields.chain.next;
+ /* Nope, so next insn is a virtual insn to invoke the compiler
+ (begin a pbb). */
+ return CPU_SCACHE_PBB_BEGIN (current_cpu);
+}
+
+/* Chain to the next block from a cti terminated previous block.
+ BR_TYPE indicates whether the branch was taken and whether we can cache
+ the vpc of the branch target.
+ NEW_PC is the target's branch address, and is only valid if
+ BR_TYPE != SEM_BRANCH_UNTAKEN. */
+
+INLINE SEM_PC
+sh64_media_pbb_cti_chain (SIM_CPU *current_cpu, SEM_ARG sem_arg,
+ SEM_BRANCH_TYPE br_type, PCADDR new_pc)
+{
+ SEM_PC *new_vpc_ptr;
+
+ PBB_UPDATE_INSN_COUNT (current_cpu, sem_arg);
+
+ /* If we have switched ISAs, exit back to main loop.
+ Set idesc to 0 to cause the engine to point to the right insn table. */
+ if ((new_pc & 1) == 0)
+ {
+ /* Switch to SHcompact. */
+ CPU_IDESC_SEM_INIT_P (current_cpu) = 0;
+ CPU_RUNNING_P (current_cpu) = 0;
+ }
+
+ /* If not running forever, exit back to main loop. */
+ if (CPU_MAX_SLICE_INSNS (current_cpu) != 0
+ /* Also exit back to main loop if there's an event.
+ Note that if CPU_MAX_SLICE_INSNS != 1, events won't get processed
+ at the "right" time, but then that was what was asked for.
+ There is no silver bullet for simulator engines.
+ ??? Clearly this needs a cleaner interface.
+ At present it's just so Ctrl-C works. */
+ || STATE_EVENTS (CPU_STATE (current_cpu))->work_pending)
+ CPU_RUNNING_P (current_cpu) = 0;
+
+ /* Restart compiler if we branched to an uncacheable address
+ (e.g. "j reg"). */
+ if (br_type == SEM_BRANCH_UNCACHEABLE)
+ {
+ SET_H_PC (new_pc);
+ return CPU_SCACHE_PBB_BEGIN (current_cpu);
+ }
+
+ /* If branch wasn't taken, update the pc and set BR_ADDR_PTR to our
+ next chain ptr. */
+ if (br_type == SEM_BRANCH_UNTAKEN)
+ {
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ new_pc = abuf->addr;
+ /* Set bit 0 to stay in SHmedia mode. */
+ SET_H_PC (new_pc | 1);
+ new_vpc_ptr = &abuf->fields.chain.next;
+ }
+ else
+ {
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ SET_H_PC (new_pc);
+ new_vpc_ptr = &abuf->fields.chain.branch_target;
+ }
+
+ /* If chained to next block, go straight to it. */
+ if (*new_vpc_ptr)
+ return *new_vpc_ptr;
+ /* See if next block has already been compiled. */
+ *new_vpc_ptr = scache_lookup (current_cpu, new_pc);
+ if (*new_vpc_ptr)
+ return *new_vpc_ptr;
+ /* Nope, so next insn is a virtual insn to invoke the compiler
+ (begin a pbb). */
+ return CPU_SCACHE_PBB_BEGIN (current_cpu);
+}
+
+/* x-before handler.
+ This is called before each insn. */
+
+void
+sh64_media_pbb_before (SIM_CPU *current_cpu, SCACHE *sc)
+{
+ SEM_ARG sem_arg = sc;
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int first_p = abuf->fields.before.first_p;
+ const ARGBUF *cur_abuf = SEM_ARGBUF (sc + 1);
+ const IDESC *cur_idesc = cur_abuf->idesc;
+ PCADDR pc = cur_abuf->addr;
+
+ if (ARGBUF_PROFILE_P (cur_abuf))
+ PROFILE_COUNT_INSN (current_cpu, pc, cur_idesc->num);
+
+ /* If this isn't the first insn, finish up the previous one. */
+
+ if (! first_p)
+ {
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ const SEM_ARG prev_sem_arg = sc - 1;
+ const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
+ const IDESC *prev_idesc = prev_abuf->idesc;
+ int cycles;
+
+ /* ??? May want to measure all insns if doing insn tracing. */
+ if (ARGBUF_PROFILE_P (prev_abuf))
+ {
+ cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
+ sh64_media_model_insn_after (current_cpu, 0 /*last_p*/, cycles);
+ }
+ }
+
+ TRACE_INSN_FINI (current_cpu, cur_abuf, 0 /*last_p*/);
+ }
+
+ /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (cur_abuf))
+ sh64_media_model_insn_before (current_cpu, first_p);
+
+ TRACE_INSN_INIT (current_cpu, cur_abuf, first_p);
+ TRACE_INSN (current_cpu, cur_idesc->idata, cur_abuf, pc);
+}
+
+/* x-after handler.
+ This is called after a serial insn or at the end of a group of parallel
+ insns. */
+
+void
+sh64_media_pbb_after (SIM_CPU *current_cpu, SCACHE *sc)
+{
+ SEM_ARG sem_arg = sc;
+ const ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ const SEM_ARG prev_sem_arg = sc - 1;
+ const ARGBUF *prev_abuf = SEM_ARGBUF (prev_sem_arg);
+
+ /* ??? May want to measure all insns if doing insn tracing. */
+ if (PROFILE_MODEL_P (current_cpu)
+ && ARGBUF_PROFILE_P (prev_abuf))
+ {
+ const IDESC *prev_idesc = prev_abuf->idesc;
+ int cycles;
+
+ cycles = (*prev_idesc->timing->model_fn) (current_cpu, prev_sem_arg);
+ sh64_media_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
+ }
+ TRACE_INSN_FINI (current_cpu, prev_abuf, 1 /*last_p*/);
+}
+
+#define FAST_P 0
+
+void
+sh64_media_engine_run_full (SIM_CPU *current_cpu)
+{
+ SIM_DESC current_state = CPU_STATE (current_cpu);
+ SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
+ /* virtual program counter */
+ SEM_PC vpc;
+#if WITH_SEM_SWITCH_FULL
+ /* For communication between cti's and cti-chain. */
+ SEM_BRANCH_TYPE pbb_br_type;
+ PCADDR pbb_br_npc;
+#endif
+
+
+ if (! CPU_IDESC_SEM_INIT_P (current_cpu))
+ {
+ /* ??? 'twould be nice to move this up a level and only call it once.
+ On the other hand, in the "let's go fast" case the test is only done
+ once per pbb (since we only return to the main loop at the end of
+ a pbb). And in the "let's run until we're done" case we don't return
+ until the program exits. */
+
+#if WITH_SEM_SWITCH_FULL
+#if defined (__GNUC__)
+/* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
+#define DEFINE_LABELS
+#include "sem-media-switch.c"
+#endif
+#else
+ sh64_media_sem_init_idesc_table (current_cpu);
+#endif
+
+ /* Initialize the "begin (compile) a pbb" virtual insn. */
+ vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
+ SEM_SET_FULL_CODE (SEM_ARGBUF (vpc),
+ & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEGIN]);
+ vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEGIN];
+
+ CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
+ }
+
+ CPU_RUNNING_P (current_cpu) = 1;
+ /* ??? In the case where we're returning to the main loop after every
+ pbb we don't want to call pbb_begin each time (which hashes on the pc
+ and does a table lookup). A way to speed this up is to save vpc
+ between calls. */
+ vpc = sh64_media_pbb_begin (current_cpu, FAST_P);
+
+ do
+ {
+/* begin full-exec-pbb */
+{
+#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
+#define DEFINE_SWITCH
+#define WITH_ISA_COMPACT
+#include "sem-media-switch.c"
+#else
+ vpc = execute (current_cpu, vpc, FAST_P);
+#endif
+}
+/* end full-exec-pbb */
+ }
+ while (CPU_RUNNING_P (current_cpu));
+}
+
+#undef FAST_P
+
+
+#define FAST_P 1
+
+void
+sh64_media_engine_run_fast (SIM_CPU *current_cpu)
+{
+ SIM_DESC current_state = CPU_STATE (current_cpu);
+ SCACHE *scache = CPU_SCACHE_CACHE (current_cpu);
+ /* virtual program counter */
+ SEM_PC vpc;
+#if WITH_SEM_SWITCH_FAST
+ /* For communication between cti's and cti-chain. */
+ SEM_BRANCH_TYPE pbb_br_type;
+ PCADDR pbb_br_npc;
+#endif
+
+
+ if (! CPU_IDESC_SEM_INIT_P (current_cpu))
+ {
+ /* ??? 'twould be nice to move this up a level and only call it once.
+ On the other hand, in the "let's go fast" case the test is only done
+ once per pbb (since we only return to the main loop at the end of
+ a pbb). And in the "let's run until we're done" case we don't return
+ until the program exits. */
+
+#if WITH_SEM_SWITCH_FAST
+#if defined (__GNUC__)
+/* ??? Later maybe paste sem-switch.c in when building mainloop.c. */
+#define DEFINE_LABELS
+#include "sem-media-switch.c"
+#endif
+#else
+ sh64_media_semf_init_idesc_table (current_cpu);
+#endif
+
+ /* Initialize the "begin (compile) a pbb" virtual insn. */
+ vpc = CPU_SCACHE_PBB_BEGIN (current_cpu);
+ SEM_SET_FAST_CODE (SEM_ARGBUF (vpc),
+ & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEGIN]);
+ vpc->argbuf.idesc = & CPU_IDESC (current_cpu) [SH64_MEDIA_INSN_X_BEGIN];
+
+ CPU_IDESC_SEM_INIT_P (current_cpu) = 1;
+ }
+
+ CPU_RUNNING_P (current_cpu) = 1;
+ /* ??? In the case where we're returning to the main loop after every
+ pbb we don't want to call pbb_begin each time (which hashes on the pc
+ and does a table lookup). A way to speed this up is to save vpc
+ between calls. */
+ vpc = sh64_media_pbb_begin (current_cpu, FAST_P);
+
+ do
+ {
+/* begin fast-exec-pbb */
+{
+#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
+#define DEFINE_SWITCH
+#define WITH_ISA_COMPACT
+#include "sem-media-switch.c"
+#else
+ vpc = execute (current_cpu, vpc, FAST_P);
+#endif
+}
+/* end fast-exec-pbb */
+ }
+ while (CPU_RUNNING_P (current_cpu));
+}
+
+#undef FAST_P
+
--- /dev/null
+/* Simulator instruction semantics for sh64.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifdef DEFINE_LABELS
+
+ /* The labels have the case they have because the enum of insn types
+ is all uppercase and in the non-stdc case the insn symbol is built
+ into the enum name. */
+
+ static struct {
+ int index;
+ void *label;
+ } labels[] = {
+ { SH64_COMPACT_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
+ { SH64_COMPACT_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
+ { SH64_COMPACT_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
+ { SH64_COMPACT_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
+ { SH64_COMPACT_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
+ { SH64_COMPACT_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
+ { SH64_COMPACT_INSN_ADD_COMPACT, && case_sem_INSN_ADD_COMPACT },
+ { SH64_COMPACT_INSN_ADDI_COMPACT, && case_sem_INSN_ADDI_COMPACT },
+ { SH64_COMPACT_INSN_ADDC_COMPACT, && case_sem_INSN_ADDC_COMPACT },
+ { SH64_COMPACT_INSN_ADDV_COMPACT, && case_sem_INSN_ADDV_COMPACT },
+ { SH64_COMPACT_INSN_AND_COMPACT, && case_sem_INSN_AND_COMPACT },
+ { SH64_COMPACT_INSN_ANDI_COMPACT, && case_sem_INSN_ANDI_COMPACT },
+ { SH64_COMPACT_INSN_ANDB_COMPACT, && case_sem_INSN_ANDB_COMPACT },
+ { SH64_COMPACT_INSN_BF_COMPACT, && case_sem_INSN_BF_COMPACT },
+ { SH64_COMPACT_INSN_BFS_COMPACT, && case_sem_INSN_BFS_COMPACT },
+ { SH64_COMPACT_INSN_BRA_COMPACT, && case_sem_INSN_BRA_COMPACT },
+ { SH64_COMPACT_INSN_BRAF_COMPACT, && case_sem_INSN_BRAF_COMPACT },
+ { SH64_COMPACT_INSN_BRK_COMPACT, && case_sem_INSN_BRK_COMPACT },
+ { SH64_COMPACT_INSN_BSR_COMPACT, && case_sem_INSN_BSR_COMPACT },
+ { SH64_COMPACT_INSN_BSRF_COMPACT, && case_sem_INSN_BSRF_COMPACT },
+ { SH64_COMPACT_INSN_BT_COMPACT, && case_sem_INSN_BT_COMPACT },
+ { SH64_COMPACT_INSN_BTS_COMPACT, && case_sem_INSN_BTS_COMPACT },
+ { SH64_COMPACT_INSN_CLRMAC_COMPACT, && case_sem_INSN_CLRMAC_COMPACT },
+ { SH64_COMPACT_INSN_CLRS_COMPACT, && case_sem_INSN_CLRS_COMPACT },
+ { SH64_COMPACT_INSN_CLRT_COMPACT, && case_sem_INSN_CLRT_COMPACT },
+ { SH64_COMPACT_INSN_CMPEQ_COMPACT, && case_sem_INSN_CMPEQ_COMPACT },
+ { SH64_COMPACT_INSN_CMPEQI_COMPACT, && case_sem_INSN_CMPEQI_COMPACT },
+ { SH64_COMPACT_INSN_CMPGE_COMPACT, && case_sem_INSN_CMPGE_COMPACT },
+ { SH64_COMPACT_INSN_CMPGT_COMPACT, && case_sem_INSN_CMPGT_COMPACT },
+ { SH64_COMPACT_INSN_CMPHI_COMPACT, && case_sem_INSN_CMPHI_COMPACT },
+ { SH64_COMPACT_INSN_CMPHS_COMPACT, && case_sem_INSN_CMPHS_COMPACT },
+ { SH64_COMPACT_INSN_CMPPL_COMPACT, && case_sem_INSN_CMPPL_COMPACT },
+ { SH64_COMPACT_INSN_CMPPZ_COMPACT, && case_sem_INSN_CMPPZ_COMPACT },
+ { SH64_COMPACT_INSN_CMPSTR_COMPACT, && case_sem_INSN_CMPSTR_COMPACT },
+ { SH64_COMPACT_INSN_DIV0S_COMPACT, && case_sem_INSN_DIV0S_COMPACT },
+ { SH64_COMPACT_INSN_DIV0U_COMPACT, && case_sem_INSN_DIV0U_COMPACT },
+ { SH64_COMPACT_INSN_DIV1_COMPACT, && case_sem_INSN_DIV1_COMPACT },
+ { SH64_COMPACT_INSN_DMULSL_COMPACT, && case_sem_INSN_DMULSL_COMPACT },
+ { SH64_COMPACT_INSN_DMULUL_COMPACT, && case_sem_INSN_DMULUL_COMPACT },
+ { SH64_COMPACT_INSN_DT_COMPACT, && case_sem_INSN_DT_COMPACT },
+ { SH64_COMPACT_INSN_EXTSB_COMPACT, && case_sem_INSN_EXTSB_COMPACT },
+ { SH64_COMPACT_INSN_EXTSW_COMPACT, && case_sem_INSN_EXTSW_COMPACT },
+ { SH64_COMPACT_INSN_EXTUB_COMPACT, && case_sem_INSN_EXTUB_COMPACT },
+ { SH64_COMPACT_INSN_EXTUW_COMPACT, && case_sem_INSN_EXTUW_COMPACT },
+ { SH64_COMPACT_INSN_FABS_COMPACT, && case_sem_INSN_FABS_COMPACT },
+ { SH64_COMPACT_INSN_FADD_COMPACT, && case_sem_INSN_FADD_COMPACT },
+ { SH64_COMPACT_INSN_FCMPEQ_COMPACT, && case_sem_INSN_FCMPEQ_COMPACT },
+ { SH64_COMPACT_INSN_FCMPGT_COMPACT, && case_sem_INSN_FCMPGT_COMPACT },
+ { SH64_COMPACT_INSN_FCNVDS_COMPACT, && case_sem_INSN_FCNVDS_COMPACT },
+ { SH64_COMPACT_INSN_FCNVSD_COMPACT, && case_sem_INSN_FCNVSD_COMPACT },
+ { SH64_COMPACT_INSN_FDIV_COMPACT, && case_sem_INSN_FDIV_COMPACT },
+ { SH64_COMPACT_INSN_FIPR_COMPACT, && case_sem_INSN_FIPR_COMPACT },
+ { SH64_COMPACT_INSN_FLDS_COMPACT, && case_sem_INSN_FLDS_COMPACT },
+ { SH64_COMPACT_INSN_FLDI0_COMPACT, && case_sem_INSN_FLDI0_COMPACT },
+ { SH64_COMPACT_INSN_FLDI1_COMPACT, && case_sem_INSN_FLDI1_COMPACT },
+ { SH64_COMPACT_INSN_FLOAT_COMPACT, && case_sem_INSN_FLOAT_COMPACT },
+ { SH64_COMPACT_INSN_FMAC_COMPACT, && case_sem_INSN_FMAC_COMPACT },
+ { SH64_COMPACT_INSN_FMOV1_COMPACT, && case_sem_INSN_FMOV1_COMPACT },
+ { SH64_COMPACT_INSN_FMOV2_COMPACT, && case_sem_INSN_FMOV2_COMPACT },
+ { SH64_COMPACT_INSN_FMOV3_COMPACT, && case_sem_INSN_FMOV3_COMPACT },
+ { SH64_COMPACT_INSN_FMOV4_COMPACT, && case_sem_INSN_FMOV4_COMPACT },
+ { SH64_COMPACT_INSN_FMOV5_COMPACT, && case_sem_INSN_FMOV5_COMPACT },
+ { SH64_COMPACT_INSN_FMOV6_COMPACT, && case_sem_INSN_FMOV6_COMPACT },
+ { SH64_COMPACT_INSN_FMOV7_COMPACT, && case_sem_INSN_FMOV7_COMPACT },
+ { SH64_COMPACT_INSN_FMUL_COMPACT, && case_sem_INSN_FMUL_COMPACT },
+ { SH64_COMPACT_INSN_FNEG_COMPACT, && case_sem_INSN_FNEG_COMPACT },
+ { SH64_COMPACT_INSN_FRCHG_COMPACT, && case_sem_INSN_FRCHG_COMPACT },
+ { SH64_COMPACT_INSN_FSCHG_COMPACT, && case_sem_INSN_FSCHG_COMPACT },
+ { SH64_COMPACT_INSN_FSQRT_COMPACT, && case_sem_INSN_FSQRT_COMPACT },
+ { SH64_COMPACT_INSN_FSTS_COMPACT, && case_sem_INSN_FSTS_COMPACT },
+ { SH64_COMPACT_INSN_FSUB_COMPACT, && case_sem_INSN_FSUB_COMPACT },
+ { SH64_COMPACT_INSN_FTRC_COMPACT, && case_sem_INSN_FTRC_COMPACT },
+ { SH64_COMPACT_INSN_FTRV_COMPACT, && case_sem_INSN_FTRV_COMPACT },
+ { SH64_COMPACT_INSN_JMP_COMPACT, && case_sem_INSN_JMP_COMPACT },
+ { SH64_COMPACT_INSN_JSR_COMPACT, && case_sem_INSN_JSR_COMPACT },
+ { SH64_COMPACT_INSN_LDC_COMPACT, && case_sem_INSN_LDC_COMPACT },
+ { SH64_COMPACT_INSN_LDCL_COMPACT, && case_sem_INSN_LDCL_COMPACT },
+ { SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, && case_sem_INSN_LDS_FPSCR_COMPACT },
+ { SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, && case_sem_INSN_LDSL_FPSCR_COMPACT },
+ { SH64_COMPACT_INSN_LDS_FPUL_COMPACT, && case_sem_INSN_LDS_FPUL_COMPACT },
+ { SH64_COMPACT_INSN_LDSL_FPUL_COMPACT, && case_sem_INSN_LDSL_FPUL_COMPACT },
+ { SH64_COMPACT_INSN_LDS_MACH_COMPACT, && case_sem_INSN_LDS_MACH_COMPACT },
+ { SH64_COMPACT_INSN_LDSL_MACH_COMPACT, && case_sem_INSN_LDSL_MACH_COMPACT },
+ { SH64_COMPACT_INSN_LDS_MACL_COMPACT, && case_sem_INSN_LDS_MACL_COMPACT },
+ { SH64_COMPACT_INSN_LDSL_MACL_COMPACT, && case_sem_INSN_LDSL_MACL_COMPACT },
+ { SH64_COMPACT_INSN_LDS_PR_COMPACT, && case_sem_INSN_LDS_PR_COMPACT },
+ { SH64_COMPACT_INSN_LDSL_PR_COMPACT, && case_sem_INSN_LDSL_PR_COMPACT },
+ { SH64_COMPACT_INSN_MACL_COMPACT, && case_sem_INSN_MACL_COMPACT },
+ { SH64_COMPACT_INSN_MACW_COMPACT, && case_sem_INSN_MACW_COMPACT },
+ { SH64_COMPACT_INSN_MOV_COMPACT, && case_sem_INSN_MOV_COMPACT },
+ { SH64_COMPACT_INSN_MOVI_COMPACT, && case_sem_INSN_MOVI_COMPACT },
+ { SH64_COMPACT_INSN_MOVB1_COMPACT, && case_sem_INSN_MOVB1_COMPACT },
+ { SH64_COMPACT_INSN_MOVB2_COMPACT, && case_sem_INSN_MOVB2_COMPACT },
+ { SH64_COMPACT_INSN_MOVB3_COMPACT, && case_sem_INSN_MOVB3_COMPACT },
+ { SH64_COMPACT_INSN_MOVB4_COMPACT, && case_sem_INSN_MOVB4_COMPACT },
+ { SH64_COMPACT_INSN_MOVB5_COMPACT, && case_sem_INSN_MOVB5_COMPACT },
+ { SH64_COMPACT_INSN_MOVB6_COMPACT, && case_sem_INSN_MOVB6_COMPACT },
+ { SH64_COMPACT_INSN_MOVB7_COMPACT, && case_sem_INSN_MOVB7_COMPACT },
+ { SH64_COMPACT_INSN_MOVB8_COMPACT, && case_sem_INSN_MOVB8_COMPACT },
+ { SH64_COMPACT_INSN_MOVB9_COMPACT, && case_sem_INSN_MOVB9_COMPACT },
+ { SH64_COMPACT_INSN_MOVB10_COMPACT, && case_sem_INSN_MOVB10_COMPACT },
+ { SH64_COMPACT_INSN_MOVL1_COMPACT, && case_sem_INSN_MOVL1_COMPACT },
+ { SH64_COMPACT_INSN_MOVL2_COMPACT, && case_sem_INSN_MOVL2_COMPACT },
+ { SH64_COMPACT_INSN_MOVL3_COMPACT, && case_sem_INSN_MOVL3_COMPACT },
+ { SH64_COMPACT_INSN_MOVL4_COMPACT, && case_sem_INSN_MOVL4_COMPACT },
+ { SH64_COMPACT_INSN_MOVL5_COMPACT, && case_sem_INSN_MOVL5_COMPACT },
+ { SH64_COMPACT_INSN_MOVL6_COMPACT, && case_sem_INSN_MOVL6_COMPACT },
+ { SH64_COMPACT_INSN_MOVL7_COMPACT, && case_sem_INSN_MOVL7_COMPACT },
+ { SH64_COMPACT_INSN_MOVL8_COMPACT, && case_sem_INSN_MOVL8_COMPACT },
+ { SH64_COMPACT_INSN_MOVL9_COMPACT, && case_sem_INSN_MOVL9_COMPACT },
+ { SH64_COMPACT_INSN_MOVL10_COMPACT, && case_sem_INSN_MOVL10_COMPACT },
+ { SH64_COMPACT_INSN_MOVL11_COMPACT, && case_sem_INSN_MOVL11_COMPACT },
+ { SH64_COMPACT_INSN_MOVW1_COMPACT, && case_sem_INSN_MOVW1_COMPACT },
+ { SH64_COMPACT_INSN_MOVW2_COMPACT, && case_sem_INSN_MOVW2_COMPACT },
+ { SH64_COMPACT_INSN_MOVW3_COMPACT, && case_sem_INSN_MOVW3_COMPACT },
+ { SH64_COMPACT_INSN_MOVW4_COMPACT, && case_sem_INSN_MOVW4_COMPACT },
+ { SH64_COMPACT_INSN_MOVW5_COMPACT, && case_sem_INSN_MOVW5_COMPACT },
+ { SH64_COMPACT_INSN_MOVW6_COMPACT, && case_sem_INSN_MOVW6_COMPACT },
+ { SH64_COMPACT_INSN_MOVW7_COMPACT, && case_sem_INSN_MOVW7_COMPACT },
+ { SH64_COMPACT_INSN_MOVW8_COMPACT, && case_sem_INSN_MOVW8_COMPACT },
+ { SH64_COMPACT_INSN_MOVW9_COMPACT, && case_sem_INSN_MOVW9_COMPACT },
+ { SH64_COMPACT_INSN_MOVW10_COMPACT, && case_sem_INSN_MOVW10_COMPACT },
+ { SH64_COMPACT_INSN_MOVW11_COMPACT, && case_sem_INSN_MOVW11_COMPACT },
+ { SH64_COMPACT_INSN_MOVA_COMPACT, && case_sem_INSN_MOVA_COMPACT },
+ { SH64_COMPACT_INSN_MOVCAL_COMPACT, && case_sem_INSN_MOVCAL_COMPACT },
+ { SH64_COMPACT_INSN_MOVT_COMPACT, && case_sem_INSN_MOVT_COMPACT },
+ { SH64_COMPACT_INSN_MULL_COMPACT, && case_sem_INSN_MULL_COMPACT },
+ { SH64_COMPACT_INSN_MULSW_COMPACT, && case_sem_INSN_MULSW_COMPACT },
+ { SH64_COMPACT_INSN_MULUW_COMPACT, && case_sem_INSN_MULUW_COMPACT },
+ { SH64_COMPACT_INSN_NEG_COMPACT, && case_sem_INSN_NEG_COMPACT },
+ { SH64_COMPACT_INSN_NEGC_COMPACT, && case_sem_INSN_NEGC_COMPACT },
+ { SH64_COMPACT_INSN_NOP_COMPACT, && case_sem_INSN_NOP_COMPACT },
+ { SH64_COMPACT_INSN_NOT_COMPACT, && case_sem_INSN_NOT_COMPACT },
+ { SH64_COMPACT_INSN_OCBI_COMPACT, && case_sem_INSN_OCBI_COMPACT },
+ { SH64_COMPACT_INSN_OCBP_COMPACT, && case_sem_INSN_OCBP_COMPACT },
+ { SH64_COMPACT_INSN_OCBWB_COMPACT, && case_sem_INSN_OCBWB_COMPACT },
+ { SH64_COMPACT_INSN_OR_COMPACT, && case_sem_INSN_OR_COMPACT },
+ { SH64_COMPACT_INSN_ORI_COMPACT, && case_sem_INSN_ORI_COMPACT },
+ { SH64_COMPACT_INSN_ORB_COMPACT, && case_sem_INSN_ORB_COMPACT },
+ { SH64_COMPACT_INSN_PREF_COMPACT, && case_sem_INSN_PREF_COMPACT },
+ { SH64_COMPACT_INSN_ROTCL_COMPACT, && case_sem_INSN_ROTCL_COMPACT },
+ { SH64_COMPACT_INSN_ROTCR_COMPACT, && case_sem_INSN_ROTCR_COMPACT },
+ { SH64_COMPACT_INSN_ROTL_COMPACT, && case_sem_INSN_ROTL_COMPACT },
+ { SH64_COMPACT_INSN_ROTR_COMPACT, && case_sem_INSN_ROTR_COMPACT },
+ { SH64_COMPACT_INSN_RTS_COMPACT, && case_sem_INSN_RTS_COMPACT },
+ { SH64_COMPACT_INSN_SETS_COMPACT, && case_sem_INSN_SETS_COMPACT },
+ { SH64_COMPACT_INSN_SETT_COMPACT, && case_sem_INSN_SETT_COMPACT },
+ { SH64_COMPACT_INSN_SHAD_COMPACT, && case_sem_INSN_SHAD_COMPACT },
+ { SH64_COMPACT_INSN_SHAL_COMPACT, && case_sem_INSN_SHAL_COMPACT },
+ { SH64_COMPACT_INSN_SHAR_COMPACT, && case_sem_INSN_SHAR_COMPACT },
+ { SH64_COMPACT_INSN_SHLD_COMPACT, && case_sem_INSN_SHLD_COMPACT },
+ { SH64_COMPACT_INSN_SHLL_COMPACT, && case_sem_INSN_SHLL_COMPACT },
+ { SH64_COMPACT_INSN_SHLL2_COMPACT, && case_sem_INSN_SHLL2_COMPACT },
+ { SH64_COMPACT_INSN_SHLL8_COMPACT, && case_sem_INSN_SHLL8_COMPACT },
+ { SH64_COMPACT_INSN_SHLL16_COMPACT, && case_sem_INSN_SHLL16_COMPACT },
+ { SH64_COMPACT_INSN_SHLR_COMPACT, && case_sem_INSN_SHLR_COMPACT },
+ { SH64_COMPACT_INSN_SHLR2_COMPACT, && case_sem_INSN_SHLR2_COMPACT },
+ { SH64_COMPACT_INSN_SHLR8_COMPACT, && case_sem_INSN_SHLR8_COMPACT },
+ { SH64_COMPACT_INSN_SHLR16_COMPACT, && case_sem_INSN_SHLR16_COMPACT },
+ { SH64_COMPACT_INSN_STC_GBR_COMPACT, && case_sem_INSN_STC_GBR_COMPACT },
+ { SH64_COMPACT_INSN_STCL_GBR_COMPACT, && case_sem_INSN_STCL_GBR_COMPACT },
+ { SH64_COMPACT_INSN_STS_FPSCR_COMPACT, && case_sem_INSN_STS_FPSCR_COMPACT },
+ { SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, && case_sem_INSN_STSL_FPSCR_COMPACT },
+ { SH64_COMPACT_INSN_STS_FPUL_COMPACT, && case_sem_INSN_STS_FPUL_COMPACT },
+ { SH64_COMPACT_INSN_STSL_FPUL_COMPACT, && case_sem_INSN_STSL_FPUL_COMPACT },
+ { SH64_COMPACT_INSN_STS_MACH_COMPACT, && case_sem_INSN_STS_MACH_COMPACT },
+ { SH64_COMPACT_INSN_STSL_MACH_COMPACT, && case_sem_INSN_STSL_MACH_COMPACT },
+ { SH64_COMPACT_INSN_STS_MACL_COMPACT, && case_sem_INSN_STS_MACL_COMPACT },
+ { SH64_COMPACT_INSN_STSL_MACL_COMPACT, && case_sem_INSN_STSL_MACL_COMPACT },
+ { SH64_COMPACT_INSN_STS_PR_COMPACT, && case_sem_INSN_STS_PR_COMPACT },
+ { SH64_COMPACT_INSN_STSL_PR_COMPACT, && case_sem_INSN_STSL_PR_COMPACT },
+ { SH64_COMPACT_INSN_SUB_COMPACT, && case_sem_INSN_SUB_COMPACT },
+ { SH64_COMPACT_INSN_SUBC_COMPACT, && case_sem_INSN_SUBC_COMPACT },
+ { SH64_COMPACT_INSN_SUBV_COMPACT, && case_sem_INSN_SUBV_COMPACT },
+ { SH64_COMPACT_INSN_SWAPB_COMPACT, && case_sem_INSN_SWAPB_COMPACT },
+ { SH64_COMPACT_INSN_SWAPW_COMPACT, && case_sem_INSN_SWAPW_COMPACT },
+ { SH64_COMPACT_INSN_TASB_COMPACT, && case_sem_INSN_TASB_COMPACT },
+ { SH64_COMPACT_INSN_TRAPA_COMPACT, && case_sem_INSN_TRAPA_COMPACT },
+ { SH64_COMPACT_INSN_TST_COMPACT, && case_sem_INSN_TST_COMPACT },
+ { SH64_COMPACT_INSN_TSTI_COMPACT, && case_sem_INSN_TSTI_COMPACT },
+ { SH64_COMPACT_INSN_TSTB_COMPACT, && case_sem_INSN_TSTB_COMPACT },
+ { SH64_COMPACT_INSN_XOR_COMPACT, && case_sem_INSN_XOR_COMPACT },
+ { SH64_COMPACT_INSN_XORI_COMPACT, && case_sem_INSN_XORI_COMPACT },
+ { SH64_COMPACT_INSN_XORB_COMPACT, && case_sem_INSN_XORB_COMPACT },
+ { SH64_COMPACT_INSN_XTRCT_COMPACT, && case_sem_INSN_XTRCT_COMPACT },
+ { 0, 0 }
+ };
+ int i;
+
+ for (i = 0; labels[i].label != 0; ++i)
+ {
+#if FAST_P
+ CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
+#else
+ CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
+#endif
+ }
+
+#undef DEFINE_LABELS
+#endif /* DEFINE_LABELS */
+
+#ifdef DEFINE_SWITCH
+
+/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
+ off frills like tracing and profiling. */
+/* FIXME: A better way would be to have TRACE_RESULT check for something
+ that can cause it to be optimized out. Another way would be to emit
+ special handlers into the instruction "stream". */
+
+#if FAST_P
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#endif
+
+#undef GET_ATTR
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+#else
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
+#endif
+
+{
+
+#if WITH_SCACHE_PBB
+
+/* Branch to next handler without going around main loop. */
+#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
+SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
+
+#else /* ! WITH_SCACHE_PBB */
+
+#define NEXT(vpc) BREAK (sem)
+#ifdef __GNUC__
+#if FAST_P
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
+#endif
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
+#endif
+
+#endif /* ! WITH_SCACHE_PBB */
+
+ {
+
+ CASE (sem, INSN_X_INVALID) : /* --invalid-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_AFTER) : /* --after-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_COMPACT
+ sh64_compact_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEFORE) : /* --before-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_COMPACT
+ sh64_compact_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_COMPACT
+#ifdef DEFINE_SWITCH
+ vpc = sh64_compact_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = sh64_compact_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CHAIN) : /* --chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_COMPACT
+ vpc = sh64_compact_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEGIN) : /* --begin-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_COMPACT
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = sh64_compact_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = sh64_compact_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = sh64_compact_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD_COMPACT) : /* add $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI_COMPACT) : /* add #$imm8, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), EXTQISI (ANDQI (FLD (f_imm8), 255)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDC_COMPACT) : /* addc $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_flag;
+ tmp_flag = ADDCFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
+ {
+ SI opval = ADDCSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = tmp_flag;
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDV_COMPACT) : /* addv $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_t;
+ tmp_t = ADDOFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), 0);
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = tmp_t;
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND_COMPACT) : /* and $rm64, $rn64 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = ANDDI (GET_H_GR (FLD (f_rm)), GET_H_GR (FLD (f_rn)));
+ SET_H_GR (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ANDI_COMPACT) : /* and #$uimm8, r0 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ANDSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8)));
+ SET_H_GRC (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ANDB_COMPACT) : /* and.b #$imm8, @(r0, gbr) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ UQI tmp_data;
+ tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ());
+ tmp_data = ANDQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8));
+ {
+ UQI opval = tmp_data;
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BF_COMPACT) : /* bf $disp8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bf_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_TBIT ())) {
+ {
+ UDI opval = FLD (i_disp8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BFS_COMPACT) : /* bf/s $disp8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bf_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_TBIT ())) {
+{
+ {
+ UDI opval = FLD (i_disp8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRA_COMPACT) : /* bra $disp12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bra_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ UDI opval = FLD (i_disp12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRAF_COMPACT) : /* braf $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ UDI opval = ADDDI (EXTSIDI (GET_H_GRC (FLD (f_rn))), ADDDI (pc, 4));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRK_COMPACT) : /* brk */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+sh64_break (current_cpu, pc);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSR_COMPACT) : /* bsr $disp12 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bra_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ SI opval = ADDDI (pc, 4);
+ SET_H_PR (opval);
+ TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
+ }
+ {
+ UDI opval = FLD (i_disp12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BSRF_COMPACT) : /* bsrf $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ SI opval = ADDDI (pc, 4);
+ SET_H_PR (opval);
+ TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
+ }
+ {
+ UDI opval = ADDDI (EXTSIDI (GET_H_GRC (FLD (f_rn))), ADDDI (pc, 4));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BT_COMPACT) : /* bt $disp8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bf_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_TBIT ()) {
+ {
+ UDI opval = FLD (i_disp8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BTS_COMPACT) : /* bt/s $disp8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_bf_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_TBIT ()) {
+{
+ {
+ UDI opval = FLD (i_disp8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CLRMAC_COMPACT) : /* clrmac */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = 0;
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+ {
+ SI opval = 0;
+ SET_H_MACH (opval);
+ TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CLRS_COMPACT) : /* clrs */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = 0;
+ SET_H_SBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "sbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CLRT_COMPACT) : /* clrt */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = 0;
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPEQ_COMPACT) : /* cmp/eq $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = EQSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn)));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPEQI_COMPACT) : /* cmp/eq #$imm8, r0 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = EQSI (GET_H_GRC (((UINT) 0)), EXTQISI (ANDQI (FLD (f_imm8), 255)));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPGE_COMPACT) : /* cmp/ge $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = GESI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPGT_COMPACT) : /* cmp/gt $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = GTSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPHI_COMPACT) : /* cmp/hi $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = GTUSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPHS_COMPACT) : /* cmp/hs $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = GEUSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPPL_COMPACT) : /* cmp/pl $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = GTSI (GET_H_GRC (FLD (f_rn)), 0);
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPPZ_COMPACT) : /* cmp/pz $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = GESI (GET_H_GRC (FLD (f_rn)), 0);
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPSTR_COMPACT) : /* cmp/str $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_t;
+ SI tmp_temp;
+ tmp_temp = XORSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn)));
+ tmp_t = EQSI (ANDSI (tmp_temp, 0xff000000), 0);
+ tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 16711680), 0), tmp_t);
+ tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 65280), 0), tmp_t);
+ tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 255), 0), tmp_t);
+ {
+ BI opval = ((GTUBI (tmp_t, 0)) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIV0S_COMPACT) : /* div0s $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ BI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+ {
+ BI opval = SRLSI (GET_H_GRC (FLD (f_rm)), 31);
+ SET_H_MBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval);
+ }
+ {
+ BI opval = ((EQSI (SRLSI (GET_H_GRC (FLD (f_rm)), 31), SRLSI (GET_H_GRC (FLD (f_rn)), 31))) ? (0) : (1));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIV0U_COMPACT) : /* div0u */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ BI opval = 0;
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_MBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DIV1_COMPACT) : /* div1 $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_oldq;
+ SI tmp_tmp0;
+ UQI tmp_tmp1;
+ tmp_oldq = GET_H_QBIT ();
+ {
+ BI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+ {
+ SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), ZEXTBISI (GET_H_TBIT ()));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+if (NOTBI (tmp_oldq)) {
+if (NOTBI (GET_H_MBIT ())) {
+{
+ tmp_tmp0 = GET_H_GRC (FLD (f_rn));
+ {
+ SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ tmp_tmp1 = GTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0);
+if (NOTBI (GET_H_QBIT ())) {
+ {
+ BI opval = ((tmp_tmp1) ? (1) : (0));
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+} else {
+ {
+ BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0));
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+}
+}
+} else {
+{
+ tmp_tmp0 = GET_H_GRC (FLD (f_rn));
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ tmp_tmp1 = LTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0);
+if (NOTBI (GET_H_QBIT ())) {
+ {
+ BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0));
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+} else {
+ {
+ BI opval = ((tmp_tmp1) ? (1) : (0));
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+}
+}
+}
+} else {
+if (NOTBI (GET_H_MBIT ())) {
+{
+ tmp_tmp0 = GET_H_GRC (FLD (f_rn));
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ tmp_tmp1 = LTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0);
+if (NOTBI (GET_H_QBIT ())) {
+ {
+ BI opval = ((tmp_tmp1) ? (1) : (0));
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+} else {
+ {
+ BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0));
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+}
+}
+} else {
+{
+ tmp_tmp0 = GET_H_GRC (FLD (f_rn));
+ {
+ SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ tmp_tmp1 = GTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0);
+if (NOTBI (GET_H_QBIT ())) {
+ {
+ BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0));
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+} else {
+ {
+ BI opval = ((tmp_tmp1) ? (1) : (0));
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+}
+}
+}
+}
+ {
+ BI opval = ((EQBI (GET_H_QBIT (), GET_H_MBIT ())) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DMULSL_COMPACT) : /* dmuls.l $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_GRC (FLD (f_rm))), EXTSIDI (GET_H_GRC (FLD (f_rn))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MACH (opval);
+ TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DMULUL_COMPACT) : /* dmulu.l $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_GRC (FLD (f_rm))), ZEXTSIDI (GET_H_GRC (FLD (f_rn))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MACH (opval);
+ TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_DT_COMPACT) : /* dt $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 1);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = EQSI (GET_H_GRC (FLD (f_rn)), 0);
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EXTSB_COMPACT) : /* exts.b $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTQISI (SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EXTSW_COMPACT) : /* exts.w $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EXTUB_COMPACT) : /* extu.b $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ZEXTQISI (SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_EXTUW_COMPACT) : /* extu.w $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FABS_COMPACT) : /* fabs $fsdn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ DF opval = sh64_fabsd (current_cpu, GET_H_DR (FLD (f_rn)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
+ }
+} else {
+ {
+ SF opval = sh64_fabss (current_cpu, GET_H_FRC (FLD (f_rn)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FADD_COMPACT) : /* fadd $fsdm, $fsdn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ DF opval = sh64_faddd (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
+ }
+} else {
+ {
+ SF opval = sh64_fadds (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FCMPEQ_COMPACT) : /* fcmp/eq $fsdm, $fsdn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ BI opval = sh64_fcmpeqd (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn)));
+ SET_H_TBIT (opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+} else {
+ {
+ BI opval = sh64_fcmpeqs (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn)));
+ SET_H_TBIT (opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FCMPGT_COMPACT) : /* fcmp/gt $fsdm, $fsdn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ BI opval = sh64_fcmpgtd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm)));
+ SET_H_TBIT (opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+} else {
+ {
+ BI opval = sh64_fcmpgts (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm)));
+ SET_H_TBIT (opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FCNVDS_COMPACT) : /* fcnvds $drn, fpul */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SF opval = sh64_fcnvds (current_cpu, GET_H_DRC (FLD (f_dn)));
+ CPU (h_fr[((UINT) 32)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FCNVSD_COMPACT) : /* fcnvsd fpul, $drn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DF opval = sh64_fcnvsd (current_cpu, CPU (h_fr[((UINT) 32)]));
+ SET_H_DRC (FLD (f_dn), opval);
+ TRACE_RESULT (current_cpu, abuf, "drn", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FDIV_COMPACT) : /* fdiv $fsdm, $fsdn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ DF opval = sh64_fdivd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
+ }
+} else {
+ {
+ SF opval = sh64_fdivs (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FIPR_COMPACT) : /* fipr $fvm, $fvn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fipr_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_m;
+ QI tmp_n;
+ SF tmp_res;
+ tmp_m = FLD (f_vm);
+ tmp_n = FLD (f_vn);
+ tmp_res = sh64_fmuls (current_cpu, GET_H_FVC (FLD (f_vm)), GET_H_FVC (FLD (f_vn)));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 1)), GET_H_FRC (ADDQI (tmp_n, 1))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 2)), GET_H_FRC (ADDQI (tmp_n, 2))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 3)), GET_H_FRC (ADDQI (tmp_n, 3))));
+ {
+ SF opval = tmp_res;
+ SET_H_FRC (ADDQI (tmp_n, 3), opval);
+ TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-3", 'f', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLDS_COMPACT) : /* flds $frn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SF opval = GET_H_FRC (FLD (f_rn));
+ CPU (h_fr[((UINT) 32)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLDI0_COMPACT) : /* fldi0 $frn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SF opval = sh64_fldi0 (current_cpu);
+ SET_H_FRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLDI1_COMPACT) : /* fldi1 $frn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SF opval = sh64_fldi1 (current_cpu);
+ SET_H_FRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLOAT_COMPACT) : /* float fpul, $fsdn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ DF opval = sh64_floatld (current_cpu, CPU (h_fr[((UINT) 32)]));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
+ }
+} else {
+ {
+ SF opval = sh64_floatls (current_cpu, CPU (h_fr[((UINT) 32)]));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMAC_COMPACT) : /* fmac fr0, $frm, $frn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SF opval = sh64_fmacs (current_cpu, GET_H_FRC (((UINT) 0)), GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn)));
+ SET_H_FRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMOV1_COMPACT) : /* fmov $frm, $frn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_SZBIT ())) {
+ {
+ SF opval = GET_H_FRC (FLD (f_rm));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
+ }
+} else {
+if (EQSI (ANDSI (FLD (f_rm), 1), 1)) {
+if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
+ {
+ DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
+ SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
+ }
+} else {
+ {
+ DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
+ }
+}
+} else {
+if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
+ {
+ DF opval = GET_H_DR (FLD (f_rm));
+ SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
+ }
+} else {
+ {
+ DF opval = GET_H_DR (FLD (f_rm));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMOV2_COMPACT) : /* fmov @$rm, $frn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_SZBIT ())) {
+ {
+ SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
+ }
+} else {
+if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
+ {
+ DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
+ }
+} else {
+ {
+ DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMOV3_COMPACT) : /* fmov @${rm}+, frn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_SZBIT ())) {
+{
+ {
+ SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+}
+} else {
+{
+if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
+ {
+ DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
+ }
+} else {
+ {
+ DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
+ }
+}
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 8);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMOV4_COMPACT) : /* fmov @(r0, $rm), $frn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_SZBIT ())) {
+ {
+ SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
+ }
+} else {
+if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
+ {
+ DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))));
+ SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
+ }
+} else {
+ {
+ DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMOV5_COMPACT) : /* fmov $frm, @$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_SZBIT ())) {
+ {
+ SF opval = GET_H_FRC (FLD (f_rm));
+ SETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+} else {
+if (EQSI (ANDSI (FLD (f_rm), 1), 1)) {
+ {
+ DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
+ SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+} else {
+ {
+ DF opval = GET_H_DR (FLD (f_rm));
+ SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMOV6_COMPACT) : /* fmov $frm, @-$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_SZBIT ())) {
+{
+ {
+ SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ SF opval = GET_H_FRC (FLD (f_rm));
+ SETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+}
+} else {
+{
+ {
+ SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 8);
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+if (EQSI (ANDSI (FLD (f_rm), 1), 1)) {
+ {
+ DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
+ SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+} else {
+ {
+ DF opval = GET_H_DR (FLD (f_rm));
+ SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMOV7_COMPACT) : /* fmov $frm, @(r0, $rn) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_SZBIT ())) {
+ {
+ SF opval = GET_H_FRC (FLD (f_rm));
+ SETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+} else {
+if (EQSI (ANDSI (FLD (f_rm), 1), 1)) {
+ {
+ DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
+ SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+} else {
+ {
+ DF opval = GET_H_DR (FLD (f_rm));
+ SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMUL_COMPACT) : /* fmul $fsdm, $fsdn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ DF opval = sh64_fmuld (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
+ }
+} else {
+ {
+ SF opval = sh64_fmuls (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FNEG_COMPACT) : /* fneg $fsdn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ DF opval = sh64_fnegd (current_cpu, GET_H_DR (FLD (f_rn)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
+ }
+} else {
+ {
+ SF opval = sh64_fnegs (current_cpu, GET_H_FRC (FLD (f_rn)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FRCHG_COMPACT) : /* frchg */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = NOTBI (GET_H_FRBIT ());
+ SET_H_FRBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "frbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FSCHG_COMPACT) : /* fschg */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = NOTBI (GET_H_SZBIT ());
+ SET_H_SZBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "szbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FSQRT_COMPACT) : /* fsqrt $fsdn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ DF opval = sh64_fsqrtd (current_cpu, GET_H_DR (FLD (f_rn)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
+ }
+} else {
+ {
+ SF opval = sh64_fsqrts (current_cpu, GET_H_FRC (FLD (f_rn)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FSTS_COMPACT) : /* fsts fpul, $frn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SF opval = CPU (h_fr[((UINT) 32)]);
+ SET_H_FRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FSUB_COMPACT) : /* fsub $fsdm, $fsdn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ DF opval = sh64_fsubd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
+ }
+} else {
+ {
+ SF opval = sh64_fsubs (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FTRC_COMPACT) : /* ftrc $fsdn, fpul */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SF opval = ((GET_H_PRBIT ()) ? (sh64_ftrcdl (current_cpu, GET_H_DR (FLD (f_rn)))) : (sh64_ftrcsl (current_cpu, GET_H_FRC (FLD (f_rn)))));
+ CPU (h_fr[((UINT) 32)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FTRV_COMPACT) : /* ftrv xmtrx, $fvn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fipr_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_n;
+ SF tmp_res;
+ tmp_n = FLD (f_vn);
+ tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 0)), GET_H_FRC (tmp_n));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 4)), GET_H_FRC (ADDQI (tmp_n, 1))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 8)), GET_H_FRC (ADDQI (tmp_n, 2))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 12)), GET_H_FRC (ADDQI (tmp_n, 3))));
+ {
+ SF opval = tmp_res;
+ SET_H_FRC (tmp_n, opval);
+ TRACE_RESULT (current_cpu, abuf, "frc-n", 'f', opval);
+ }
+ tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 1)), GET_H_FRC (tmp_n));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 5)), GET_H_FRC (ADDQI (tmp_n, 1))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 9)), GET_H_FRC (ADDQI (tmp_n, 2))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 13)), GET_H_FRC (ADDQI (tmp_n, 3))));
+ {
+ SF opval = tmp_res;
+ SET_H_FRC (ADDQI (tmp_n, 1), opval);
+ TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-1", 'f', opval);
+ }
+ tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 2)), GET_H_FRC (tmp_n));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 6)), GET_H_FRC (ADDQI (tmp_n, 1))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 10)), GET_H_FRC (ADDQI (tmp_n, 2))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 14)), GET_H_FRC (ADDQI (tmp_n, 3))));
+ {
+ SF opval = tmp_res;
+ SET_H_FRC (ADDQI (tmp_n, 2), opval);
+ TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-2", 'f', opval);
+ }
+ tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 3)), GET_H_FRC (tmp_n));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 7)), GET_H_FRC (ADDQI (tmp_n, 1))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 11)), GET_H_FRC (ADDQI (tmp_n, 2))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 15)), GET_H_FRC (ADDQI (tmp_n, 3))));
+ {
+ SF opval = tmp_res;
+ SET_H_FRC (ADDQI (tmp_n, 3), opval);
+ TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-3", 'f', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JMP_COMPACT) : /* jmp @$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ UDI opval = GET_H_GRC (FLD (f_rn));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_JSR_COMPACT) : /* jsr @$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ SI opval = ADDDI (pc, 4);
+ SET_H_PR (opval);
+ TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
+ }
+ {
+ UDI opval = GET_H_GRC (FLD (f_rn));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDC_COMPACT) : /* ldc $rn, gbr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (FLD (f_rn));
+ SET_H_GBR (opval);
+ TRACE_RESULT (current_cpu, abuf, "gbr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDCL_COMPACT) : /* ldc.l @${rn}+, gbr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ SET_H_GBR (opval);
+ TRACE_RESULT (current_cpu, abuf, "gbr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDS_FPSCR_COMPACT) : /* lds $rn, fpscr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (FLD (f_rn));
+ SET_H_FPCCR (opval);
+ TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDSL_FPSCR_COMPACT) : /* lds.l @${rn}+, fpscr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ SET_H_FPCCR (opval);
+ TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDS_FPUL_COMPACT) : /* lds $rn, fpul */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SF opval = SUBWORDSISF (GET_H_GRC (FLD (f_rn)));
+ CPU (h_fr[((UINT) 32)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDSL_FPUL_COMPACT) : /* lds.l @${rn}+, fpul */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ CPU (h_fr[((UINT) 32)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDS_MACH_COMPACT) : /* lds $rn, mach */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (FLD (f_rn));
+ SET_H_MACH (opval);
+ TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDSL_MACH_COMPACT) : /* lds.l @${rn}+, mach */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ SET_H_MACH (opval);
+ TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDS_MACL_COMPACT) : /* lds $rn, macl */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (FLD (f_rn));
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDSL_MACL_COMPACT) : /* lds.l @${rn}+, macl */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDS_PR_COMPACT) : /* lds $rn, pr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (FLD (f_rn));
+ SET_H_PR (opval);
+ TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDSL_PR_COMPACT) : /* lds.l @${rn}+, pr */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ SET_H_PR (opval);
+ TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACL_COMPACT) : /* mac.l @${rm}+, @${rn}+ */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_tmpry;
+ DI tmp_mac;
+ DI tmp_result;
+ SI tmp_x;
+ SI tmp_y;
+ tmp_x = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+if (EQSI (FLD (f_rn), FLD (f_rm))) {
+{
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+}
+}
+ tmp_y = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+ tmp_tmpry = MULDI (ZEXTSIDI (tmp_x), ZEXTSIDI (tmp_y));
+ tmp_mac = ORDI (SLLDI (ZEXTSIDI (GET_H_MACH ()), 32), ZEXTSIDI (GET_H_MACL ()));
+ tmp_result = ADDDI (tmp_mac, tmp_tmpry);
+{
+if (GET_H_SBIT ()) {
+{
+ SI tmp_min;
+ SI tmp_max;
+ tmp_max = SRLDI (INVDI (0), 16);
+ tmp_min = SRLDI (INVDI (0), 15);
+if (GTDI (tmp_result, tmp_max)) {
+ tmp_result = tmp_max;
+} else {
+if (LTDI (tmp_result, tmp_min)) {
+ tmp_result = tmp_min;
+}
+}
+}
+}
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MACH (opval);
+ TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MACW_COMPACT) : /* mac.w @${rm}+, @${rn}+ */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpry;
+ DI tmp_mac;
+ DI tmp_result;
+ HI tmp_x;
+ HI tmp_y;
+ tmp_x = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 2);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+if (EQSI (FLD (f_rn), FLD (f_rm))) {
+{
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 2);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+}
+}
+ tmp_y = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+ tmp_tmpry = MULSI (ZEXTHISI (tmp_x), ZEXTHISI (tmp_y));
+if (GET_H_SBIT ()) {
+{
+if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) {
+ {
+ SI opval = 1;
+ SET_H_MACH (opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
+ }
+}
+ {
+ SI opval = ADDSI (tmp_tmpry, GET_H_MACL ());
+ SET_H_MACL (opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+}
+} else {
+{
+ tmp_mac = ORDI (SLLDI (ZEXTSIDI (GET_H_MACH ()), 32), ZEXTSIDI (GET_H_MACL ()));
+ tmp_result = ADDDI (tmp_mac, EXTSIDI (tmp_tmpry));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MACH (opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MACL (opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOV_COMPACT) : /* mov $rm64, $rn64 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = GET_H_GR (FLD (f_rm));
+ SET_H_GR (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVI_COMPACT) : /* mov #$imm8, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTQIDI (ANDQI (FLD (f_imm8), 255));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVB1_COMPACT) : /* mov.b $rm, @$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3);
+ SETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVB2_COMPACT) : /* mov.b $rm, @-$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 1);
+ {
+ UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVB3_COMPACT) : /* mov.b $rm, @(r0,$rn) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3);
+ SETMEMUQI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVB4_COMPACT) : /* mov.b r0, @($imm8, gbr) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = ADDSI (GET_H_GBR (), FLD (f_imm8));
+ {
+ UQI opval = SUBWORDSIUQI (GET_H_GRC (((UINT) 0)), 3);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVB5_COMPACT) : /* mov.b r0, @($imm4, $rm) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movb5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4));
+ {
+ UQI opval = SUBWORDSIUQI (GET_H_GRC (((UINT) 0)), 3);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVB6_COMPACT) : /* mov.b @$rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, GET_H_GRC (FLD (f_rm))));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVB7_COMPACT) : /* mov.b @${rm}+, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_data;
+ tmp_data = GETMEMQI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+if (EQSI (FLD (f_rm), FLD (f_rn))) {
+ {
+ SI opval = EXTQISI (tmp_data);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 1);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+}
+ {
+ SI opval = EXTQISI (tmp_data);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVB8_COMPACT) : /* mov.b @(r0, $rm), $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVB9_COMPACT) : /* mov.b @($imm8, gbr), r0 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8))));
+ SET_H_GRC (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVB10_COMPACT) : /* mov.b @($imm4, $rm), r0 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movb5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4))));
+ SET_H_GRC (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVL1_COMPACT) : /* mov.l $rm, @$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (FLD (f_rm));
+ SETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVL2_COMPACT) : /* mov.l $rm, @-$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
+ {
+ SI opval = GET_H_GRC (FLD (f_rm));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVL3_COMPACT) : /* mov.l $rm, @(r0, $rn) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (FLD (f_rm));
+ SETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVL4_COMPACT) : /* mov.l r0, @($imm8x4, gbr) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (((UINT) 0));
+ SETMEMSI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x4)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVL5_COMPACT) : /* mov.l $rm, @($imm4x4, $rn) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (FLD (f_rm));
+ SETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm4x4)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVL6_COMPACT) : /* mov.l @$rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVL7_COMPACT) : /* mov.l @${rm}+, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+if (EQSI (FLD (f_rm), FLD (f_rn))) {
+ {
+ SI opval = GET_H_GRC (FLD (f_rn));
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVL8_COMPACT) : /* mov.l @(r0, $rm), $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVL9_COMPACT) : /* mov.l @($imm8x4, gbr), r0 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x4)));
+ SET_H_GRC (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVL10_COMPACT) : /* mov.l @($imm8x4, pc), $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_imm8x4), ANDDI (ADDDI (pc, 4), INVSI (3))));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVL11_COMPACT) : /* mov.l @($imm4x4, $rm), $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x4)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVW1_COMPACT) : /* mov.w $rm, @$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1);
+ SETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVW2_COMPACT) : /* mov.w $rm, @-$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 2);
+ {
+ HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1);
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVW3_COMPACT) : /* mov.w $rm, @(r0, $rn) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1);
+ SETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVW4_COMPACT) : /* mov.w r0, @($imm8x2, gbr) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ HI opval = SUBWORDSIHI (GET_H_GRC (((UINT) 0)), 1);
+ SETMEMHI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x2)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVW5_COMPACT) : /* mov.w r0, @($imm4x2, $rn) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ HI opval = SUBWORDSIHI (GET_H_GRC (((UINT) 0)), 1);
+ SETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm4x2)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVW6_COMPACT) : /* mov.w @$rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm))));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVW7_COMPACT) : /* mov.w @${rm}+, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_data;
+ tmp_data = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+if (EQSI (FLD (f_rm), FLD (f_rn))) {
+ {
+ SI opval = EXTHISI (tmp_data);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+}
+ {
+ SI opval = EXTHISI (tmp_data);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVW8_COMPACT) : /* mov.w @(r0, $rm), $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVW9_COMPACT) : /* mov.w @($imm8x2, gbr), r0 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x2))));
+ SET_H_GRC (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVW10_COMPACT) : /* mov.w @($imm8x2, pc), $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDDI (ADDDI (pc, 4), FLD (f_imm8x2))));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVW11_COMPACT) : /* mov.w @($imm4x2, $rm), r0 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw11_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x2))));
+ SET_H_GRC (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVA_COMPACT) : /* mova @($imm8x4, pc), r0 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ADDDI (ANDDI (ADDDI (pc, 4), INVSI (3)), FLD (f_imm8x4));
+ SET_H_GRC (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVCAL_COMPACT) : /* movca.l r0, @$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (((UINT) 0));
+ SETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVT_COMPACT) : /* movt $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ZEXTBISI (GET_H_TBIT ());
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULL_COMPACT) : /* mul.l $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = MULSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn)));
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULSW_COMPACT) : /* muls.w $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = MULSI (EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)), EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rn)), 1)));
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULUW_COMPACT) : /* mulu.w $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = MULSI (ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)), ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rn)), 1)));
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEG_COMPACT) : /* neg $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = NEGSI (GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NEGC_COMPACT) : /* negc $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_flag;
+ tmp_flag = SUBCFSI (0, GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
+ {
+ SI opval = SUBCSI (0, GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = tmp_flag;
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NOP_COMPACT) : /* nop */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NOT_COMPACT) : /* not $rm64, $rn64 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = INVDI (GET_H_GR (FLD (f_rm)));
+ SET_H_GR (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OCBI_COMPACT) : /* ocbi @$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OCBP_COMPACT) : /* ocbp @$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OCBWB_COMPACT) : /* ocbwb @$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR_COMPACT) : /* or $rm64, $rn64 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = ORDI (GET_H_GR (FLD (f_rm)), GET_H_GR (FLD (f_rn)));
+ SET_H_GR (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORI_COMPACT) : /* or #$uimm8, r0 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ORSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8)));
+ SET_H_GRC (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORB_COMPACT) : /* or.b #$imm8, @(r0, gbr) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ UQI tmp_data;
+ tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ());
+ tmp_data = ORQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8));
+ {
+ UQI opval = tmp_data;
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_PREF_COMPACT) : /* pref @$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROTCL_COMPACT) : /* rotcl $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_temp;
+ tmp_temp = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
+ {
+ SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), GET_H_TBIT ());
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_temp) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROTCR_COMPACT) : /* rotcr $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_lsbit;
+ SI tmp_temp;
+ tmp_lsbit = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rn)), 1), 0)) ? (0) : (1));
+ tmp_temp = GET_H_TBIT ();
+ {
+ SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rn)), 1), SLLSI (tmp_temp, 31));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_lsbit) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROTL_COMPACT) : /* rotl $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_temp;
+ tmp_temp = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
+ {
+ SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), tmp_temp);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_temp) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ROTR_COMPACT) : /* rotr $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_lsbit;
+ SI tmp_temp;
+ tmp_lsbit = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rn)), 1), 0)) ? (0) : (1));
+ tmp_temp = tmp_lsbit;
+ {
+ SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rn)), 1), SLLSI (tmp_temp, 31));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_lsbit) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RTS_COMPACT) : /* rts */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ UDI opval = GET_H_PR ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SETS_COMPACT) : /* sets */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = 1;
+ SET_H_SBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "sbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SETT_COMPACT) : /* sett */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = 1;
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHAD_COMPACT) : /* shad $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_shamt;
+ tmp_shamt = ANDQI (GET_H_GRC (FLD (f_rm)), 31);
+if (GESI (GET_H_GRC (FLD (f_rm)), 0)) {
+ {
+ SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), tmp_shamt);
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+} else {
+if (NEQI (tmp_shamt, 0)) {
+ {
+ SI opval = SRASI (GET_H_GRC (FLD (f_rn)), SUBSI (32, tmp_shamt));
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+} else {
+if (LTSI (GET_H_GRC (FLD (f_rn)), 0)) {
+ {
+ SI opval = NEGSI (1);
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+} else {
+ {
+ SI opval = 0;
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHAL_COMPACT) : /* shal $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_t;
+ tmp_t = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
+ {
+ SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 1);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_t) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHAR_COMPACT) : /* shar $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_t;
+ tmp_t = ANDSI (GET_H_GRC (FLD (f_rn)), 1);
+ {
+ SI opval = SRASI (GET_H_GRC (FLD (f_rn)), 1);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_t) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLD_COMPACT) : /* shld $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_shamt;
+ tmp_shamt = ANDQI (GET_H_GRC (FLD (f_rm)), 31);
+if (GESI (GET_H_GRC (FLD (f_rm)), 0)) {
+ {
+ SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), tmp_shamt);
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+} else {
+if (NEQI (tmp_shamt, 0)) {
+ {
+ SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), SUBSI (32, tmp_shamt));
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+} else {
+ {
+ SI opval = 0;
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLL_COMPACT) : /* shll $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_t;
+ tmp_t = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
+ {
+ SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 1);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_t) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLL2_COMPACT) : /* shll2 $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 2);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLL8_COMPACT) : /* shll8 $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 8);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLL16_COMPACT) : /* shll16 $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 16);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLR_COMPACT) : /* shlr $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_t;
+ tmp_t = ANDSI (GET_H_GRC (FLD (f_rn)), 1);
+ {
+ SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 1);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_t) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLR2_COMPACT) : /* shlr2 $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 2);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLR8_COMPACT) : /* shlr8 $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 8);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLR16_COMPACT) : /* shlr16 $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 16);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STC_GBR_COMPACT) : /* stc gbr, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GBR ();
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STCL_GBR_COMPACT) : /* stc.l gbr, @-$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
+ {
+ SI opval = GET_H_GBR ();
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STS_FPSCR_COMPACT) : /* sts fpscr, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_FPCCR ();
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STSL_FPSCR_COMPACT) : /* sts.l fpscr, @-$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
+ {
+ SI opval = GET_H_FPCCR ();
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STS_FPUL_COMPACT) : /* sts fpul, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SUBWORDSFSI (CPU (h_fr[((UINT) 32)]));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STSL_FPUL_COMPACT) : /* sts.l fpul, @-$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
+ {
+ SF opval = CPU (h_fr[((UINT) 32)]);
+ SETMEMSF (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STS_MACH_COMPACT) : /* sts mach, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_MACH ();
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STSL_MACH_COMPACT) : /* sts.l mach, @-$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
+ {
+ SI opval = GET_H_MACH ();
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STS_MACL_COMPACT) : /* sts macl, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_MACL ();
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STSL_MACL_COMPACT) : /* sts.l macl, @-$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
+ {
+ SI opval = GET_H_MACL ();
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STS_PR_COMPACT) : /* sts pr, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_PR ();
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STSL_PR_COMPACT) : /* sts.l pr, @-$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
+ {
+ SI opval = GET_H_PR ();
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB_COMPACT) : /* sub $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBC_COMPACT) : /* subc $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_flag;
+ tmp_flag = SUBCFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
+ {
+ SI opval = SUBCSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = tmp_flag;
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBV_COMPACT) : /* subv $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_t;
+ tmp_t = SUBOFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), 0);
+ {
+ SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_t) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SWAPB_COMPACT) : /* swap.b $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ UHI tmp_top_half;
+ UQI tmp_byte1;
+ UQI tmp_byte0;
+ tmp_top_half = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 0);
+ tmp_byte1 = SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 2);
+ tmp_byte0 = SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3);
+ {
+ SI opval = ORSI (SLLSI (tmp_top_half, 16), ORSI (SLLSI (tmp_byte0, 8), tmp_byte1));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SWAPW_COMPACT) : /* swap.w $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rm)), 16), SLLSI (GET_H_GRC (FLD (f_rm)), 16));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TASB_COMPACT) : /* tas.b @$rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ UQI tmp_byte;
+ tmp_byte = GETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ {
+ BI opval = ((EQQI (tmp_byte, 0)) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+ tmp_byte = ORQI (tmp_byte, 128);
+ {
+ UQI opval = tmp_byte;
+ SETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TRAPA_COMPACT) : /* trapa #$uimm8 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+sh64_compact_trapa (current_cpu, FLD (f_imm8), pc);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TST_COMPACT) : /* tst $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn))), 0)) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TSTI_COMPACT) : /* tst #$uimm8, r0 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_GRC (((UINT) 0)), ZEXTSISI (FLD (f_imm8))), 0)) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TSTB_COMPACT) : /* tst.b #$imm8, @(r0, gbr) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ());
+ {
+ BI opval = ((EQQI (ANDQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8)), 0)) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR_COMPACT) : /* xor $rm64, $rn64 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = XORDI (GET_H_GR (FLD (f_rn)), GET_H_GR (FLD (f_rm)));
+ SET_H_GR (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XORI_COMPACT) : /* xor #$uimm8, r0 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = XORDI (GET_H_GR (((UINT) 0)), ZEXTSIDI (FLD (f_imm8)));
+ SET_H_GR (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-0", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XORB_COMPACT) : /* xor.b #$imm8, @(r0, gbr) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ UQI tmp_data;
+ tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ());
+ tmp_data = XORQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8));
+ {
+ UQI opval = tmp_data;
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XTRCT_COMPACT) : /* xtrct $rm, $rn */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rm)), 16), SRLSI (GET_H_GRC (FLD (f_rn)), 16));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+
+ }
+ ENDSWITCH (sem) /* End of semantic switch. */
+
+ /* At this point `vpc' contains the next insn to execute. */
+}
+
+#undef DEFINE_SWITCH
+#endif /* DEFINE_SWITCH */
--- /dev/null
+/* Simulator instruction semantics for sh64.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU sh64
+#define WANT_CPU_SH64
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+#undef GET_ATTR
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+#else
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
+#endif
+
+/* This is used so that we can compile two copies of the semantic code,
+ one with full feature support and one without that runs fast(er).
+ FAST_P, when desired, is defined on the command line, -DFAST_P=1. */
+#if FAST_P
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#else
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
+#endif
+
+/* x-invalid: --invalid-- */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-after: --after-- */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_COMPACT
+ sh64_compact_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-before: --before-- */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_COMPACT
+ sh64_compact_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-cti-chain: --cti-chain-- */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_COMPACT
+#ifdef DEFINE_SWITCH
+ vpc = sh64_compact_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = sh64_compact_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-chain: --chain-- */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_COMPACT
+ vpc = sh64_compact_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-begin: --begin-- */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_COMPACT
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = sh64_compact_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = sh64_compact_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = sh64_compact_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* add-compact: add $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,add_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* addi-compact: add #$imm8, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,addi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), EXTQISI (ANDQI (FLD (f_imm8), 255)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* addc-compact: addc $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,addc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_flag;
+ tmp_flag = ADDCFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
+ {
+ SI opval = ADDCSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = tmp_flag;
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* addv-compact: addv $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,addv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_t;
+ tmp_t = ADDOFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), 0);
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = tmp_t;
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* and-compact: and $rm64, $rn64 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,and_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = ANDDI (GET_H_GR (FLD (f_rm)), GET_H_GR (FLD (f_rn)));
+ SET_H_GR (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* andi-compact: and #$uimm8, r0 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,andi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ANDSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8)));
+ SET_H_GRC (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* andb-compact: and.b #$imm8, @(r0, gbr) */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,andb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ UQI tmp_data;
+ tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ());
+ tmp_data = ANDQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8));
+ {
+ UQI opval = tmp_data;
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* bf-compact: bf $disp8 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,bf_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bf_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_TBIT ())) {
+ {
+ UDI opval = FLD (i_disp8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bfs-compact: bf/s $disp8 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,bfs_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bf_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_TBIT ())) {
+{
+ {
+ UDI opval = FLD (i_disp8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bra-compact: bra $disp12 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,bra_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bra_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ UDI opval = FLD (i_disp12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* braf-compact: braf $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,braf_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ UDI opval = ADDDI (EXTSIDI (GET_H_GRC (FLD (f_rn))), ADDDI (pc, 4));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brk-compact: brk */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,brk_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+sh64_break (current_cpu, pc);
+
+ return vpc;
+#undef FLD
+}
+
+/* bsr-compact: bsr $disp12 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,bsr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bra_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ SI opval = ADDDI (pc, 4);
+ SET_H_PR (opval);
+ TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
+ }
+ {
+ UDI opval = FLD (i_disp12);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bsrf-compact: bsrf $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,bsrf_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ SI opval = ADDDI (pc, 4);
+ SET_H_PR (opval);
+ TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
+ }
+ {
+ UDI opval = ADDDI (EXTSIDI (GET_H_GRC (FLD (f_rn))), ADDDI (pc, 4));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bt-compact: bt $disp8 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,bt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bf_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_TBIT ()) {
+ {
+ UDI opval = FLD (i_disp8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bts-compact: bt/s $disp8 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,bts_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bf_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_TBIT ()) {
+{
+ {
+ UDI opval = FLD (i_disp8);
+ SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* clrmac-compact: clrmac */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,clrmac_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = 0;
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+ {
+ SI opval = 0;
+ SET_H_MACH (opval);
+ TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* clrs-compact: clrs */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,clrs_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = 0;
+ SET_H_SBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "sbit", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* clrt-compact: clrt */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,clrt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = 0;
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* cmpeq-compact: cmp/eq $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,cmpeq_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = EQSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn)));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* cmpeqi-compact: cmp/eq #$imm8, r0 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,cmpeqi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = EQSI (GET_H_GRC (((UINT) 0)), EXTQISI (ANDQI (FLD (f_imm8), 255)));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* cmpge-compact: cmp/ge $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,cmpge_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = GESI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* cmpgt-compact: cmp/gt $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,cmpgt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = GTSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* cmphi-compact: cmp/hi $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,cmphi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = GTUSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* cmphs-compact: cmp/hs $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,cmphs_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = GEUSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* cmppl-compact: cmp/pl $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,cmppl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = GTSI (GET_H_GRC (FLD (f_rn)), 0);
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* cmppz-compact: cmp/pz $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,cmppz_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = GESI (GET_H_GRC (FLD (f_rn)), 0);
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* cmpstr-compact: cmp/str $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,cmpstr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_t;
+ SI tmp_temp;
+ tmp_temp = XORSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn)));
+ tmp_t = EQSI (ANDSI (tmp_temp, 0xff000000), 0);
+ tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 16711680), 0), tmp_t);
+ tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 65280), 0), tmp_t);
+ tmp_t = ORBI (EQSI (ANDSI (tmp_temp, 255), 0), tmp_t);
+ {
+ BI opval = ((GTUBI (tmp_t, 0)) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* div0s-compact: div0s $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,div0s_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ BI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+ {
+ BI opval = SRLSI (GET_H_GRC (FLD (f_rm)), 31);
+ SET_H_MBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval);
+ }
+ {
+ BI opval = ((EQSI (SRLSI (GET_H_GRC (FLD (f_rm)), 31), SRLSI (GET_H_GRC (FLD (f_rn)), 31))) ? (0) : (1));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* div0u-compact: div0u */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,div0u_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ BI opval = 0;
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+ {
+ BI opval = 0;
+ SET_H_MBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* div1-compact: div1 $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,div1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_oldq;
+ SI tmp_tmp0;
+ UQI tmp_tmp1;
+ tmp_oldq = GET_H_QBIT ();
+ {
+ BI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+ {
+ SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), ZEXTBISI (GET_H_TBIT ()));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+if (NOTBI (tmp_oldq)) {
+if (NOTBI (GET_H_MBIT ())) {
+{
+ tmp_tmp0 = GET_H_GRC (FLD (f_rn));
+ {
+ SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ tmp_tmp1 = GTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0);
+if (NOTBI (GET_H_QBIT ())) {
+ {
+ BI opval = ((tmp_tmp1) ? (1) : (0));
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+} else {
+ {
+ BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0));
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+}
+}
+} else {
+{
+ tmp_tmp0 = GET_H_GRC (FLD (f_rn));
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ tmp_tmp1 = LTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0);
+if (NOTBI (GET_H_QBIT ())) {
+ {
+ BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0));
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+} else {
+ {
+ BI opval = ((tmp_tmp1) ? (1) : (0));
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+}
+}
+}
+} else {
+if (NOTBI (GET_H_MBIT ())) {
+{
+ tmp_tmp0 = GET_H_GRC (FLD (f_rn));
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ tmp_tmp1 = LTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0);
+if (NOTBI (GET_H_QBIT ())) {
+ {
+ BI opval = ((tmp_tmp1) ? (1) : (0));
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+} else {
+ {
+ BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0));
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+}
+}
+} else {
+{
+ tmp_tmp0 = GET_H_GRC (FLD (f_rn));
+ {
+ SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ tmp_tmp1 = GTUSI (GET_H_GRC (FLD (f_rn)), tmp_tmp0);
+if (NOTBI (GET_H_QBIT ())) {
+ {
+ BI opval = ((EQQI (tmp_tmp1, 0)) ? (1) : (0));
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+} else {
+ {
+ BI opval = ((tmp_tmp1) ? (1) : (0));
+ SET_H_QBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "qbit", 'x', opval);
+ }
+}
+}
+}
+}
+ {
+ BI opval = ((EQBI (GET_H_QBIT (), GET_H_MBIT ())) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* dmulsl-compact: dmuls.l $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,dmulsl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_result;
+ tmp_result = MULDI (EXTSIDI (GET_H_GRC (FLD (f_rm))), EXTSIDI (GET_H_GRC (FLD (f_rn))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MACH (opval);
+ TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* dmulul-compact: dmulu.l $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,dmulul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_result;
+ tmp_result = MULDI (ZEXTSIDI (GET_H_GRC (FLD (f_rm))), ZEXTSIDI (GET_H_GRC (FLD (f_rn))));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MACH (opval);
+ TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* dt-compact: dt $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,dt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 1);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = EQSI (GET_H_GRC (FLD (f_rn)), 0);
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* extsb-compact: exts.b $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,extsb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTQISI (SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* extsw-compact: exts.w $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,extsw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* extub-compact: extu.b $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,extub_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ZEXTQISI (SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* extuw-compact: extu.w $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,extuw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fabs-compact: fabs $fsdn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fabs_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ DF opval = sh64_fabsd (current_cpu, GET_H_DR (FLD (f_rn)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
+ }
+} else {
+ {
+ SF opval = sh64_fabss (current_cpu, GET_H_FRC (FLD (f_rn)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* fadd-compact: fadd $fsdm, $fsdn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fadd_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ DF opval = sh64_faddd (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
+ }
+} else {
+ {
+ SF opval = sh64_fadds (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* fcmpeq-compact: fcmp/eq $fsdm, $fsdn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fcmpeq_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ BI opval = sh64_fcmpeqd (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn)));
+ SET_H_TBIT (opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+} else {
+ {
+ BI opval = sh64_fcmpeqs (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn)));
+ SET_H_TBIT (opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* fcmpgt-compact: fcmp/gt $fsdm, $fsdn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fcmpgt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ BI opval = sh64_fcmpgtd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm)));
+ SET_H_TBIT (opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+} else {
+ {
+ BI opval = sh64_fcmpgts (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm)));
+ SET_H_TBIT (opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* fcnvds-compact: fcnvds $drn, fpul */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fcnvds_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SF opval = sh64_fcnvds (current_cpu, GET_H_DRC (FLD (f_dn)));
+ CPU (h_fr[((UINT) 32)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fcnvsd-compact: fcnvsd fpul, $drn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fcnvsd_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcnvds_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DF opval = sh64_fcnvsd (current_cpu, CPU (h_fr[((UINT) 32)]));
+ SET_H_DRC (FLD (f_dn), opval);
+ TRACE_RESULT (current_cpu, abuf, "drn", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fdiv-compact: fdiv $fsdm, $fsdn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fdiv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ DF opval = sh64_fdivd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
+ }
+} else {
+ {
+ SF opval = sh64_fdivs (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* fipr-compact: fipr $fvm, $fvn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fipr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fipr_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_m;
+ QI tmp_n;
+ SF tmp_res;
+ tmp_m = FLD (f_vm);
+ tmp_n = FLD (f_vn);
+ tmp_res = sh64_fmuls (current_cpu, GET_H_FVC (FLD (f_vm)), GET_H_FVC (FLD (f_vn)));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 1)), GET_H_FRC (ADDQI (tmp_n, 1))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 2)), GET_H_FRC (ADDQI (tmp_n, 2))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_FRC (ADDQI (tmp_m, 3)), GET_H_FRC (ADDQI (tmp_n, 3))));
+ {
+ SF opval = tmp_res;
+ SET_H_FRC (ADDQI (tmp_n, 3), opval);
+ TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-3", 'f', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* flds-compact: flds $frn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,flds_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SF opval = GET_H_FRC (FLD (f_rn));
+ CPU (h_fr[((UINT) 32)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fldi0-compact: fldi0 $frn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fldi0_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SF opval = sh64_fldi0 (current_cpu);
+ SET_H_FRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fldi1-compact: fldi1 $frn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fldi1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SF opval = sh64_fldi1 (current_cpu);
+ SET_H_FRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* float-compact: float fpul, $fsdn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,float_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ DF opval = sh64_floatld (current_cpu, CPU (h_fr[((UINT) 32)]));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
+ }
+} else {
+ {
+ SF opval = sh64_floatls (current_cpu, CPU (h_fr[((UINT) 32)]));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* fmac-compact: fmac fr0, $frm, $frn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fmac_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SF opval = sh64_fmacs (current_cpu, GET_H_FRC (((UINT) 0)), GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn)));
+ SET_H_FRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fmov1-compact: fmov $frm, $frn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fmov1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_SZBIT ())) {
+ {
+ SF opval = GET_H_FRC (FLD (f_rm));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
+ }
+} else {
+if (EQSI (ANDSI (FLD (f_rm), 1), 1)) {
+if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
+ {
+ DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
+ SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
+ }
+} else {
+ {
+ DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
+ }
+}
+} else {
+if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
+ {
+ DF opval = GET_H_DR (FLD (f_rm));
+ SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
+ }
+} else {
+ {
+ DF opval = GET_H_DR (FLD (f_rm));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* fmov2-compact: fmov @$rm, $frn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fmov2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_SZBIT ())) {
+ {
+ SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
+ }
+} else {
+if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
+ {
+ DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
+ }
+} else {
+ {
+ DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* fmov3-compact: fmov @${rm}+, frn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fmov3_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_SZBIT ())) {
+{
+ {
+ SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+}
+} else {
+{
+if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
+ {
+ DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
+ }
+} else {
+ {
+ DF opval = GETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
+ }
+}
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 8);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* fmov4-compact: fmov @(r0, $rm), $frn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fmov4_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_SZBIT ())) {
+ {
+ SF opval = GETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
+ }
+} else {
+if (EQSI (ANDSI (FLD (f_rn), 1), 1)) {
+ {
+ DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))));
+ SET_H_XD (((FLD (f_rn)) & (INVQI (1))), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "xd-and--DFLT-index-of--DFLT-frn-inv--QI-1", 'f', opval);
+ }
+} else {
+ {
+ DF opval = GETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-frn", 'f', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* fmov5-compact: fmov $frm, @$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fmov5_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_SZBIT ())) {
+ {
+ SF opval = GET_H_FRC (FLD (f_rm));
+ SETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+} else {
+if (EQSI (ANDSI (FLD (f_rm), 1), 1)) {
+ {
+ DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
+ SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+} else {
+ {
+ DF opval = GET_H_DR (FLD (f_rm));
+ SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* fmov6-compact: fmov $frm, @-$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fmov6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_SZBIT ())) {
+{
+ {
+ SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ SF opval = GET_H_FRC (FLD (f_rm));
+ SETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ written |= (1 << 6);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+}
+} else {
+{
+ {
+ SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), 8);
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+if (EQSI (ANDSI (FLD (f_rm), 1), 1)) {
+ {
+ DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
+ SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+} else {
+ {
+ DF opval = GET_H_DR (FLD (f_rm));
+ SETMEMDF (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* fmov7-compact: fmov $frm, @(r0, $rn) */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fmov7_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (NOTBI (GET_H_SZBIT ())) {
+ {
+ SF opval = GET_H_FRC (FLD (f_rm));
+ SETMEMSF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+} else {
+if (EQSI (ANDSI (FLD (f_rm), 1), 1)) {
+ {
+ DF opval = GET_H_XD (((FLD (f_rm)) & (INVQI (1))));
+ SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+} else {
+ {
+ DF opval = GET_H_DR (FLD (f_rm));
+ SETMEMDF (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* fmul-compact: fmul $fsdm, $fsdn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fmul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ DF opval = sh64_fmuld (current_cpu, GET_H_DR (FLD (f_rm)), GET_H_DR (FLD (f_rn)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
+ }
+} else {
+ {
+ SF opval = sh64_fmuls (current_cpu, GET_H_FRC (FLD (f_rm)), GET_H_FRC (FLD (f_rn)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* fneg-compact: fneg $fsdn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fneg_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ DF opval = sh64_fnegd (current_cpu, GET_H_DR (FLD (f_rn)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
+ }
+} else {
+ {
+ SF opval = sh64_fnegs (current_cpu, GET_H_FRC (FLD (f_rn)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* frchg-compact: frchg */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,frchg_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = NOTBI (GET_H_FRBIT ());
+ SET_H_FRBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "frbit", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fschg-compact: fschg */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fschg_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = NOTBI (GET_H_SZBIT ());
+ SET_H_SZBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "szbit", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fsqrt-compact: fsqrt $fsdn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fsqrt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ DF opval = sh64_fsqrtd (current_cpu, GET_H_DR (FLD (f_rn)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
+ }
+} else {
+ {
+ SF opval = sh64_fsqrts (current_cpu, GET_H_FRC (FLD (f_rn)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* fsts-compact: fsts fpul, $frn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fsts_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SF opval = CPU (h_fr[((UINT) 32)]);
+ SET_H_FRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "frn", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fsub-compact: fsub $fsdm, $fsdn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,fsub_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+if (GET_H_PRBIT ()) {
+ {
+ DF opval = sh64_fsubd (current_cpu, GET_H_DR (FLD (f_rn)), GET_H_DR (FLD (f_rm)));
+ SET_H_DR (FLD (f_rn), opval);
+ written |= (1 << 8);
+ TRACE_RESULT (current_cpu, abuf, "dr-index-of--DFLT-fsdn", 'f', opval);
+ }
+} else {
+ {
+ SF opval = sh64_fsubs (current_cpu, GET_H_FRC (FLD (f_rn)), GET_H_FRC (FLD (f_rm)));
+ SET_H_FRC (FLD (f_rn), opval);
+ written |= (1 << 7);
+ TRACE_RESULT (current_cpu, abuf, "fsdn", 'f', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* ftrc-compact: ftrc $fsdn, fpul */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,ftrc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SF opval = ((GET_H_PRBIT ()) ? (sh64_ftrcdl (current_cpu, GET_H_DR (FLD (f_rn)))) : (sh64_ftrcsl (current_cpu, GET_H_FRC (FLD (f_rn)))));
+ CPU (h_fr[((UINT) 32)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ftrv-compact: ftrv xmtrx, $fvn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,ftrv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fipr_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_n;
+ SF tmp_res;
+ tmp_n = FLD (f_vn);
+ tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 0)), GET_H_FRC (tmp_n));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 4)), GET_H_FRC (ADDQI (tmp_n, 1))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 8)), GET_H_FRC (ADDQI (tmp_n, 2))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 12)), GET_H_FRC (ADDQI (tmp_n, 3))));
+ {
+ SF opval = tmp_res;
+ SET_H_FRC (tmp_n, opval);
+ TRACE_RESULT (current_cpu, abuf, "frc-n", 'f', opval);
+ }
+ tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 1)), GET_H_FRC (tmp_n));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 5)), GET_H_FRC (ADDQI (tmp_n, 1))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 9)), GET_H_FRC (ADDQI (tmp_n, 2))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 13)), GET_H_FRC (ADDQI (tmp_n, 3))));
+ {
+ SF opval = tmp_res;
+ SET_H_FRC (ADDQI (tmp_n, 1), opval);
+ TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-1", 'f', opval);
+ }
+ tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 2)), GET_H_FRC (tmp_n));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 6)), GET_H_FRC (ADDQI (tmp_n, 1))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 10)), GET_H_FRC (ADDQI (tmp_n, 2))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 14)), GET_H_FRC (ADDQI (tmp_n, 3))));
+ {
+ SF opval = tmp_res;
+ SET_H_FRC (ADDQI (tmp_n, 2), opval);
+ TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-2", 'f', opval);
+ }
+ tmp_res = sh64_fmuls (current_cpu, GET_H_XF (((UINT) 3)), GET_H_FRC (tmp_n));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 7)), GET_H_FRC (ADDQI (tmp_n, 1))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 11)), GET_H_FRC (ADDQI (tmp_n, 2))));
+ tmp_res = sh64_fadds (current_cpu, tmp_res, sh64_fmuls (current_cpu, GET_H_XF (((UINT) 15)), GET_H_FRC (ADDQI (tmp_n, 3))));
+ {
+ SF opval = tmp_res;
+ SET_H_FRC (ADDQI (tmp_n, 3), opval);
+ TRACE_RESULT (current_cpu, abuf, "frc-add--DFLT-n-3", 'f', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* jmp-compact: jmp @$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,jmp_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ UDI opval = GET_H_GRC (FLD (f_rn));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* jsr-compact: jsr @$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,jsr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+{
+ {
+ SI opval = ADDDI (pc, 4);
+ SET_H_PR (opval);
+ TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
+ }
+ {
+ UDI opval = GET_H_GRC (FLD (f_rn));
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* ldc-compact: ldc $rn, gbr */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,ldc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (FLD (f_rn));
+ SET_H_GBR (opval);
+ TRACE_RESULT (current_cpu, abuf, "gbr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldcl-compact: ldc.l @${rn}+, gbr */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,ldcl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ SET_H_GBR (opval);
+ TRACE_RESULT (current_cpu, abuf, "gbr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lds-fpscr-compact: lds $rn, fpscr */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,lds_fpscr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (FLD (f_rn));
+ SET_H_FPCCR (opval);
+ TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldsl-fpscr-compact: lds.l @${rn}+, fpscr */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,ldsl_fpscr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ SET_H_FPCCR (opval);
+ TRACE_RESULT (current_cpu, abuf, "fpscr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lds-fpul-compact: lds $rn, fpul */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,lds_fpul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SF opval = SUBWORDSISF (GET_H_GRC (FLD (f_rn)));
+ CPU (h_fr[((UINT) 32)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldsl-fpul-compact: lds.l @${rn}+, fpul */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,ldsl_fpul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SF opval = GETMEMSF (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ CPU (h_fr[((UINT) 32)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fpul", 'f', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lds-mach-compact: lds $rn, mach */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,lds_mach_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (FLD (f_rn));
+ SET_H_MACH (opval);
+ TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldsl-mach-compact: lds.l @${rn}+, mach */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,ldsl_mach_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ SET_H_MACH (opval);
+ TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lds-macl-compact: lds $rn, macl */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,lds_macl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (FLD (f_rn));
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldsl-macl-compact: lds.l @${rn}+, macl */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,ldsl_macl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* lds-pr-compact: lds $rn, pr */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,lds_pr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (FLD (f_rn));
+ SET_H_PR (opval);
+ TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldsl-pr-compact: lds.l @${rn}+, pr */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,ldsl_pr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ SET_H_PR (opval);
+ TRACE_RESULT (current_cpu, abuf, "pr", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* macl-compact: mac.l @${rm}+, @${rn}+ */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,macl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_tmpry;
+ DI tmp_mac;
+ DI tmp_result;
+ SI tmp_x;
+ SI tmp_y;
+ tmp_x = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+if (EQSI (FLD (f_rn), FLD (f_rm))) {
+{
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 4);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+}
+}
+ tmp_y = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+ tmp_tmpry = MULDI (ZEXTSIDI (tmp_x), ZEXTSIDI (tmp_y));
+ tmp_mac = ORDI (SLLDI (ZEXTSIDI (GET_H_MACH ()), 32), ZEXTSIDI (GET_H_MACL ()));
+ tmp_result = ADDDI (tmp_mac, tmp_tmpry);
+{
+if (GET_H_SBIT ()) {
+{
+ SI tmp_min;
+ SI tmp_max;
+ tmp_max = SRLDI (INVDI (0), 16);
+ tmp_min = SRLDI (INVDI (0), 15);
+if (GTDI (tmp_result, tmp_max)) {
+ tmp_result = tmp_max;
+} else {
+if (LTDI (tmp_result, tmp_min)) {
+ tmp_result = tmp_min;
+}
+}
+}
+}
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MACH (opval);
+ TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* macw-compact: mac.w @${rm}+, @${rn}+ */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,macw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_tmpry;
+ DI tmp_mac;
+ DI tmp_result;
+ HI tmp_x;
+ HI tmp_y;
+ tmp_x = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 2);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+if (EQSI (FLD (f_rn), FLD (f_rm))) {
+{
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rn)), 2);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+}
+}
+ tmp_y = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+ tmp_tmpry = MULSI (ZEXTHISI (tmp_x), ZEXTHISI (tmp_y));
+if (GET_H_SBIT ()) {
+{
+if (ADDOFSI (tmp_tmpry, GET_H_MACL (), 0)) {
+ {
+ SI opval = 1;
+ SET_H_MACH (opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
+ }
+}
+ {
+ SI opval = ADDSI (tmp_tmpry, GET_H_MACL ());
+ SET_H_MACL (opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+}
+} else {
+{
+ tmp_mac = ORDI (SLLDI (ZEXTSIDI (GET_H_MACH ()), 32), ZEXTSIDI (GET_H_MACL ()));
+ tmp_result = ADDDI (tmp_mac, EXTSIDI (tmp_tmpry));
+ {
+ SI opval = SUBWORDDISI (tmp_result, 0);
+ SET_H_MACH (opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "mach", 'x', opval);
+ }
+ {
+ SI opval = SUBWORDDISI (tmp_result, 1);
+ SET_H_MACL (opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mov-compact: mov $rm64, $rn64 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,mov_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = GET_H_GR (FLD (f_rm));
+ SET_H_GR (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movi-compact: mov #$imm8, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTQIDI (ANDQI (FLD (f_imm8), 255));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movb1-compact: mov.b $rm, @$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movb1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3);
+ SETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movb2-compact: mov.b $rm, @-$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movb2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 1);
+ {
+ UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* movb3-compact: mov.b $rm, @(r0,$rn) */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movb3_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ UQI opval = SUBWORDSIUQI (GET_H_GRC (FLD (f_rm)), 3);
+ SETMEMUQI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movb4-compact: mov.b r0, @($imm8, gbr) */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movb4_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = ADDSI (GET_H_GBR (), FLD (f_imm8));
+ {
+ UQI opval = SUBWORDSIUQI (GET_H_GRC (((UINT) 0)), 3);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* movb5-compact: mov.b r0, @($imm4, $rm) */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movb5_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movb5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4));
+ {
+ UQI opval = SUBWORDSIUQI (GET_H_GRC (((UINT) 0)), 3);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* movb6-compact: mov.b @$rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movb6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, GET_H_GRC (FLD (f_rm))));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movb7-compact: mov.b @${rm}+, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movb7_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_data;
+ tmp_data = GETMEMQI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+if (EQSI (FLD (f_rm), FLD (f_rn))) {
+ {
+ SI opval = EXTQISI (tmp_data);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 1);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+}
+ {
+ SI opval = EXTQISI (tmp_data);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* movb8-compact: mov.b @(r0, $rm), $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movb8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movb9-compact: mov.b @($imm8, gbr), r0 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movb9_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8))));
+ SET_H_GRC (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movb10-compact: mov.b @($imm4, $rm), r0 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movb10_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movb5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4))));
+ SET_H_GRC (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movl1-compact: mov.l $rm, @$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movl1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (FLD (f_rm));
+ SETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movl2-compact: mov.l $rm, @-$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movl2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ SI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
+ {
+ SI opval = GET_H_GRC (FLD (f_rm));
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* movl3-compact: mov.l $rm, @(r0, $rn) */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movl3_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (FLD (f_rm));
+ SETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movl4-compact: mov.l r0, @($imm8x4, gbr) */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movl4_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (((UINT) 0));
+ SETMEMSI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x4)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movl5-compact: mov.l $rm, @($imm4x4, $rn) */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movl5_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (FLD (f_rm));
+ SETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm4x4)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movl6-compact: mov.l @$rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movl6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movl7-compact: mov.l @${rm}+, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movl7_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ SI opval = GETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+if (EQSI (FLD (f_rm), FLD (f_rn))) {
+ {
+ SI opval = GET_H_GRC (FLD (f_rn));
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 4);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 5);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* movl8-compact: mov.l @(r0, $rm), $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movl8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm))));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movl9-compact: mov.l @($imm8x4, gbr), r0 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movl9_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x4)));
+ SET_H_GRC (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movl10-compact: mov.l @($imm8x4, pc), $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movl10_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_imm8x4), ANDDI (ADDDI (pc, 4), INVSI (3))));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movl11-compact: mov.l @($imm4x4, $rm), $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movl11_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GETMEMSI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x4)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movw1-compact: mov.w $rm, @$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movw1_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1);
+ SETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movw2-compact: mov.w $rm, @-$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movw2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 2);
+ {
+ HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1);
+ SETMEMHI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* movw3-compact: mov.w $rm, @(r0, $rn) */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movw3_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ HI opval = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1);
+ SETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rn))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movw4-compact: mov.w r0, @($imm8x2, gbr) */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movw4_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ HI opval = SUBWORDSIHI (GET_H_GRC (((UINT) 0)), 1);
+ SETMEMHI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x2)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movw5-compact: mov.w r0, @($imm4x2, $rn) */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movw5_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ HI opval = SUBWORDSIHI (GET_H_GRC (((UINT) 0)), 1);
+ SETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rn)), FLD (f_imm4x2)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movw6-compact: mov.w @$rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movw6_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm))));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movw7-compact: mov.w @${rm}+, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movw7_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ HI tmp_data;
+ tmp_data = GETMEMHI (current_cpu, pc, GET_H_GRC (FLD (f_rm)));
+if (EQSI (FLD (f_rm), FLD (f_rn))) {
+ {
+ SI opval = EXTHISI (tmp_data);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+} else {
+ {
+ SI opval = ADDSI (GET_H_GRC (FLD (f_rm)), 2);
+ SET_H_GRC (FLD (f_rm), opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "rm", 'x', opval);
+ }
+}
+ {
+ SI opval = EXTHISI (tmp_data);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* movw8-compact: mov.w @(r0, $rm), $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movw8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GRC (FLD (f_rm)))));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movw9-compact: mov.w @($imm8x2, gbr), r0 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movw9_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GBR (), FLD (f_imm8x2))));
+ SET_H_GRC (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movw10-compact: mov.w @($imm8x2, pc), $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movw10_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDDI (ADDDI (pc, 4), FLD (f_imm8x2))));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movw11-compact: mov.w @($imm4x2, $rm), r0 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movw11_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw11_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (GET_H_GRC (FLD (f_rm)), FLD (f_imm4x2))));
+ SET_H_GRC (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mova-compact: mova @($imm8x4, pc), r0 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,mova_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ADDDI (ANDDI (ADDDI (pc, 4), INVSI (3)), FLD (f_imm8x4));
+ SET_H_GRC (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movcal-compact: movca.l r0, @$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movcal_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GRC (((UINT) 0));
+ SETMEMSI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* movt-compact: movt $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,movt_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ZEXTBISI (GET_H_TBIT ());
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mull-compact: mul.l $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,mull_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = MULSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn)));
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mulsw-compact: muls.w $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,mulsw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = MULSI (EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)), EXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rn)), 1)));
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* muluw-compact: mulu.w $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,muluw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = MULSI (ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 1)), ZEXTHISI (SUBWORDSIHI (GET_H_GRC (FLD (f_rn)), 1)));
+ SET_H_MACL (opval);
+ TRACE_RESULT (current_cpu, abuf, "macl", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* neg-compact: neg $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,neg_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = NEGSI (GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* negc-compact: negc $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,negc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_flag;
+ tmp_flag = SUBCFSI (0, GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
+ {
+ SI opval = SUBCSI (0, GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = tmp_flag;
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* nop-compact: nop */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,nop_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* not-compact: not $rm64, $rn64 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,not_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = INVDI (GET_H_GR (FLD (f_rm)));
+ SET_H_GR (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ocbi-compact: ocbi @$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,ocbi_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* ocbp-compact: ocbp @$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,ocbp_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* ocbwb-compact: ocbwb @$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,ocbwb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* or-compact: or $rm64, $rn64 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,or_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = ORDI (GET_H_GR (FLD (f_rm)), GET_H_GR (FLD (f_rn)));
+ SET_H_GR (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ori-compact: or #$uimm8, r0 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,ori_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ORSI (GET_H_GRC (((UINT) 0)), ZEXTSIDI (FLD (f_imm8)));
+ SET_H_GRC (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "r0", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* orb-compact: or.b #$imm8, @(r0, gbr) */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,orb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ UQI tmp_data;
+ tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ());
+ tmp_data = ORQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8));
+ {
+ UQI opval = tmp_data;
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* pref-compact: pref @$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,pref_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* rotcl-compact: rotcl $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,rotcl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_temp;
+ tmp_temp = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
+ {
+ SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), GET_H_TBIT ());
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_temp) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rotcr-compact: rotcr $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,rotcr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_lsbit;
+ SI tmp_temp;
+ tmp_lsbit = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rn)), 1), 0)) ? (0) : (1));
+ tmp_temp = GET_H_TBIT ();
+ {
+ SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rn)), 1), SLLSI (tmp_temp, 31));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_lsbit) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rotl-compact: rotl $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,rotl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_temp;
+ tmp_temp = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
+ {
+ SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rn)), 1), tmp_temp);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_temp) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rotr-compact: rotr $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,rotr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_lsbit;
+ SI tmp_temp;
+ tmp_lsbit = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rn)), 1), 0)) ? (0) : (1));
+ tmp_temp = tmp_lsbit;
+ {
+ SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rn)), 1), SLLSI (tmp_temp, 31));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_lsbit) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* rts-compact: rts */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,rts_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ {
+ UDI opval = GET_H_PR ();
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* sets-compact: sets */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,sets_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = 1;
+ SET_H_SBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "sbit", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* sett-compact: sett */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,sett_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = 1;
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shad-compact: shad $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,shad_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_shamt;
+ tmp_shamt = ANDQI (GET_H_GRC (FLD (f_rm)), 31);
+if (GESI (GET_H_GRC (FLD (f_rm)), 0)) {
+ {
+ SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), tmp_shamt);
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+} else {
+if (NEQI (tmp_shamt, 0)) {
+ {
+ SI opval = SRASI (GET_H_GRC (FLD (f_rn)), SUBSI (32, tmp_shamt));
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+} else {
+if (LTSI (GET_H_GRC (FLD (f_rn)), 0)) {
+ {
+ SI opval = NEGSI (1);
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+} else {
+ {
+ SI opval = 0;
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* shal-compact: shal $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,shal_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_t;
+ tmp_t = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
+ {
+ SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 1);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_t) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* shar-compact: shar $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,shar_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_t;
+ tmp_t = ANDSI (GET_H_GRC (FLD (f_rn)), 1);
+ {
+ SI opval = SRASI (GET_H_GRC (FLD (f_rn)), 1);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_t) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* shld-compact: shld $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,shld_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ QI tmp_shamt;
+ tmp_shamt = ANDQI (GET_H_GRC (FLD (f_rm)), 31);
+if (GESI (GET_H_GRC (FLD (f_rm)), 0)) {
+ {
+ SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), tmp_shamt);
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+} else {
+if (NEQI (tmp_shamt, 0)) {
+ {
+ SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), SUBSI (32, tmp_shamt));
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+} else {
+ {
+ SI opval = 0;
+ SET_H_GRC (FLD (f_rn), opval);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* shll-compact: shll $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,shll_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_t;
+ tmp_t = SRLSI (GET_H_GRC (FLD (f_rn)), 31);
+ {
+ SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 1);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_t) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* shll2-compact: shll2 $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,shll2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 2);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shll8-compact: shll8 $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,shll8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 8);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shll16-compact: shll16 $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,shll16_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SLLSI (GET_H_GRC (FLD (f_rn)), 16);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shlr-compact: shlr $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,shlr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_t;
+ tmp_t = ANDSI (GET_H_GRC (FLD (f_rn)), 1);
+ {
+ SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 1);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_t) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* shlr2-compact: shlr2 $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,shlr2_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 2);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shlr8-compact: shlr8 $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,shlr8_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 8);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shlr16-compact: shlr16 $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,shlr16_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SRLSI (GET_H_GRC (FLD (f_rn)), 16);
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stc-gbr-compact: stc gbr, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,stc_gbr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_GBR ();
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stcl-gbr-compact: stc.l gbr, @-$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,stcl_gbr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
+ {
+ SI opval = GET_H_GBR ();
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sts-fpscr-compact: sts fpscr, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,sts_fpscr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_FPCCR ();
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stsl-fpscr-compact: sts.l fpscr, @-$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,stsl_fpscr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
+ {
+ SI opval = GET_H_FPCCR ();
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sts-fpul-compact: sts fpul, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,sts_fpul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SUBWORDSFSI (CPU (h_fr[((UINT) 32)]));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stsl-fpul-compact: sts.l fpul, @-$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,stsl_fpul_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
+ {
+ SF opval = CPU (h_fr[((UINT) 32)]);
+ SETMEMSF (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sts-mach-compact: sts mach, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,sts_mach_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_MACH ();
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stsl-mach-compact: sts.l mach, @-$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,stsl_mach_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
+ {
+ SI opval = GET_H_MACH ();
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sts-macl-compact: sts macl, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,sts_macl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_MACL ();
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stsl-macl-compact: sts.l macl, @-$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,stsl_macl_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
+ {
+ SI opval = GET_H_MACL ();
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sts-pr-compact: sts pr, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,sts_pr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = GET_H_PR ();
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stsl-pr-compact: sts.l pr, @-$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,stsl_pr_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = SUBSI (GET_H_GRC (FLD (f_rn)), 4);
+ {
+ SI opval = GET_H_PR ();
+ SETMEMSI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ {
+ SI opval = tmp_addr;
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* sub-compact: sub $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,sub_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* subc-compact: subc $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,subc_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_flag;
+ tmp_flag = SUBCFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
+ {
+ SI opval = SUBCSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), GET_H_TBIT ());
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = tmp_flag;
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* subv-compact: subv $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,subv_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ BI tmp_t;
+ tmp_t = SUBOFSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)), 0);
+ {
+ SI opval = SUBSI (GET_H_GRC (FLD (f_rn)), GET_H_GRC (FLD (f_rm)));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+ {
+ BI opval = ((tmp_t) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* swapb-compact: swap.b $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,swapb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ UHI tmp_top_half;
+ UQI tmp_byte1;
+ UQI tmp_byte0;
+ tmp_top_half = SUBWORDSIHI (GET_H_GRC (FLD (f_rm)), 0);
+ tmp_byte1 = SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 2);
+ tmp_byte0 = SUBWORDSIQI (GET_H_GRC (FLD (f_rm)), 3);
+ {
+ SI opval = ORSI (SLLSI (tmp_top_half, 16), ORSI (SLLSI (tmp_byte0, 8), tmp_byte1));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* swapw-compact: swap.w $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,swapw_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ORSI (SRLSI (GET_H_GRC (FLD (f_rm)), 16), SLLSI (GET_H_GRC (FLD (f_rm)), 16));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* tasb-compact: tas.b @$rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,tasb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movw10_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ UQI tmp_byte;
+ tmp_byte = GETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn)));
+ {
+ BI opval = ((EQQI (tmp_byte, 0)) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+ tmp_byte = ORQI (tmp_byte, 128);
+ {
+ UQI opval = tmp_byte;
+ SETMEMUQI (current_cpu, pc, GET_H_GRC (FLD (f_rn)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* trapa-compact: trapa #$uimm8 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,trapa_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+sh64_compact_trapa (current_cpu, FLD (f_imm8), pc);
+
+ return vpc;
+#undef FLD
+}
+
+/* tst-compact: tst $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,tst_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_GRC (FLD (f_rm)), GET_H_GRC (FLD (f_rn))), 0)) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* tsti-compact: tst #$uimm8, r0 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,tsti_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ BI opval = ((EQSI (ANDSI (GET_H_GRC (((UINT) 0)), ZEXTSISI (FLD (f_imm8))), 0)) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* tstb-compact: tst.b #$imm8, @(r0, gbr) */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,tstb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ());
+ {
+ BI opval = ((EQQI (ANDQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8)), 0)) ? (1) : (0));
+ SET_H_TBIT (opval);
+ TRACE_RESULT (current_cpu, abuf, "tbit", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* xor-compact: xor $rm64, $rn64 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,xor_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = XORDI (GET_H_GR (FLD (f_rn)), GET_H_GR (FLD (f_rm)));
+ SET_H_GR (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn64", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* xori-compact: xor #$uimm8, r0 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,xori_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ DI opval = XORDI (GET_H_GR (((UINT) 0)), ZEXTSIDI (FLD (f_imm8)));
+ SET_H_GR (((UINT) 0), opval);
+ TRACE_RESULT (current_cpu, abuf, "gr-0", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* xorb-compact: xor.b #$imm8, @(r0, gbr) */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,xorb_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+{
+ DI tmp_addr;
+ UQI tmp_data;
+ tmp_addr = ADDSI (GET_H_GRC (((UINT) 0)), GET_H_GBR ());
+ tmp_data = XORQI (GETMEMUQI (current_cpu, pc, tmp_addr), FLD (f_imm8));
+ {
+ UQI opval = tmp_data;
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* xtrct-compact: xtrct $rm, $rn */
+
+static SEM_PC
+SEM_FN_NAME (sh64_compact,xtrct_compact) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movl5_compact.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
+
+ {
+ SI opval = ORSI (SLLSI (GET_H_GRC (FLD (f_rm)), 16), SRLSI (GET_H_GRC (FLD (f_rn)), 16));
+ SET_H_GRC (FLD (f_rn), opval);
+ TRACE_RESULT (current_cpu, abuf, "rn", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* Table of all semantic fns. */
+
+static const struct sem_fn_desc sem_fns[] = {
+ { SH64_COMPACT_INSN_X_INVALID, SEM_FN_NAME (sh64_compact,x_invalid) },
+ { SH64_COMPACT_INSN_X_AFTER, SEM_FN_NAME (sh64_compact,x_after) },
+ { SH64_COMPACT_INSN_X_BEFORE, SEM_FN_NAME (sh64_compact,x_before) },
+ { SH64_COMPACT_INSN_X_CTI_CHAIN, SEM_FN_NAME (sh64_compact,x_cti_chain) },
+ { SH64_COMPACT_INSN_X_CHAIN, SEM_FN_NAME (sh64_compact,x_chain) },
+ { SH64_COMPACT_INSN_X_BEGIN, SEM_FN_NAME (sh64_compact,x_begin) },
+ { SH64_COMPACT_INSN_ADD_COMPACT, SEM_FN_NAME (sh64_compact,add_compact) },
+ { SH64_COMPACT_INSN_ADDI_COMPACT, SEM_FN_NAME (sh64_compact,addi_compact) },
+ { SH64_COMPACT_INSN_ADDC_COMPACT, SEM_FN_NAME (sh64_compact,addc_compact) },
+ { SH64_COMPACT_INSN_ADDV_COMPACT, SEM_FN_NAME (sh64_compact,addv_compact) },
+ { SH64_COMPACT_INSN_AND_COMPACT, SEM_FN_NAME (sh64_compact,and_compact) },
+ { SH64_COMPACT_INSN_ANDI_COMPACT, SEM_FN_NAME (sh64_compact,andi_compact) },
+ { SH64_COMPACT_INSN_ANDB_COMPACT, SEM_FN_NAME (sh64_compact,andb_compact) },
+ { SH64_COMPACT_INSN_BF_COMPACT, SEM_FN_NAME (sh64_compact,bf_compact) },
+ { SH64_COMPACT_INSN_BFS_COMPACT, SEM_FN_NAME (sh64_compact,bfs_compact) },
+ { SH64_COMPACT_INSN_BRA_COMPACT, SEM_FN_NAME (sh64_compact,bra_compact) },
+ { SH64_COMPACT_INSN_BRAF_COMPACT, SEM_FN_NAME (sh64_compact,braf_compact) },
+ { SH64_COMPACT_INSN_BRK_COMPACT, SEM_FN_NAME (sh64_compact,brk_compact) },
+ { SH64_COMPACT_INSN_BSR_COMPACT, SEM_FN_NAME (sh64_compact,bsr_compact) },
+ { SH64_COMPACT_INSN_BSRF_COMPACT, SEM_FN_NAME (sh64_compact,bsrf_compact) },
+ { SH64_COMPACT_INSN_BT_COMPACT, SEM_FN_NAME (sh64_compact,bt_compact) },
+ { SH64_COMPACT_INSN_BTS_COMPACT, SEM_FN_NAME (sh64_compact,bts_compact) },
+ { SH64_COMPACT_INSN_CLRMAC_COMPACT, SEM_FN_NAME (sh64_compact,clrmac_compact) },
+ { SH64_COMPACT_INSN_CLRS_COMPACT, SEM_FN_NAME (sh64_compact,clrs_compact) },
+ { SH64_COMPACT_INSN_CLRT_COMPACT, SEM_FN_NAME (sh64_compact,clrt_compact) },
+ { SH64_COMPACT_INSN_CMPEQ_COMPACT, SEM_FN_NAME (sh64_compact,cmpeq_compact) },
+ { SH64_COMPACT_INSN_CMPEQI_COMPACT, SEM_FN_NAME (sh64_compact,cmpeqi_compact) },
+ { SH64_COMPACT_INSN_CMPGE_COMPACT, SEM_FN_NAME (sh64_compact,cmpge_compact) },
+ { SH64_COMPACT_INSN_CMPGT_COMPACT, SEM_FN_NAME (sh64_compact,cmpgt_compact) },
+ { SH64_COMPACT_INSN_CMPHI_COMPACT, SEM_FN_NAME (sh64_compact,cmphi_compact) },
+ { SH64_COMPACT_INSN_CMPHS_COMPACT, SEM_FN_NAME (sh64_compact,cmphs_compact) },
+ { SH64_COMPACT_INSN_CMPPL_COMPACT, SEM_FN_NAME (sh64_compact,cmppl_compact) },
+ { SH64_COMPACT_INSN_CMPPZ_COMPACT, SEM_FN_NAME (sh64_compact,cmppz_compact) },
+ { SH64_COMPACT_INSN_CMPSTR_COMPACT, SEM_FN_NAME (sh64_compact,cmpstr_compact) },
+ { SH64_COMPACT_INSN_DIV0S_COMPACT, SEM_FN_NAME (sh64_compact,div0s_compact) },
+ { SH64_COMPACT_INSN_DIV0U_COMPACT, SEM_FN_NAME (sh64_compact,div0u_compact) },
+ { SH64_COMPACT_INSN_DIV1_COMPACT, SEM_FN_NAME (sh64_compact,div1_compact) },
+ { SH64_COMPACT_INSN_DMULSL_COMPACT, SEM_FN_NAME (sh64_compact,dmulsl_compact) },
+ { SH64_COMPACT_INSN_DMULUL_COMPACT, SEM_FN_NAME (sh64_compact,dmulul_compact) },
+ { SH64_COMPACT_INSN_DT_COMPACT, SEM_FN_NAME (sh64_compact,dt_compact) },
+ { SH64_COMPACT_INSN_EXTSB_COMPACT, SEM_FN_NAME (sh64_compact,extsb_compact) },
+ { SH64_COMPACT_INSN_EXTSW_COMPACT, SEM_FN_NAME (sh64_compact,extsw_compact) },
+ { SH64_COMPACT_INSN_EXTUB_COMPACT, SEM_FN_NAME (sh64_compact,extub_compact) },
+ { SH64_COMPACT_INSN_EXTUW_COMPACT, SEM_FN_NAME (sh64_compact,extuw_compact) },
+ { SH64_COMPACT_INSN_FABS_COMPACT, SEM_FN_NAME (sh64_compact,fabs_compact) },
+ { SH64_COMPACT_INSN_FADD_COMPACT, SEM_FN_NAME (sh64_compact,fadd_compact) },
+ { SH64_COMPACT_INSN_FCMPEQ_COMPACT, SEM_FN_NAME (sh64_compact,fcmpeq_compact) },
+ { SH64_COMPACT_INSN_FCMPGT_COMPACT, SEM_FN_NAME (sh64_compact,fcmpgt_compact) },
+ { SH64_COMPACT_INSN_FCNVDS_COMPACT, SEM_FN_NAME (sh64_compact,fcnvds_compact) },
+ { SH64_COMPACT_INSN_FCNVSD_COMPACT, SEM_FN_NAME (sh64_compact,fcnvsd_compact) },
+ { SH64_COMPACT_INSN_FDIV_COMPACT, SEM_FN_NAME (sh64_compact,fdiv_compact) },
+ { SH64_COMPACT_INSN_FIPR_COMPACT, SEM_FN_NAME (sh64_compact,fipr_compact) },
+ { SH64_COMPACT_INSN_FLDS_COMPACT, SEM_FN_NAME (sh64_compact,flds_compact) },
+ { SH64_COMPACT_INSN_FLDI0_COMPACT, SEM_FN_NAME (sh64_compact,fldi0_compact) },
+ { SH64_COMPACT_INSN_FLDI1_COMPACT, SEM_FN_NAME (sh64_compact,fldi1_compact) },
+ { SH64_COMPACT_INSN_FLOAT_COMPACT, SEM_FN_NAME (sh64_compact,float_compact) },
+ { SH64_COMPACT_INSN_FMAC_COMPACT, SEM_FN_NAME (sh64_compact,fmac_compact) },
+ { SH64_COMPACT_INSN_FMOV1_COMPACT, SEM_FN_NAME (sh64_compact,fmov1_compact) },
+ { SH64_COMPACT_INSN_FMOV2_COMPACT, SEM_FN_NAME (sh64_compact,fmov2_compact) },
+ { SH64_COMPACT_INSN_FMOV3_COMPACT, SEM_FN_NAME (sh64_compact,fmov3_compact) },
+ { SH64_COMPACT_INSN_FMOV4_COMPACT, SEM_FN_NAME (sh64_compact,fmov4_compact) },
+ { SH64_COMPACT_INSN_FMOV5_COMPACT, SEM_FN_NAME (sh64_compact,fmov5_compact) },
+ { SH64_COMPACT_INSN_FMOV6_COMPACT, SEM_FN_NAME (sh64_compact,fmov6_compact) },
+ { SH64_COMPACT_INSN_FMOV7_COMPACT, SEM_FN_NAME (sh64_compact,fmov7_compact) },
+ { SH64_COMPACT_INSN_FMUL_COMPACT, SEM_FN_NAME (sh64_compact,fmul_compact) },
+ { SH64_COMPACT_INSN_FNEG_COMPACT, SEM_FN_NAME (sh64_compact,fneg_compact) },
+ { SH64_COMPACT_INSN_FRCHG_COMPACT, SEM_FN_NAME (sh64_compact,frchg_compact) },
+ { SH64_COMPACT_INSN_FSCHG_COMPACT, SEM_FN_NAME (sh64_compact,fschg_compact) },
+ { SH64_COMPACT_INSN_FSQRT_COMPACT, SEM_FN_NAME (sh64_compact,fsqrt_compact) },
+ { SH64_COMPACT_INSN_FSTS_COMPACT, SEM_FN_NAME (sh64_compact,fsts_compact) },
+ { SH64_COMPACT_INSN_FSUB_COMPACT, SEM_FN_NAME (sh64_compact,fsub_compact) },
+ { SH64_COMPACT_INSN_FTRC_COMPACT, SEM_FN_NAME (sh64_compact,ftrc_compact) },
+ { SH64_COMPACT_INSN_FTRV_COMPACT, SEM_FN_NAME (sh64_compact,ftrv_compact) },
+ { SH64_COMPACT_INSN_JMP_COMPACT, SEM_FN_NAME (sh64_compact,jmp_compact) },
+ { SH64_COMPACT_INSN_JSR_COMPACT, SEM_FN_NAME (sh64_compact,jsr_compact) },
+ { SH64_COMPACT_INSN_LDC_COMPACT, SEM_FN_NAME (sh64_compact,ldc_compact) },
+ { SH64_COMPACT_INSN_LDCL_COMPACT, SEM_FN_NAME (sh64_compact,ldcl_compact) },
+ { SH64_COMPACT_INSN_LDS_FPSCR_COMPACT, SEM_FN_NAME (sh64_compact,lds_fpscr_compact) },
+ { SH64_COMPACT_INSN_LDSL_FPSCR_COMPACT, SEM_FN_NAME (sh64_compact,ldsl_fpscr_compact) },
+ { SH64_COMPACT_INSN_LDS_FPUL_COMPACT, SEM_FN_NAME (sh64_compact,lds_fpul_compact) },
+ { SH64_COMPACT_INSN_LDSL_FPUL_COMPACT, SEM_FN_NAME (sh64_compact,ldsl_fpul_compact) },
+ { SH64_COMPACT_INSN_LDS_MACH_COMPACT, SEM_FN_NAME (sh64_compact,lds_mach_compact) },
+ { SH64_COMPACT_INSN_LDSL_MACH_COMPACT, SEM_FN_NAME (sh64_compact,ldsl_mach_compact) },
+ { SH64_COMPACT_INSN_LDS_MACL_COMPACT, SEM_FN_NAME (sh64_compact,lds_macl_compact) },
+ { SH64_COMPACT_INSN_LDSL_MACL_COMPACT, SEM_FN_NAME (sh64_compact,ldsl_macl_compact) },
+ { SH64_COMPACT_INSN_LDS_PR_COMPACT, SEM_FN_NAME (sh64_compact,lds_pr_compact) },
+ { SH64_COMPACT_INSN_LDSL_PR_COMPACT, SEM_FN_NAME (sh64_compact,ldsl_pr_compact) },
+ { SH64_COMPACT_INSN_MACL_COMPACT, SEM_FN_NAME (sh64_compact,macl_compact) },
+ { SH64_COMPACT_INSN_MACW_COMPACT, SEM_FN_NAME (sh64_compact,macw_compact) },
+ { SH64_COMPACT_INSN_MOV_COMPACT, SEM_FN_NAME (sh64_compact,mov_compact) },
+ { SH64_COMPACT_INSN_MOVI_COMPACT, SEM_FN_NAME (sh64_compact,movi_compact) },
+ { SH64_COMPACT_INSN_MOVB1_COMPACT, SEM_FN_NAME (sh64_compact,movb1_compact) },
+ { SH64_COMPACT_INSN_MOVB2_COMPACT, SEM_FN_NAME (sh64_compact,movb2_compact) },
+ { SH64_COMPACT_INSN_MOVB3_COMPACT, SEM_FN_NAME (sh64_compact,movb3_compact) },
+ { SH64_COMPACT_INSN_MOVB4_COMPACT, SEM_FN_NAME (sh64_compact,movb4_compact) },
+ { SH64_COMPACT_INSN_MOVB5_COMPACT, SEM_FN_NAME (sh64_compact,movb5_compact) },
+ { SH64_COMPACT_INSN_MOVB6_COMPACT, SEM_FN_NAME (sh64_compact,movb6_compact) },
+ { SH64_COMPACT_INSN_MOVB7_COMPACT, SEM_FN_NAME (sh64_compact,movb7_compact) },
+ { SH64_COMPACT_INSN_MOVB8_COMPACT, SEM_FN_NAME (sh64_compact,movb8_compact) },
+ { SH64_COMPACT_INSN_MOVB9_COMPACT, SEM_FN_NAME (sh64_compact,movb9_compact) },
+ { SH64_COMPACT_INSN_MOVB10_COMPACT, SEM_FN_NAME (sh64_compact,movb10_compact) },
+ { SH64_COMPACT_INSN_MOVL1_COMPACT, SEM_FN_NAME (sh64_compact,movl1_compact) },
+ { SH64_COMPACT_INSN_MOVL2_COMPACT, SEM_FN_NAME (sh64_compact,movl2_compact) },
+ { SH64_COMPACT_INSN_MOVL3_COMPACT, SEM_FN_NAME (sh64_compact,movl3_compact) },
+ { SH64_COMPACT_INSN_MOVL4_COMPACT, SEM_FN_NAME (sh64_compact,movl4_compact) },
+ { SH64_COMPACT_INSN_MOVL5_COMPACT, SEM_FN_NAME (sh64_compact,movl5_compact) },
+ { SH64_COMPACT_INSN_MOVL6_COMPACT, SEM_FN_NAME (sh64_compact,movl6_compact) },
+ { SH64_COMPACT_INSN_MOVL7_COMPACT, SEM_FN_NAME (sh64_compact,movl7_compact) },
+ { SH64_COMPACT_INSN_MOVL8_COMPACT, SEM_FN_NAME (sh64_compact,movl8_compact) },
+ { SH64_COMPACT_INSN_MOVL9_COMPACT, SEM_FN_NAME (sh64_compact,movl9_compact) },
+ { SH64_COMPACT_INSN_MOVL10_COMPACT, SEM_FN_NAME (sh64_compact,movl10_compact) },
+ { SH64_COMPACT_INSN_MOVL11_COMPACT, SEM_FN_NAME (sh64_compact,movl11_compact) },
+ { SH64_COMPACT_INSN_MOVW1_COMPACT, SEM_FN_NAME (sh64_compact,movw1_compact) },
+ { SH64_COMPACT_INSN_MOVW2_COMPACT, SEM_FN_NAME (sh64_compact,movw2_compact) },
+ { SH64_COMPACT_INSN_MOVW3_COMPACT, SEM_FN_NAME (sh64_compact,movw3_compact) },
+ { SH64_COMPACT_INSN_MOVW4_COMPACT, SEM_FN_NAME (sh64_compact,movw4_compact) },
+ { SH64_COMPACT_INSN_MOVW5_COMPACT, SEM_FN_NAME (sh64_compact,movw5_compact) },
+ { SH64_COMPACT_INSN_MOVW6_COMPACT, SEM_FN_NAME (sh64_compact,movw6_compact) },
+ { SH64_COMPACT_INSN_MOVW7_COMPACT, SEM_FN_NAME (sh64_compact,movw7_compact) },
+ { SH64_COMPACT_INSN_MOVW8_COMPACT, SEM_FN_NAME (sh64_compact,movw8_compact) },
+ { SH64_COMPACT_INSN_MOVW9_COMPACT, SEM_FN_NAME (sh64_compact,movw9_compact) },
+ { SH64_COMPACT_INSN_MOVW10_COMPACT, SEM_FN_NAME (sh64_compact,movw10_compact) },
+ { SH64_COMPACT_INSN_MOVW11_COMPACT, SEM_FN_NAME (sh64_compact,movw11_compact) },
+ { SH64_COMPACT_INSN_MOVA_COMPACT, SEM_FN_NAME (sh64_compact,mova_compact) },
+ { SH64_COMPACT_INSN_MOVCAL_COMPACT, SEM_FN_NAME (sh64_compact,movcal_compact) },
+ { SH64_COMPACT_INSN_MOVT_COMPACT, SEM_FN_NAME (sh64_compact,movt_compact) },
+ { SH64_COMPACT_INSN_MULL_COMPACT, SEM_FN_NAME (sh64_compact,mull_compact) },
+ { SH64_COMPACT_INSN_MULSW_COMPACT, SEM_FN_NAME (sh64_compact,mulsw_compact) },
+ { SH64_COMPACT_INSN_MULUW_COMPACT, SEM_FN_NAME (sh64_compact,muluw_compact) },
+ { SH64_COMPACT_INSN_NEG_COMPACT, SEM_FN_NAME (sh64_compact,neg_compact) },
+ { SH64_COMPACT_INSN_NEGC_COMPACT, SEM_FN_NAME (sh64_compact,negc_compact) },
+ { SH64_COMPACT_INSN_NOP_COMPACT, SEM_FN_NAME (sh64_compact,nop_compact) },
+ { SH64_COMPACT_INSN_NOT_COMPACT, SEM_FN_NAME (sh64_compact,not_compact) },
+ { SH64_COMPACT_INSN_OCBI_COMPACT, SEM_FN_NAME (sh64_compact,ocbi_compact) },
+ { SH64_COMPACT_INSN_OCBP_COMPACT, SEM_FN_NAME (sh64_compact,ocbp_compact) },
+ { SH64_COMPACT_INSN_OCBWB_COMPACT, SEM_FN_NAME (sh64_compact,ocbwb_compact) },
+ { SH64_COMPACT_INSN_OR_COMPACT, SEM_FN_NAME (sh64_compact,or_compact) },
+ { SH64_COMPACT_INSN_ORI_COMPACT, SEM_FN_NAME (sh64_compact,ori_compact) },
+ { SH64_COMPACT_INSN_ORB_COMPACT, SEM_FN_NAME (sh64_compact,orb_compact) },
+ { SH64_COMPACT_INSN_PREF_COMPACT, SEM_FN_NAME (sh64_compact,pref_compact) },
+ { SH64_COMPACT_INSN_ROTCL_COMPACT, SEM_FN_NAME (sh64_compact,rotcl_compact) },
+ { SH64_COMPACT_INSN_ROTCR_COMPACT, SEM_FN_NAME (sh64_compact,rotcr_compact) },
+ { SH64_COMPACT_INSN_ROTL_COMPACT, SEM_FN_NAME (sh64_compact,rotl_compact) },
+ { SH64_COMPACT_INSN_ROTR_COMPACT, SEM_FN_NAME (sh64_compact,rotr_compact) },
+ { SH64_COMPACT_INSN_RTS_COMPACT, SEM_FN_NAME (sh64_compact,rts_compact) },
+ { SH64_COMPACT_INSN_SETS_COMPACT, SEM_FN_NAME (sh64_compact,sets_compact) },
+ { SH64_COMPACT_INSN_SETT_COMPACT, SEM_FN_NAME (sh64_compact,sett_compact) },
+ { SH64_COMPACT_INSN_SHAD_COMPACT, SEM_FN_NAME (sh64_compact,shad_compact) },
+ { SH64_COMPACT_INSN_SHAL_COMPACT, SEM_FN_NAME (sh64_compact,shal_compact) },
+ { SH64_COMPACT_INSN_SHAR_COMPACT, SEM_FN_NAME (sh64_compact,shar_compact) },
+ { SH64_COMPACT_INSN_SHLD_COMPACT, SEM_FN_NAME (sh64_compact,shld_compact) },
+ { SH64_COMPACT_INSN_SHLL_COMPACT, SEM_FN_NAME (sh64_compact,shll_compact) },
+ { SH64_COMPACT_INSN_SHLL2_COMPACT, SEM_FN_NAME (sh64_compact,shll2_compact) },
+ { SH64_COMPACT_INSN_SHLL8_COMPACT, SEM_FN_NAME (sh64_compact,shll8_compact) },
+ { SH64_COMPACT_INSN_SHLL16_COMPACT, SEM_FN_NAME (sh64_compact,shll16_compact) },
+ { SH64_COMPACT_INSN_SHLR_COMPACT, SEM_FN_NAME (sh64_compact,shlr_compact) },
+ { SH64_COMPACT_INSN_SHLR2_COMPACT, SEM_FN_NAME (sh64_compact,shlr2_compact) },
+ { SH64_COMPACT_INSN_SHLR8_COMPACT, SEM_FN_NAME (sh64_compact,shlr8_compact) },
+ { SH64_COMPACT_INSN_SHLR16_COMPACT, SEM_FN_NAME (sh64_compact,shlr16_compact) },
+ { SH64_COMPACT_INSN_STC_GBR_COMPACT, SEM_FN_NAME (sh64_compact,stc_gbr_compact) },
+ { SH64_COMPACT_INSN_STCL_GBR_COMPACT, SEM_FN_NAME (sh64_compact,stcl_gbr_compact) },
+ { SH64_COMPACT_INSN_STS_FPSCR_COMPACT, SEM_FN_NAME (sh64_compact,sts_fpscr_compact) },
+ { SH64_COMPACT_INSN_STSL_FPSCR_COMPACT, SEM_FN_NAME (sh64_compact,stsl_fpscr_compact) },
+ { SH64_COMPACT_INSN_STS_FPUL_COMPACT, SEM_FN_NAME (sh64_compact,sts_fpul_compact) },
+ { SH64_COMPACT_INSN_STSL_FPUL_COMPACT, SEM_FN_NAME (sh64_compact,stsl_fpul_compact) },
+ { SH64_COMPACT_INSN_STS_MACH_COMPACT, SEM_FN_NAME (sh64_compact,sts_mach_compact) },
+ { SH64_COMPACT_INSN_STSL_MACH_COMPACT, SEM_FN_NAME (sh64_compact,stsl_mach_compact) },
+ { SH64_COMPACT_INSN_STS_MACL_COMPACT, SEM_FN_NAME (sh64_compact,sts_macl_compact) },
+ { SH64_COMPACT_INSN_STSL_MACL_COMPACT, SEM_FN_NAME (sh64_compact,stsl_macl_compact) },
+ { SH64_COMPACT_INSN_STS_PR_COMPACT, SEM_FN_NAME (sh64_compact,sts_pr_compact) },
+ { SH64_COMPACT_INSN_STSL_PR_COMPACT, SEM_FN_NAME (sh64_compact,stsl_pr_compact) },
+ { SH64_COMPACT_INSN_SUB_COMPACT, SEM_FN_NAME (sh64_compact,sub_compact) },
+ { SH64_COMPACT_INSN_SUBC_COMPACT, SEM_FN_NAME (sh64_compact,subc_compact) },
+ { SH64_COMPACT_INSN_SUBV_COMPACT, SEM_FN_NAME (sh64_compact,subv_compact) },
+ { SH64_COMPACT_INSN_SWAPB_COMPACT, SEM_FN_NAME (sh64_compact,swapb_compact) },
+ { SH64_COMPACT_INSN_SWAPW_COMPACT, SEM_FN_NAME (sh64_compact,swapw_compact) },
+ { SH64_COMPACT_INSN_TASB_COMPACT, SEM_FN_NAME (sh64_compact,tasb_compact) },
+ { SH64_COMPACT_INSN_TRAPA_COMPACT, SEM_FN_NAME (sh64_compact,trapa_compact) },
+ { SH64_COMPACT_INSN_TST_COMPACT, SEM_FN_NAME (sh64_compact,tst_compact) },
+ { SH64_COMPACT_INSN_TSTI_COMPACT, SEM_FN_NAME (sh64_compact,tsti_compact) },
+ { SH64_COMPACT_INSN_TSTB_COMPACT, SEM_FN_NAME (sh64_compact,tstb_compact) },
+ { SH64_COMPACT_INSN_XOR_COMPACT, SEM_FN_NAME (sh64_compact,xor_compact) },
+ { SH64_COMPACT_INSN_XORI_COMPACT, SEM_FN_NAME (sh64_compact,xori_compact) },
+ { SH64_COMPACT_INSN_XORB_COMPACT, SEM_FN_NAME (sh64_compact,xorb_compact) },
+ { SH64_COMPACT_INSN_XTRCT_COMPACT, SEM_FN_NAME (sh64_compact,xtrct_compact) },
+ { 0, 0 }
+};
+
+/* Add the semantic fns to IDESC_TABLE. */
+
+void
+SEM_FN_NAME (sh64_compact,init_idesc_table) (SIM_CPU *current_cpu)
+{
+ IDESC *idesc_table = CPU_IDESC (current_cpu);
+ const struct sem_fn_desc *sf;
+ int mach_num = MACH_NUM (CPU_MACH (current_cpu));
+
+ for (sf = &sem_fns[0]; sf->fn != 0; ++sf)
+ {
+ const CGEN_INSN *insn = idesc_table[sf->index].idata;
+ int valid_p = (CGEN_INSN_VIRTUAL_P (insn)
+ || CGEN_INSN_MACH_HAS_P (insn, mach_num));
+#if FAST_P
+ if (valid_p)
+ idesc_table[sf->index].sem_fast = sf->fn;
+ else
+ idesc_table[sf->index].sem_fast = SEM_FN_NAME (sh64_compact,x_invalid);
+#else
+ if (valid_p)
+ idesc_table[sf->index].sem_full = sf->fn;
+ else
+ idesc_table[sf->index].sem_full = SEM_FN_NAME (sh64_compact,x_invalid);
+#endif
+ }
+}
+
--- /dev/null
+/* Simulator instruction semantics for sh64.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifdef DEFINE_LABELS
+
+ /* The labels have the case they have because the enum of insn types
+ is all uppercase and in the non-stdc case the insn symbol is built
+ into the enum name. */
+
+ static struct {
+ int index;
+ void *label;
+ } labels[] = {
+ { SH64_MEDIA_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
+ { SH64_MEDIA_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
+ { SH64_MEDIA_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
+ { SH64_MEDIA_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
+ { SH64_MEDIA_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
+ { SH64_MEDIA_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
+ { SH64_MEDIA_INSN_ADD, && case_sem_INSN_ADD },
+ { SH64_MEDIA_INSN_ADDL, && case_sem_INSN_ADDL },
+ { SH64_MEDIA_INSN_ADDI, && case_sem_INSN_ADDI },
+ { SH64_MEDIA_INSN_ADDIL, && case_sem_INSN_ADDIL },
+ { SH64_MEDIA_INSN_ADDZL, && case_sem_INSN_ADDZL },
+ { SH64_MEDIA_INSN_ALLOCO, && case_sem_INSN_ALLOCO },
+ { SH64_MEDIA_INSN_AND, && case_sem_INSN_AND },
+ { SH64_MEDIA_INSN_ANDC, && case_sem_INSN_ANDC },
+ { SH64_MEDIA_INSN_ANDI, && case_sem_INSN_ANDI },
+ { SH64_MEDIA_INSN_BEQ, && case_sem_INSN_BEQ },
+ { SH64_MEDIA_INSN_BEQI, && case_sem_INSN_BEQI },
+ { SH64_MEDIA_INSN_BGE, && case_sem_INSN_BGE },
+ { SH64_MEDIA_INSN_BGEU, && case_sem_INSN_BGEU },
+ { SH64_MEDIA_INSN_BGT, && case_sem_INSN_BGT },
+ { SH64_MEDIA_INSN_BGTU, && case_sem_INSN_BGTU },
+ { SH64_MEDIA_INSN_BLINK, && case_sem_INSN_BLINK },
+ { SH64_MEDIA_INSN_BNE, && case_sem_INSN_BNE },
+ { SH64_MEDIA_INSN_BNEI, && case_sem_INSN_BNEI },
+ { SH64_MEDIA_INSN_BRK, && case_sem_INSN_BRK },
+ { SH64_MEDIA_INSN_BYTEREV, && case_sem_INSN_BYTEREV },
+ { SH64_MEDIA_INSN_CMPEQ, && case_sem_INSN_CMPEQ },
+ { SH64_MEDIA_INSN_CMPGT, && case_sem_INSN_CMPGT },
+ { SH64_MEDIA_INSN_CMPGTU, && case_sem_INSN_CMPGTU },
+ { SH64_MEDIA_INSN_CMVEQ, && case_sem_INSN_CMVEQ },
+ { SH64_MEDIA_INSN_CMVNE, && case_sem_INSN_CMVNE },
+ { SH64_MEDIA_INSN_FABSD, && case_sem_INSN_FABSD },
+ { SH64_MEDIA_INSN_FABSS, && case_sem_INSN_FABSS },
+ { SH64_MEDIA_INSN_FADDD, && case_sem_INSN_FADDD },
+ { SH64_MEDIA_INSN_FADDS, && case_sem_INSN_FADDS },
+ { SH64_MEDIA_INSN_FCMPEQD, && case_sem_INSN_FCMPEQD },
+ { SH64_MEDIA_INSN_FCMPEQS, && case_sem_INSN_FCMPEQS },
+ { SH64_MEDIA_INSN_FCMPGED, && case_sem_INSN_FCMPGED },
+ { SH64_MEDIA_INSN_FCMPGES, && case_sem_INSN_FCMPGES },
+ { SH64_MEDIA_INSN_FCMPGTD, && case_sem_INSN_FCMPGTD },
+ { SH64_MEDIA_INSN_FCMPGTS, && case_sem_INSN_FCMPGTS },
+ { SH64_MEDIA_INSN_FCMPUND, && case_sem_INSN_FCMPUND },
+ { SH64_MEDIA_INSN_FCMPUNS, && case_sem_INSN_FCMPUNS },
+ { SH64_MEDIA_INSN_FCNVDS, && case_sem_INSN_FCNVDS },
+ { SH64_MEDIA_INSN_FCNVSD, && case_sem_INSN_FCNVSD },
+ { SH64_MEDIA_INSN_FDIVD, && case_sem_INSN_FDIVD },
+ { SH64_MEDIA_INSN_FDIVS, && case_sem_INSN_FDIVS },
+ { SH64_MEDIA_INSN_FGETSCR, && case_sem_INSN_FGETSCR },
+ { SH64_MEDIA_INSN_FIPRS, && case_sem_INSN_FIPRS },
+ { SH64_MEDIA_INSN_FLDD, && case_sem_INSN_FLDD },
+ { SH64_MEDIA_INSN_FLDP, && case_sem_INSN_FLDP },
+ { SH64_MEDIA_INSN_FLDS, && case_sem_INSN_FLDS },
+ { SH64_MEDIA_INSN_FLDXD, && case_sem_INSN_FLDXD },
+ { SH64_MEDIA_INSN_FLDXP, && case_sem_INSN_FLDXP },
+ { SH64_MEDIA_INSN_FLDXS, && case_sem_INSN_FLDXS },
+ { SH64_MEDIA_INSN_FLOATLD, && case_sem_INSN_FLOATLD },
+ { SH64_MEDIA_INSN_FLOATLS, && case_sem_INSN_FLOATLS },
+ { SH64_MEDIA_INSN_FLOATQD, && case_sem_INSN_FLOATQD },
+ { SH64_MEDIA_INSN_FLOATQS, && case_sem_INSN_FLOATQS },
+ { SH64_MEDIA_INSN_FMACS, && case_sem_INSN_FMACS },
+ { SH64_MEDIA_INSN_FMOVD, && case_sem_INSN_FMOVD },
+ { SH64_MEDIA_INSN_FMOVDQ, && case_sem_INSN_FMOVDQ },
+ { SH64_MEDIA_INSN_FMOVLS, && case_sem_INSN_FMOVLS },
+ { SH64_MEDIA_INSN_FMOVQD, && case_sem_INSN_FMOVQD },
+ { SH64_MEDIA_INSN_FMOVS, && case_sem_INSN_FMOVS },
+ { SH64_MEDIA_INSN_FMOVSL, && case_sem_INSN_FMOVSL },
+ { SH64_MEDIA_INSN_FMULD, && case_sem_INSN_FMULD },
+ { SH64_MEDIA_INSN_FMULS, && case_sem_INSN_FMULS },
+ { SH64_MEDIA_INSN_FNEGD, && case_sem_INSN_FNEGD },
+ { SH64_MEDIA_INSN_FNEGS, && case_sem_INSN_FNEGS },
+ { SH64_MEDIA_INSN_FPUTSCR, && case_sem_INSN_FPUTSCR },
+ { SH64_MEDIA_INSN_FSQRTD, && case_sem_INSN_FSQRTD },
+ { SH64_MEDIA_INSN_FSQRTS, && case_sem_INSN_FSQRTS },
+ { SH64_MEDIA_INSN_FSTD, && case_sem_INSN_FSTD },
+ { SH64_MEDIA_INSN_FSTP, && case_sem_INSN_FSTP },
+ { SH64_MEDIA_INSN_FSTS, && case_sem_INSN_FSTS },
+ { SH64_MEDIA_INSN_FSTXD, && case_sem_INSN_FSTXD },
+ { SH64_MEDIA_INSN_FSTXP, && case_sem_INSN_FSTXP },
+ { SH64_MEDIA_INSN_FSTXS, && case_sem_INSN_FSTXS },
+ { SH64_MEDIA_INSN_FSUBD, && case_sem_INSN_FSUBD },
+ { SH64_MEDIA_INSN_FSUBS, && case_sem_INSN_FSUBS },
+ { SH64_MEDIA_INSN_FTRCDL, && case_sem_INSN_FTRCDL },
+ { SH64_MEDIA_INSN_FTRCSL, && case_sem_INSN_FTRCSL },
+ { SH64_MEDIA_INSN_FTRCDQ, && case_sem_INSN_FTRCDQ },
+ { SH64_MEDIA_INSN_FTRCSQ, && case_sem_INSN_FTRCSQ },
+ { SH64_MEDIA_INSN_FTRVS, && case_sem_INSN_FTRVS },
+ { SH64_MEDIA_INSN_GETCFG, && case_sem_INSN_GETCFG },
+ { SH64_MEDIA_INSN_GETCON, && case_sem_INSN_GETCON },
+ { SH64_MEDIA_INSN_GETTR, && case_sem_INSN_GETTR },
+ { SH64_MEDIA_INSN_ICBI, && case_sem_INSN_ICBI },
+ { SH64_MEDIA_INSN_LDB, && case_sem_INSN_LDB },
+ { SH64_MEDIA_INSN_LDL, && case_sem_INSN_LDL },
+ { SH64_MEDIA_INSN_LDQ, && case_sem_INSN_LDQ },
+ { SH64_MEDIA_INSN_LDUB, && case_sem_INSN_LDUB },
+ { SH64_MEDIA_INSN_LDUW, && case_sem_INSN_LDUW },
+ { SH64_MEDIA_INSN_LDW, && case_sem_INSN_LDW },
+ { SH64_MEDIA_INSN_LDHIL, && case_sem_INSN_LDHIL },
+ { SH64_MEDIA_INSN_LDHIQ, && case_sem_INSN_LDHIQ },
+ { SH64_MEDIA_INSN_LDLOL, && case_sem_INSN_LDLOL },
+ { SH64_MEDIA_INSN_LDLOQ, && case_sem_INSN_LDLOQ },
+ { SH64_MEDIA_INSN_LDXB, && case_sem_INSN_LDXB },
+ { SH64_MEDIA_INSN_LDXL, && case_sem_INSN_LDXL },
+ { SH64_MEDIA_INSN_LDXQ, && case_sem_INSN_LDXQ },
+ { SH64_MEDIA_INSN_LDXUB, && case_sem_INSN_LDXUB },
+ { SH64_MEDIA_INSN_LDXUW, && case_sem_INSN_LDXUW },
+ { SH64_MEDIA_INSN_LDXW, && case_sem_INSN_LDXW },
+ { SH64_MEDIA_INSN_MABSL, && case_sem_INSN_MABSL },
+ { SH64_MEDIA_INSN_MABSW, && case_sem_INSN_MABSW },
+ { SH64_MEDIA_INSN_MADDL, && case_sem_INSN_MADDL },
+ { SH64_MEDIA_INSN_MADDW, && case_sem_INSN_MADDW },
+ { SH64_MEDIA_INSN_MADDSL, && case_sem_INSN_MADDSL },
+ { SH64_MEDIA_INSN_MADDSUB, && case_sem_INSN_MADDSUB },
+ { SH64_MEDIA_INSN_MADDSW, && case_sem_INSN_MADDSW },
+ { SH64_MEDIA_INSN_MCMPEQB, && case_sem_INSN_MCMPEQB },
+ { SH64_MEDIA_INSN_MCMPEQL, && case_sem_INSN_MCMPEQL },
+ { SH64_MEDIA_INSN_MCMPEQW, && case_sem_INSN_MCMPEQW },
+ { SH64_MEDIA_INSN_MCMPGTL, && case_sem_INSN_MCMPGTL },
+ { SH64_MEDIA_INSN_MCMPGTUB, && case_sem_INSN_MCMPGTUB },
+ { SH64_MEDIA_INSN_MCMPGTW, && case_sem_INSN_MCMPGTW },
+ { SH64_MEDIA_INSN_MCMV, && case_sem_INSN_MCMV },
+ { SH64_MEDIA_INSN_MCNVSLW, && case_sem_INSN_MCNVSLW },
+ { SH64_MEDIA_INSN_MCNVSWB, && case_sem_INSN_MCNVSWB },
+ { SH64_MEDIA_INSN_MCNVSWUB, && case_sem_INSN_MCNVSWUB },
+ { SH64_MEDIA_INSN_MEXTR1, && case_sem_INSN_MEXTR1 },
+ { SH64_MEDIA_INSN_MEXTR2, && case_sem_INSN_MEXTR2 },
+ { SH64_MEDIA_INSN_MEXTR3, && case_sem_INSN_MEXTR3 },
+ { SH64_MEDIA_INSN_MEXTR4, && case_sem_INSN_MEXTR4 },
+ { SH64_MEDIA_INSN_MEXTR5, && case_sem_INSN_MEXTR5 },
+ { SH64_MEDIA_INSN_MEXTR6, && case_sem_INSN_MEXTR6 },
+ { SH64_MEDIA_INSN_MEXTR7, && case_sem_INSN_MEXTR7 },
+ { SH64_MEDIA_INSN_MMACFXWL, && case_sem_INSN_MMACFXWL },
+ { SH64_MEDIA_INSN_MMACNFX_WL, && case_sem_INSN_MMACNFX_WL },
+ { SH64_MEDIA_INSN_MMULL, && case_sem_INSN_MMULL },
+ { SH64_MEDIA_INSN_MMULW, && case_sem_INSN_MMULW },
+ { SH64_MEDIA_INSN_MMULFXL, && case_sem_INSN_MMULFXL },
+ { SH64_MEDIA_INSN_MMULFXW, && case_sem_INSN_MMULFXW },
+ { SH64_MEDIA_INSN_MMULFXRPW, && case_sem_INSN_MMULFXRPW },
+ { SH64_MEDIA_INSN_MMULHIWL, && case_sem_INSN_MMULHIWL },
+ { SH64_MEDIA_INSN_MMULLOWL, && case_sem_INSN_MMULLOWL },
+ { SH64_MEDIA_INSN_MMULSUMWQ, && case_sem_INSN_MMULSUMWQ },
+ { SH64_MEDIA_INSN_MOVI, && case_sem_INSN_MOVI },
+ { SH64_MEDIA_INSN_MPERMW, && case_sem_INSN_MPERMW },
+ { SH64_MEDIA_INSN_MSADUBQ, && case_sem_INSN_MSADUBQ },
+ { SH64_MEDIA_INSN_MSHALDSL, && case_sem_INSN_MSHALDSL },
+ { SH64_MEDIA_INSN_MSHALDSW, && case_sem_INSN_MSHALDSW },
+ { SH64_MEDIA_INSN_MSHARDL, && case_sem_INSN_MSHARDL },
+ { SH64_MEDIA_INSN_MSHARDW, && case_sem_INSN_MSHARDW },
+ { SH64_MEDIA_INSN_MSHARDSQ, && case_sem_INSN_MSHARDSQ },
+ { SH64_MEDIA_INSN_MSHFHIB, && case_sem_INSN_MSHFHIB },
+ { SH64_MEDIA_INSN_MSHFHIL, && case_sem_INSN_MSHFHIL },
+ { SH64_MEDIA_INSN_MSHFHIW, && case_sem_INSN_MSHFHIW },
+ { SH64_MEDIA_INSN_MSHFLOB, && case_sem_INSN_MSHFLOB },
+ { SH64_MEDIA_INSN_MSHFLOL, && case_sem_INSN_MSHFLOL },
+ { SH64_MEDIA_INSN_MSHFLOW, && case_sem_INSN_MSHFLOW },
+ { SH64_MEDIA_INSN_MSHLLDL, && case_sem_INSN_MSHLLDL },
+ { SH64_MEDIA_INSN_MSHLLDW, && case_sem_INSN_MSHLLDW },
+ { SH64_MEDIA_INSN_MSHLRDL, && case_sem_INSN_MSHLRDL },
+ { SH64_MEDIA_INSN_MSHLRDW, && case_sem_INSN_MSHLRDW },
+ { SH64_MEDIA_INSN_MSUBL, && case_sem_INSN_MSUBL },
+ { SH64_MEDIA_INSN_MSUBW, && case_sem_INSN_MSUBW },
+ { SH64_MEDIA_INSN_MSUBSL, && case_sem_INSN_MSUBSL },
+ { SH64_MEDIA_INSN_MSUBSUB, && case_sem_INSN_MSUBSUB },
+ { SH64_MEDIA_INSN_MSUBSW, && case_sem_INSN_MSUBSW },
+ { SH64_MEDIA_INSN_MULSL, && case_sem_INSN_MULSL },
+ { SH64_MEDIA_INSN_MULUL, && case_sem_INSN_MULUL },
+ { SH64_MEDIA_INSN_NOP, && case_sem_INSN_NOP },
+ { SH64_MEDIA_INSN_NSB, && case_sem_INSN_NSB },
+ { SH64_MEDIA_INSN_OCBI, && case_sem_INSN_OCBI },
+ { SH64_MEDIA_INSN_OCBP, && case_sem_INSN_OCBP },
+ { SH64_MEDIA_INSN_OCBWB, && case_sem_INSN_OCBWB },
+ { SH64_MEDIA_INSN_OR, && case_sem_INSN_OR },
+ { SH64_MEDIA_INSN_ORI, && case_sem_INSN_ORI },
+ { SH64_MEDIA_INSN_PREFI, && case_sem_INSN_PREFI },
+ { SH64_MEDIA_INSN_PTA, && case_sem_INSN_PTA },
+ { SH64_MEDIA_INSN_PTABS, && case_sem_INSN_PTABS },
+ { SH64_MEDIA_INSN_PTB, && case_sem_INSN_PTB },
+ { SH64_MEDIA_INSN_PTREL, && case_sem_INSN_PTREL },
+ { SH64_MEDIA_INSN_PUTCFG, && case_sem_INSN_PUTCFG },
+ { SH64_MEDIA_INSN_PUTCON, && case_sem_INSN_PUTCON },
+ { SH64_MEDIA_INSN_RTE, && case_sem_INSN_RTE },
+ { SH64_MEDIA_INSN_SHARD, && case_sem_INSN_SHARD },
+ { SH64_MEDIA_INSN_SHARDL, && case_sem_INSN_SHARDL },
+ { SH64_MEDIA_INSN_SHARI, && case_sem_INSN_SHARI },
+ { SH64_MEDIA_INSN_SHARIL, && case_sem_INSN_SHARIL },
+ { SH64_MEDIA_INSN_SHLLD, && case_sem_INSN_SHLLD },
+ { SH64_MEDIA_INSN_SHLLDL, && case_sem_INSN_SHLLDL },
+ { SH64_MEDIA_INSN_SHLLI, && case_sem_INSN_SHLLI },
+ { SH64_MEDIA_INSN_SHLLIL, && case_sem_INSN_SHLLIL },
+ { SH64_MEDIA_INSN_SHLRD, && case_sem_INSN_SHLRD },
+ { SH64_MEDIA_INSN_SHLRDL, && case_sem_INSN_SHLRDL },
+ { SH64_MEDIA_INSN_SHLRI, && case_sem_INSN_SHLRI },
+ { SH64_MEDIA_INSN_SHLRIL, && case_sem_INSN_SHLRIL },
+ { SH64_MEDIA_INSN_SHORI, && case_sem_INSN_SHORI },
+ { SH64_MEDIA_INSN_SLEEP, && case_sem_INSN_SLEEP },
+ { SH64_MEDIA_INSN_STB, && case_sem_INSN_STB },
+ { SH64_MEDIA_INSN_STL, && case_sem_INSN_STL },
+ { SH64_MEDIA_INSN_STQ, && case_sem_INSN_STQ },
+ { SH64_MEDIA_INSN_STW, && case_sem_INSN_STW },
+ { SH64_MEDIA_INSN_STHIL, && case_sem_INSN_STHIL },
+ { SH64_MEDIA_INSN_STHIQ, && case_sem_INSN_STHIQ },
+ { SH64_MEDIA_INSN_STLOL, && case_sem_INSN_STLOL },
+ { SH64_MEDIA_INSN_STLOQ, && case_sem_INSN_STLOQ },
+ { SH64_MEDIA_INSN_STXB, && case_sem_INSN_STXB },
+ { SH64_MEDIA_INSN_STXL, && case_sem_INSN_STXL },
+ { SH64_MEDIA_INSN_STXQ, && case_sem_INSN_STXQ },
+ { SH64_MEDIA_INSN_STXW, && case_sem_INSN_STXW },
+ { SH64_MEDIA_INSN_SUB, && case_sem_INSN_SUB },
+ { SH64_MEDIA_INSN_SUBL, && case_sem_INSN_SUBL },
+ { SH64_MEDIA_INSN_SWAPQ, && case_sem_INSN_SWAPQ },
+ { SH64_MEDIA_INSN_SYNCI, && case_sem_INSN_SYNCI },
+ { SH64_MEDIA_INSN_SYNCO, && case_sem_INSN_SYNCO },
+ { SH64_MEDIA_INSN_TRAPA, && case_sem_INSN_TRAPA },
+ { SH64_MEDIA_INSN_XOR, && case_sem_INSN_XOR },
+ { SH64_MEDIA_INSN_XORI, && case_sem_INSN_XORI },
+ { 0, 0 }
+ };
+ int i;
+
+ for (i = 0; labels[i].label != 0; ++i)
+ {
+#if FAST_P
+ CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
+#else
+ CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
+#endif
+ }
+
+#undef DEFINE_LABELS
+#endif /* DEFINE_LABELS */
+
+#ifdef DEFINE_SWITCH
+
+/* If hyper-fast [well not unnecessarily slow] execution is selected, turn
+ off frills like tracing and profiling. */
+/* FIXME: A better way would be to have TRACE_RESULT check for something
+ that can cause it to be optimized out. Another way would be to emit
+ special handlers into the instruction "stream". */
+
+#if FAST_P
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#endif
+
+#undef GET_ATTR
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+#else
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
+#endif
+
+{
+
+#if WITH_SCACHE_PBB
+
+/* Branch to next handler without going around main loop. */
+#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
+SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
+
+#else /* ! WITH_SCACHE_PBB */
+
+#define NEXT(vpc) BREAK (sem)
+#ifdef __GNUC__
+#if FAST_P
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
+#endif
+#else
+ SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
+#endif
+
+#endif /* ! WITH_SCACHE_PBB */
+
+ {
+
+ CASE (sem, INSN_X_INVALID) : /* --invalid-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_AFTER) : /* --after-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_MEDIA
+ sh64_media_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEFORE) : /* --before-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_MEDIA
+ sh64_media_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_MEDIA
+#ifdef DEFINE_SWITCH
+ vpc = sh64_media_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = sh64_media_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_CHAIN) : /* --chain-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_MEDIA
+ vpc = sh64_media_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_X_BEGIN) : /* --begin-- */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_MEDIA
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = sh64_media_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = sh64_media_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = sh64_media_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADD) : /* add $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDL) : /* add.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDI) : /* addi $rm, $disp10, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDIL) : /* addi.l $rm, $disp10, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (ADDSI (EXTSISI (FLD (f_disp10)), SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ADDZL) : /* addz.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTSIDI (ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ALLOCO) : /* alloco $rm, $disp6x32 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_AND) : /* and $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ANDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ANDC) : /* andc $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ANDDI (GET_H_GR (FLD (f_left)), INVDI (GET_H_GR (FLD (f_right))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ANDI) : /* andi $rm, $disp10, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ANDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BEQ) : /* beq$likely $rm, $rn, $tra */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
+ {
+ UDI opval = CPU (h_tr[FLD (f_tra)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BEQI) : /* beqi$likely $rm, $imm6, $tra */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beqi.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
+ {
+ UDI opval = CPU (h_tr[FLD (f_tra)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BGE) : /* bge$likely $rm, $rn, $tra */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
+ {
+ UDI opval = CPU (h_tr[FLD (f_tra)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BGEU) : /* bgeu$likely $rm, $rn, $tra */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GEUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
+ {
+ UDI opval = CPU (h_tr[FLD (f_tra)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BGT) : /* bgt$likely $rm, $rn, $tra */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
+ {
+ UDI opval = CPU (h_tr[FLD (f_tra)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BGTU) : /* bgtu$likely $rm, $rn, $tra */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
+ {
+ UDI opval = CPU (h_tr[FLD (f_tra)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BLINK) : /* blink $trb, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_blink.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ DI opval = ORDI (ADDDI (pc, 4), 1);
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+ {
+ UDI opval = CPU (h_tr[FLD (f_trb)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BNE) : /* bne$likely $rm, $rn, $tra */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
+ {
+ UDI opval = CPU (h_tr[FLD (f_tra)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BNEI) : /* bnei$likely $rm, $imm6, $tra */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beqi.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NEDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
+ {
+ UDI opval = CPU (h_tr[FLD (f_tra)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BRK) : /* brk */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+sh64_break (current_cpu, pc);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_BYTEREV) : /* byterev $rm, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_xori.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ DI tmp_source;
+ DI tmp_result;
+ tmp_source = GET_H_GR (FLD (f_left));
+ tmp_result = 0;
+{
+ tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
+ tmp_source = SRLDI (tmp_source, 8);
+}
+{
+ tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
+ tmp_source = SRLDI (tmp_source, 8);
+}
+{
+ tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
+ tmp_source = SRLDI (tmp_source, 8);
+}
+{
+ tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
+ tmp_source = SRLDI (tmp_source, 8);
+}
+{
+ tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
+ tmp_source = SRLDI (tmp_source, 8);
+}
+{
+ tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
+ tmp_source = SRLDI (tmp_source, 8);
+}
+{
+ tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
+ tmp_source = SRLDI (tmp_source, 8);
+}
+{
+ tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
+ tmp_source = SRLDI (tmp_source, 8);
+}
+ {
+ DI opval = tmp_result;
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPEQ) : /* cmpeq $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ((EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) ? (1) : (0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPGT) : /* cmpgt $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ((GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) ? (1) : (0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMPGTU) : /* cmpgtu $rm,$rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ((GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) ? (1) : (0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMVEQ) : /* cmveq $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQDI (GET_H_GR (FLD (f_left)), 0)) {
+ {
+ DI opval = GET_H_GR (FLD (f_right));
+ SET_H_GR (FLD (f_dest), opval);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_CMVNE) : /* cmvne $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NEDI (GET_H_GR (FLD (f_left)), 0)) {
+ {
+ DI opval = GET_H_GR (FLD (f_right));
+ SET_H_GR (FLD (f_dest), opval);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FABSD) : /* fabs.d $drgh, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_fabsd (current_cpu, GET_H_DR (FLD (f_left_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FABSS) : /* fabs.s $frgh, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fabss (current_cpu, CPU (h_fr[FLD (f_left_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FADDD) : /* fadd.d $drg, $drh, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_faddd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FADDS) : /* fadd.s $frg, $frh, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fadds (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FCMPEQD) : /* fcmpeq.d $drg, $drh, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTBIDI (sh64_fcmpeqd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FCMPEQS) : /* fcmpeq.s $frg, $frh, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTBIDI (sh64_fcmpeqs (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FCMPGED) : /* fcmpge.d $drg, $drh, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTBIDI (sh64_fcmpged (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FCMPGES) : /* fcmpge.s $frg, $frh, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTBIDI (sh64_fcmpges (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FCMPGTD) : /* fcmpgt.d $drg, $drh, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTBIDI (sh64_fcmpgtd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FCMPGTS) : /* fcmpgt.s $frg, $frh, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTBIDI (sh64_fcmpgts (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FCMPUND) : /* fcmpun.d $drg, $drh, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTBIDI (sh64_fcmpund (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FCMPUNS) : /* fcmpun.s $frg, $frh, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTBIDI (sh64_fcmpuns (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FCNVDS) : /* fcnv.ds $drgh, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fcnvds (current_cpu, GET_H_DR (FLD (f_left_right)));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FCNVSD) : /* fcnv.sd $frgh, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_fcnvsd (current_cpu, CPU (h_fr[FLD (f_left_right)]));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FDIVD) : /* fdiv.d $drg, $drh, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_fdivd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FDIVS) : /* fdiv.s $frg, $frh, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fdivs (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FGETSCR) : /* fgetscr $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FIPRS) : /* fipr.s $fvg, $fvh, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ UQI tmp_g;
+ UQI tmp_h;
+ SF tmp_temp;
+ tmp_g = FLD (f_left);
+ tmp_h = FLD (f_right);
+ tmp_temp = sh64_fmuls (current_cpu, CPU (h_fr[tmp_g]), CPU (h_fr[tmp_h]));
+ tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 1)]), CPU (h_fr[ADDQI (tmp_h, 1)])));
+ tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 2)]), CPU (h_fr[ADDQI (tmp_h, 2)])));
+ tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 3)]), CPU (h_fr[ADDQI (tmp_h, 3)])));
+ {
+ SF opval = tmp_temp;
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLDD) : /* fld.d $rm, $disp10x8, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = GETMEMDF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLDP) : /* fld.p $rm, $disp10x8, $fpf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_f;
+ tmp_f = FLD (f_dest);
+ {
+ SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)));
+ CPU (h_fr[tmp_f]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fr-f", 'f', opval);
+ }
+ {
+ SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDSI (FLD (f_disp10x8), 4)));
+ CPU (h_fr[ADDQI (tmp_f, 1)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fr-add--DFLT-f-1", 'f', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLDS) : /* fld.s $rm, $disp10x4, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_flds.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x4)));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLDXD) : /* fldx.d $rm, $rn, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = GETMEMDF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLDXP) : /* fldx.p $rm, $rn, $fpf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_f;
+ tmp_f = FLD (f_dest);
+ {
+ SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
+ CPU (h_fr[tmp_f]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fr-f", 'f', opval);
+ }
+ {
+ SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDDI (GET_H_GR (FLD (f_right)), 4)));
+ CPU (h_fr[ADDQI (tmp_f, 1)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fr-add--DFLT-f-1", 'f', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLDXS) : /* fldx.s $rm, $rn, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLOATLD) : /* float.ld $frgh, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_floatld (current_cpu, CPU (h_fr[FLD (f_left_right)]));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLOATLS) : /* float.ls $frgh, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_floatls (current_cpu, CPU (h_fr[FLD (f_left_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLOATQD) : /* float.qd $drgh, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_floatqd (current_cpu, GET_H_DR (FLD (f_left_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FLOATQS) : /* float.qs $drgh, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_floatqs (current_cpu, GET_H_DR (FLD (f_left_right)));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMACS) : /* fmac.s $frg, $frh, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fadds (current_cpu, CPU (h_fr[FLD (f_dest)]), sh64_fmuls (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMOVD) : /* fmov.d $drgh, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = GET_H_DR (FLD (f_left_right));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMOVDQ) : /* fmov.dq $drgh, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = SUBWORDDFDI (GET_H_DR (FLD (f_left_right)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMOVLS) : /* fmov.ls $rm, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_xori.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = SUBWORDSISF (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMOVQD) : /* fmov.qd $rm, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_xori.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = SUBWORDDIDF (GET_H_GR (FLD (f_left)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMOVS) : /* fmov.s $frgh, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CPU (h_fr[FLD (f_left_right)]);
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMOVSL) : /* fmov.sl $frgh, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (SUBWORDSFSI (CPU (h_fr[FLD (f_left_right)])));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMULD) : /* fmul.d $drg, $drh, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_fmuld (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FMULS) : /* fmul.s $frg, $frh, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fmuls (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FNEGD) : /* fneg.d $drgh, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_fnegd (current_cpu, GET_H_DR (FLD (f_left_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FNEGS) : /* fneg.s $frgh, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fnegs (current_cpu, CPU (h_fr[FLD (f_left_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FPUTSCR) : /* fputscr $frgh */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FSQRTD) : /* fsqrt.d $drgh, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_fsqrtd (current_cpu, GET_H_DR (FLD (f_left_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FSQRTS) : /* fsqrt.s $frgh, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fsqrts (current_cpu, CPU (h_fr[FLD (f_left_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FSTD) : /* fst.d $rm, $disp10x8, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = GET_H_DR (FLD (f_dest));
+ SETMEMDF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FSTP) : /* fst.p $rm, $disp10x8, $fpf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_f;
+ tmp_f = FLD (f_dest);
+ {
+ SF opval = CPU (h_fr[tmp_f]);
+ SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+ {
+ SF opval = CPU (h_fr[ADDQI (tmp_f, 1)]);
+ SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDSI (FLD (f_disp10x8), 4)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FSTS) : /* fst.s $rm, $disp10x4, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_flds.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CPU (h_fr[FLD (f_dest)]);
+ SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x4)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FSTXD) : /* fstx.d $rm, $rn, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = GET_H_DR (FLD (f_dest));
+ SETMEMDF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FSTXP) : /* fstx.p $rm, $rn, $fpf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_f;
+ tmp_f = FLD (f_dest);
+ {
+ SF opval = CPU (h_fr[tmp_f]);
+ SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+ {
+ SF opval = CPU (h_fr[ADDQI (tmp_f, 1)]);
+ SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDDI (GET_H_GR (FLD (f_right)), 4)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FSTXS) : /* fstx.s $rm, $rn, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CPU (h_fr[FLD (f_dest)]);
+ SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FSUBD) : /* fsub.d $drg, $drh, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_fsubd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FSUBS) : /* fsub.s $frg, $frh, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fsubs (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FTRCDL) : /* ftrc.dl $drgh, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_ftrcdl (current_cpu, GET_H_DR (FLD (f_left_right)));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FTRCSL) : /* ftrc.sl $frgh, $frf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_ftrcsl (current_cpu, CPU (h_fr[FLD (f_left_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FTRCDQ) : /* ftrc.dq $drgh, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_ftrcdq (current_cpu, GET_H_DR (FLD (f_left_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FTRCSQ) : /* ftrc.sq $frgh, $drf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_ftrcsq (current_cpu, CPU (h_fr[FLD (f_left_right)]));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_FTRVS) : /* ftrv.s $mtrxg, $fvh, $fvf */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+sh64_ftrvs (current_cpu, FLD (f_left), FLD (f_right), FLD (f_dest));
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_GETCFG) : /* getcfg $rm, $disp6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_GETCON) : /* getcon $crk, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_xori.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = GET_H_CR (FLD (f_left));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_GETTR) : /* gettr $trb, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_blink.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = CPU (h_tr[FLD (f_trb)]);
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ICBI) : /* icbi $rm, $disp6x32 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDB) : /* ld.b $rm, $disp10, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTQIDI (GETMEMQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDL) : /* ld.l $rm, $disp10x4, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_flds.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (GETMEMSI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x4)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDQ) : /* ld.q $rm, $disp10x8, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = GETMEMDI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x8))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDUB) : /* ld.ub $rm, $disp10, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTQIDI (GETMEMQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDUW) : /* ld.uw $rm, $disp10x2, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lduw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTHIDI (GETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x2)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDW) : /* ld.w $rm, $disp10x2, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lduw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTHIDI (GETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x2)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDHIL) : /* ldhi.l $rm, $disp6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDHIQ) : /* ldhi.q $rm, $disp6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDLOL) : /* ldlo.l $rm, $disp6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDLOQ) : /* ldlo.q $rm, $disp6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDXB) : /* ldx.b $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTQIDI (GETMEMQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDXL) : /* ldx.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (GETMEMSI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDXQ) : /* ldx.q $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = GETMEMDI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDXUB) : /* ldx.ub $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTQIDI (GETMEMUQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDXUW) : /* ldx.uw $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTHIDI (GETMEMUHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_LDXW) : /* ldx.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTHIDI (GETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MABSL) : /* mabs.l $rm, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_xori.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = ABSSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1));
+ tmp_result1 = ABSSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MABSW) : /* mabs.w $rm, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_xori.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = ABSHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3));
+ tmp_result1 = ABSHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2));
+ tmp_result2 = ABSHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1));
+ tmp_result3 = ABSHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MADDL) : /* madd.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1));
+ tmp_result1 = ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MADDW) : /* madd.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3));
+ tmp_result1 = ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2));
+ tmp_result2 = ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1));
+ tmp_result3 = ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MADDSL) : /* madds.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = ((LTSI (ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)), SLLSI (1, SUBSI (32, 1)))) ? (ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_result1 = ((LTSI (ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)), SLLSI (1, SUBSI (32, 1)))) ? (ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MADDSUB) : /* madds.ub $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = ((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)), 0)) ? (0) : (((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)), SLLQI (1, 8))) ? (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result1 = ((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)), 0)) ? (0) : (((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)), SLLQI (1, 8))) ? (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result2 = ((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)), 0)) ? (0) : (((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)), SLLQI (1, 8))) ? (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result3 = ((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)), 0)) ? (0) : (((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)), SLLQI (1, 8))) ? (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result4 = ((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)), 0)) ? (0) : (((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)), SLLQI (1, 8))) ? (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result5 = ((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)), 0)) ? (0) : (((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)), SLLQI (1, 8))) ? (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result6 = ((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)), 0)) ? (0) : (((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)), SLLQI (1, 8))) ? (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result7 = ((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)), 0)) ? (0) : (((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)), SLLQI (1, 8))) ? (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))) : (SUBQI (SLLQI (1, 8), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MADDSW) : /* madds.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = ((LTHI (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTHI (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)), SLLHI (1, SUBSI (16, 1)))) ? (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result1 = ((LTHI (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTHI (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)), SLLHI (1, SUBSI (16, 1)))) ? (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result2 = ((LTHI (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTHI (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)), SLLHI (1, SUBSI (16, 1)))) ? (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result3 = ((LTHI (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTHI (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)), SLLHI (1, SUBSI (16, 1)))) ? (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MCMPEQB) : /* mcmpeq.b $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))) ? (INVQI (0)) : (0));
+ tmp_result1 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))) ? (INVQI (0)) : (0));
+ tmp_result2 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))) ? (INVQI (0)) : (0));
+ tmp_result3 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))) ? (INVQI (0)) : (0));
+ tmp_result4 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))) ? (INVQI (0)) : (0));
+ tmp_result5 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))) ? (INVQI (0)) : (0));
+ tmp_result6 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))) ? (INVQI (0)) : (0));
+ tmp_result7 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))) ? (INVQI (0)) : (0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MCMPEQL) : /* mcmpeq.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = ((EQSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))) ? (INVSI (0)) : (0));
+ tmp_result1 = ((EQSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))) ? (INVSI (0)) : (0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MCMPEQW) : /* mcmpeq.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = ((EQHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))) ? (INVHI (0)) : (0));
+ tmp_result1 = ((EQHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))) ? (INVHI (0)) : (0));
+ tmp_result2 = ((EQHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))) ? (INVHI (0)) : (0));
+ tmp_result3 = ((EQHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0))) ? (INVHI (0)) : (0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MCMPGTL) : /* mcmpgt.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = ((GTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))) ? (INVSI (0)) : (0));
+ tmp_result1 = ((GTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))) ? (INVSI (0)) : (0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MCMPGTUB) : /* mcmpgt.ub $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))) ? (INVQI (0)) : (0));
+ tmp_result1 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))) ? (INVQI (0)) : (0));
+ tmp_result2 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))) ? (INVQI (0)) : (0));
+ tmp_result3 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))) ? (INVQI (0)) : (0));
+ tmp_result4 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))) ? (INVQI (0)) : (0));
+ tmp_result5 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))) ? (INVQI (0)) : (0));
+ tmp_result6 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))) ? (INVQI (0)) : (0));
+ tmp_result7 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))) ? (INVQI (0)) : (0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MCMPGTW) : /* mcmpgt.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = ((GTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))) ? (INVHI (0)) : (0));
+ tmp_result1 = ((GTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))) ? (INVHI (0)) : (0));
+ tmp_result2 = ((GTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))) ? (INVHI (0)) : (0));
+ tmp_result3 = ((GTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0))) ? (INVHI (0)) : (0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MCMV) : /* mcmv $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ORDI (ANDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), ANDDI (GET_H_GR (FLD (f_dest)), INVDI (GET_H_GR (FLD (f_right)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MCNVSLW) : /* mcnvs.lw $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = ((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SLLHI (1, SUBSI (16, 1)))) ? (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result1 = ((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SLLHI (1, SUBSI (16, 1)))) ? (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result2 = ((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0), SLLHI (1, SUBSI (16, 1)))) ? (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result3 = ((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1), SLLHI (1, SUBSI (16, 1)))) ? (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MCNVSWB) : /* mcnvs.wb $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), NEGQI (SLLQI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SLLQI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
+ tmp_result1 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), NEGQI (SLLQI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SLLQI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
+ tmp_result2 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), NEGQI (SLLQI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SLLQI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
+ tmp_result3 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), NEGQI (SLLQI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SLLQI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
+ tmp_result4 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0), NEGQI (SLLQI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0), SLLQI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
+ tmp_result5 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1), NEGQI (SLLQI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1), SLLQI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
+ tmp_result6 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2), NEGQI (SLLQI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2), SLLQI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
+ tmp_result7 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3), NEGQI (SLLQI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3), SLLQI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MCNVSWUB) : /* mcnvs.wub $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), 0)) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SLLQI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result1 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), 0)) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SLLQI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result2 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), 0)) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SLLQI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result3 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), 0)) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SLLQI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result4 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0), 0)) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0), SLLQI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result5 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1), 0)) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1), SLLQI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result6 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2), 0)) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2), SLLQI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result7 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3), 0)) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3), SLLQI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)) : (SUBQI (SLLQI (1, 8), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MEXTR1) : /* mextr1 $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_count;
+ DI tmp_mask;
+ DI tmp_rhs;
+ tmp_count = MULQI (8, SUBQI (8, 1));
+ tmp_mask = SLLDI (INVSI (0), tmp_count);
+ tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
+ tmp_count = MULQI (8, 1);
+ tmp_mask = SRLDI (INVSI (0), tmp_count);
+ {
+ DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MEXTR2) : /* mextr2 $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_count;
+ DI tmp_mask;
+ DI tmp_rhs;
+ tmp_count = MULQI (8, SUBQI (8, 2));
+ tmp_mask = SLLDI (INVSI (0), tmp_count);
+ tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
+ tmp_count = MULQI (8, 2);
+ tmp_mask = SRLDI (INVSI (0), tmp_count);
+ {
+ DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MEXTR3) : /* mextr3 $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_count;
+ DI tmp_mask;
+ DI tmp_rhs;
+ tmp_count = MULQI (8, SUBQI (8, 3));
+ tmp_mask = SLLDI (INVSI (0), tmp_count);
+ tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
+ tmp_count = MULQI (8, 3);
+ tmp_mask = SRLDI (INVSI (0), tmp_count);
+ {
+ DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MEXTR4) : /* mextr4 $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_count;
+ DI tmp_mask;
+ DI tmp_rhs;
+ tmp_count = MULQI (8, SUBQI (8, 4));
+ tmp_mask = SLLDI (INVSI (0), tmp_count);
+ tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
+ tmp_count = MULQI (8, 4);
+ tmp_mask = SRLDI (INVSI (0), tmp_count);
+ {
+ DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MEXTR5) : /* mextr5 $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_count;
+ DI tmp_mask;
+ DI tmp_rhs;
+ tmp_count = MULQI (8, SUBQI (8, 5));
+ tmp_mask = SLLDI (INVSI (0), tmp_count);
+ tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
+ tmp_count = MULQI (8, 5);
+ tmp_mask = SRLDI (INVSI (0), tmp_count);
+ {
+ DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MEXTR6) : /* mextr6 $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_count;
+ DI tmp_mask;
+ DI tmp_rhs;
+ tmp_count = MULQI (8, SUBQI (8, 6));
+ tmp_mask = SLLDI (INVSI (0), tmp_count);
+ tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
+ tmp_count = MULQI (8, 6);
+ tmp_mask = SRLDI (INVSI (0), tmp_count);
+ {
+ DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MEXTR7) : /* mextr7 $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_count;
+ DI tmp_mask;
+ DI tmp_rhs;
+ tmp_count = MULQI (8, SUBQI (8, 7));
+ tmp_mask = SLLDI (INVSI (0), tmp_count);
+ tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
+ tmp_count = MULQI (8, 7);
+ tmp_mask = SRLDI (INVSI (0), tmp_count);
+ {
+ DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MMACFXWL) : /* mmacfx.wl $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_temp;
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 0);
+ tmp_result1 = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 1);
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
+ tmp_temp = ((LTSI (SLLSI (tmp_temp, 1), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SLLSI (tmp_temp, 1), SLLSI (1, SUBSI (32, 1)))) ? (SLLSI (tmp_temp, 1)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_result0 = ((LTSI (ADDSI (tmp_result0, tmp_temp), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (ADDSI (tmp_result0, tmp_temp), SLLSI (1, SUBSI (32, 1)))) ? (ADDSI (tmp_result0, tmp_temp)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)));
+ tmp_temp = ((LTSI (SLLSI (tmp_temp, 1), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SLLSI (tmp_temp, 1), SLLSI (1, SUBSI (32, 1)))) ? (SLLSI (tmp_temp, 1)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_result1 = ((LTSI (ADDSI (tmp_result1, tmp_temp), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (ADDSI (tmp_result1, tmp_temp), SLLSI (1, SUBSI (32, 1)))) ? (ADDSI (tmp_result1, tmp_temp)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MMACNFX_WL) : /* mmacnfx.wl $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_temp;
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 0);
+ tmp_result1 = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 1);
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
+ tmp_temp = ((LTSI (SLLSI (tmp_temp, 1), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SLLSI (tmp_temp, 1), SLLSI (1, SUBSI (32, 1)))) ? (SLLSI (tmp_temp, 1)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_result0 = ((LTSI (SUBSI (tmp_result0, tmp_temp), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SUBSI (tmp_result0, tmp_temp), SLLSI (1, SUBSI (32, 1)))) ? (SUBSI (tmp_result0, tmp_temp)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)));
+ tmp_temp = ((LTSI (SLLSI (tmp_temp, 1), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SLLSI (tmp_temp, 1), SLLSI (1, SUBSI (32, 1)))) ? (SLLSI (tmp_temp, 1)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_result1 = ((LTSI (SUBSI (tmp_result1, tmp_temp), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SUBSI (tmp_result1, tmp_temp), SLLSI (1, SUBSI (32, 1)))) ? (SUBSI (tmp_result1, tmp_temp)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MMULL) : /* mmul.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = MULSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1));
+ tmp_result1 = MULSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MMULW) : /* mmul.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = MULHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3));
+ tmp_result1 = MULHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2));
+ tmp_result2 = MULHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1));
+ tmp_result3 = MULHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MMULFXL) : /* mmulfx.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ DI tmp_temp;
+ SI tmp_result0;
+ SI tmp_result1;
+ tmp_temp = MULDI (ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)), ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)));
+ tmp_result0 = ((LTDI (SRADI (tmp_temp, 31), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SRADI (tmp_temp, 31), SLLSI (1, SUBSI (32, 1)))) ? (SRADI (tmp_temp, 31)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_temp = MULDI (ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
+ tmp_result1 = ((LTDI (SRADI (tmp_temp, 31), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SRADI (tmp_temp, 31), SLLSI (1, SUBSI (32, 1)))) ? (SRADI (tmp_temp, 31)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MMULFXW) : /* mmulfx.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_temp;
+ HI tmp_result0;
+ HI tmp_result1;
+ HI tmp_result2;
+ HI tmp_result3;
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
+ tmp_result0 = ((LTSI (SRASI (tmp_temp, 15), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (tmp_temp, 15), SLLHI (1, SUBSI (16, 1)))) ? (SRASI (tmp_temp, 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)));
+ tmp_result1 = ((LTSI (SRASI (tmp_temp, 15), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (tmp_temp, 15), SLLHI (1, SUBSI (16, 1)))) ? (SRASI (tmp_temp, 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)));
+ tmp_result2 = ((LTSI (SRASI (tmp_temp, 15), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (tmp_temp, 15), SLLHI (1, SUBSI (16, 1)))) ? (SRASI (tmp_temp, 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)));
+ tmp_result3 = ((LTSI (SRASI (tmp_temp, 15), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (tmp_temp, 15), SLLHI (1, SUBSI (16, 1)))) ? (SRASI (tmp_temp, 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MMULFXRPW) : /* mmulfxrp.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_temp;
+ HI tmp_result0;
+ HI tmp_result1;
+ HI tmp_result2;
+ HI tmp_result3;
+ HI tmp_c;
+ tmp_c = SLLSI (1, 14);
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
+ tmp_result0 = ((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), SLLHI (1, SUBSI (16, 1)))) ? (SRASI (ADDSI (tmp_temp, tmp_c), 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)));
+ tmp_result1 = ((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), SLLHI (1, SUBSI (16, 1)))) ? (SRASI (ADDSI (tmp_temp, tmp_c), 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)));
+ tmp_result2 = ((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), SLLHI (1, SUBSI (16, 1)))) ? (SRASI (ADDSI (tmp_temp, tmp_c), 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)));
+ tmp_result3 = ((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), SLLHI (1, SUBSI (16, 1)))) ? (SRASI (ADDSI (tmp_temp, tmp_c), 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MMULHIWL) : /* mmulhi.wl $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)));
+ tmp_result1 = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MMULLOWL) : /* mmullo.wl $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
+ tmp_result1 = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MMULSUMWQ) : /* mmulsum.wq $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ DI tmp_acc;
+ tmp_acc = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
+ tmp_acc = ADDDI (tmp_acc, MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))));
+ tmp_acc = ADDDI (tmp_acc, MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))));
+ tmp_acc = ADDDI (tmp_acc, MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))));
+ {
+ DI opval = ADDDI (GET_H_GR (FLD (f_dest)), tmp_acc);
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MOVI) : /* movi $imm16, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_movi.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (FLD (f_imm16));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MPERMW) : /* mperm.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_control;
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_control = ANDQI (GET_H_GR (FLD (f_right)), 63);
+ tmp_result0 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), SUBSI (3, ANDQI (tmp_control, 3)));
+ tmp_result1 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), SUBSI (3, ANDQI (SRLQI (tmp_control, 2), 3)));
+ tmp_result2 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), SUBSI (3, ANDQI (SRLQI (tmp_control, 4), 3)));
+ tmp_result3 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), SUBSI (3, ANDQI (SRLQI (tmp_control, 6), 3)));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSADUBQ) : /* msad.ubq $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ DI tmp_acc;
+ tmp_acc = ABSDI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)));
+ tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))));
+ tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))));
+ tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))));
+ tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))));
+ tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))));
+ tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))));
+ tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))));
+ {
+ DI opval = ADDDI (GET_H_GR (FLD (f_dest)), tmp_acc);
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSHALDSL) : /* mshalds.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = ((LTSI (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31)), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31)), SLLSI (1, SUBSI (32, 1)))) ? (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_result1 = ((LTSI (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31)), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31)), SLLSI (1, SUBSI (32, 1)))) ? (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSHALDSW) : /* mshalds.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = ((LTHI (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTHI (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15)), SLLHI (1, SUBSI (16, 1)))) ? (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result1 = ((LTHI (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTHI (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15)), SLLHI (1, SUBSI (16, 1)))) ? (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result2 = ((LTHI (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTHI (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15)), SLLHI (1, SUBSI (16, 1)))) ? (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result3 = ((LTHI (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTHI (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15)), SLLHI (1, SUBSI (16, 1)))) ? (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSHARDL) : /* mshard.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = SRASI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31));
+ tmp_result1 = SRASI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSHARDW) : /* mshard.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = SRAHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result1 = SRAHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result2 = SRAHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result3 = SRAHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSHARDSQ) : /* mshards.q $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ((LTDI (SRADI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63)), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGDI (SLLDI (1, SUBSI (16, 1)))) : (((LTDI (SRADI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63)), SLLDI (1, SUBSI (16, 1)))) ? (SRADI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63))) : (SUBDI (SLLDI (1, SUBSI (16, 1)), 1)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSHFHIB) : /* mshfhi.b $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4);
+ tmp_result1 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4);
+ tmp_result2 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5);
+ tmp_result3 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5);
+ tmp_result4 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6);
+ tmp_result5 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6);
+ tmp_result6 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7);
+ tmp_result7 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7);
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSHFHIL) : /* mshfhi.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = SUBWORDDISI (GET_H_GR (FLD (f_left)), 1);
+ tmp_result1 = SUBWORDDISI (GET_H_GR (FLD (f_right)), 1);
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSHFHIW) : /* mshfhi.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2);
+ tmp_result1 = SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2);
+ tmp_result2 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3);
+ tmp_result3 = SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3);
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSHFLOB) : /* mshflo.b $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0);
+ tmp_result1 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0);
+ tmp_result2 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1);
+ tmp_result3 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1);
+ tmp_result4 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2);
+ tmp_result5 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2);
+ tmp_result6 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3);
+ tmp_result7 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3);
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSHFLOL) : /* mshflo.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = SUBWORDDISI (GET_H_GR (FLD (f_left)), 0);
+ tmp_result1 = SUBWORDDISI (GET_H_GR (FLD (f_right)), 0);
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSHFLOW) : /* mshflo.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0);
+ tmp_result1 = SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0);
+ tmp_result2 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1);
+ tmp_result3 = SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1);
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSHLLDL) : /* mshlld.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31));
+ tmp_result1 = SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSHLLDW) : /* mshlld.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result1 = SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result2 = SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result3 = SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSHLRDL) : /* mshlrd.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = SRLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31));
+ tmp_result1 = SRLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSHLRDW) : /* mshlrd.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = SRLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result1 = SRLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result2 = SRLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result3 = SRLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSUBL) : /* msub.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1));
+ tmp_result1 = SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSUBW) : /* msub.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = SUBHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3));
+ tmp_result1 = SUBHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2));
+ tmp_result2 = SUBHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1));
+ tmp_result3 = SUBHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSUBSL) : /* msubs.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = ((LTSI (SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)), SLLSI (1, SUBSI (32, 1)))) ? (SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_result1 = ((LTSI (SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)), SLLSI (1, SUBSI (32, 1)))) ? (SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSUBSUB) : /* msubs.ub $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)), 0)) ? (0) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)), SLLQI (1, 8))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result1 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)), 0)) ? (0) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)), SLLQI (1, 8))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result2 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)), 0)) ? (0) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)), SLLQI (1, 8))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result3 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)), 0)) ? (0) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)), SLLQI (1, 8))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result4 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)), 0)) ? (0) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)), SLLQI (1, 8))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result5 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)), 0)) ? (0) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)), SLLQI (1, 8))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result6 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)), 0)) ? (0) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)), SLLQI (1, 8))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result7 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)), 0)) ? (0) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)), SLLQI (1, 8))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))) : (SUBQI (SLLQI (1, 8), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MSUBSW) : /* msubs.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)), SLLHI (1, SUBSI (16, 1)))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result1 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)), SLLHI (1, SUBSI (16, 1)))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result2 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)), SLLHI (1, SUBSI (16, 1)))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result3 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)), SLLHI (1, SUBSI (16, 1)))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result4 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)), SLLHI (1, SUBSI (16, 1)))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result5 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)), SLLHI (1, SUBSI (16, 1)))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result6 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)), SLLHI (1, SUBSI (16, 1)))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result7 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)), SLLHI (1, SUBSI (16, 1)))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULSL) : /* muls.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = MULDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_MULUL) : /* mulu.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = MULDI (ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NOP) : /* nop */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_NSB) : /* nsb $rm, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_xori.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = sh64_nsb (current_cpu, GET_H_GR (FLD (f_left)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OCBI) : /* ocbi $rm, $disp6x32 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OCBP) : /* ocbp $rm, $disp6x32 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OCBWB) : /* ocbwb $rm, $disp6x32 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_OR) : /* or $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ORDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_ORI) : /* ori $rm, $imm10, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_ori.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ORDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm10)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_PREFI) : /* prefi $rm, $disp6x32 */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_PTA) : /* pta$likely $disp16, $tra */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_pta.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ADDSI (FLD (f_disp16), 1);
+ CPU (h_tr[FLD (f_tra)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "tra", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_PTABS) : /* ptabs$likely $rn, $tra */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = GET_H_GR (FLD (f_right));
+ CPU (h_tr[FLD (f_tra)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "tra", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_PTB) : /* ptb$likely $disp16, $tra */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_pta.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = FLD (f_disp16);
+ CPU (h_tr[FLD (f_tra)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "tra", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_PTREL) : /* ptrel$likely $rn, $tra */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_beq.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ADDDI (pc, GET_H_GR (FLD (f_right)));
+ CPU (h_tr[FLD (f_tra)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "tra", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_PUTCFG) : /* putcfg $rm, $disp6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_PUTCON) : /* putcon $rm, $crj */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_xori.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = GET_H_GR (FLD (f_left));
+ SET_H_CR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "crj", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_RTE) : /* rte */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHARD) : /* shard $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = SRADI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHARDL) : /* shard.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (SRASI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 63)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHARI) : /* shari $rm, $uimm6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_shari.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = SRADI (GET_H_GR (FLD (f_left)), FLD (f_uimm6));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHARIL) : /* shari.l $rm, $uimm6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_shari.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (SRASI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDSI (FLD (f_uimm6), 63)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLLD) : /* shlld $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = SLLDI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLLDL) : /* shlld.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 63)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLLI) : /* shlli $rm, $uimm6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_shari.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = SLLDI (GET_H_GR (FLD (f_left)), FLD (f_uimm6));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLLIL) : /* shlli.l $rm, $uimm6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_shari.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDSI (FLD (f_uimm6), 63)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLRD) : /* shlrd $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = SRLDI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLRDL) : /* shlrd.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (SRLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 63)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLRI) : /* shlri $rm, $uimm6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_shari.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = SRLDI (GET_H_GR (FLD (f_left)), FLD (f_uimm6));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHLRIL) : /* shlri.l $rm, $uimm6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_shari.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (SRLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDSI (FLD (f_uimm6), 63)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SHORI) : /* shori $uimm16, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_shori.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ORDI (SLLDI (GET_H_GR (FLD (f_dest)), 16), ZEXTSIDI (FLD (f_uimm16)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SLEEP) : /* sleep */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STB) : /* st.b $rm, $disp10, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_addi.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ UQI opval = ANDQI (GET_H_GR (FLD (f_dest)), 255);
+ SETMEMUQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STL) : /* st.l $rm, $disp10x4, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_flds.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = ANDSI (GET_H_GR (FLD (f_dest)), 0xffffffff);
+ SETMEMSI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x4))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STQ) : /* st.q $rm, $disp10x8, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = GET_H_GR (FLD (f_dest));
+ SETMEMDI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x8))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STW) : /* st.w $rm, $disp10x2, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_lduw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ HI opval = ANDHI (GET_H_GR (FLD (f_dest)), 65535);
+ SETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STHIL) : /* sthi.l $rm, $disp6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_sthil.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ DI tmp_addr;
+ QI tmp_bytecount;
+ DI tmp_val;
+ tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
+ tmp_bytecount = ADDDI (ANDDI (tmp_addr, 3), 1);
+if (GET_H_ENDIAN ()) {
+ tmp_val = GET_H_GR (FLD (f_dest));
+} else {
+ tmp_val = SRLDI (GET_H_GR (FLD (f_dest)), SUBSI (32, MULSI (8, tmp_bytecount)));
+}
+ tmp_addr = ADDDI (SUBDI (tmp_addr, tmp_bytecount), 1);
+if (GTQI (tmp_bytecount, 3)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 2)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 1)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 0)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STHIQ) : /* sthi.q $rm, $disp6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_sthil.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ DI tmp_addr;
+ QI tmp_bytecount;
+ DI tmp_val;
+ tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
+ tmp_bytecount = ADDDI (ANDDI (tmp_addr, 7), 1);
+if (GET_H_ENDIAN ()) {
+ tmp_val = GET_H_GR (FLD (f_dest));
+} else {
+ tmp_val = SRLDI (GET_H_GR (FLD (f_dest)), SUBSI (64, MULSI (8, tmp_bytecount)));
+}
+ tmp_addr = ADDDI (SUBDI (tmp_addr, tmp_bytecount), 1);
+if (GTQI (tmp_bytecount, 7)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 6)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 5)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 4)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 3)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 2)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 1)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 0)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STLOL) : /* stlo.l $rm, $disp6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STLOQ) : /* stlo.q $rm, $disp6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STXB) : /* stx.b $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ UQI opval = SUBWORDDIQI (GET_H_GR (FLD (f_dest)), 7);
+ SETMEMUQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STXL) : /* stx.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 1);
+ SETMEMSI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STXQ) : /* stx.q $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = GET_H_GR (FLD (f_dest));
+ SETMEMDI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_STXW) : /* stx.w $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ HI opval = SUBWORDDIHI (GET_H_GR (FLD (f_dest)), 3);
+ SETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUB) : /* sub $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = SUBDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SUBL) : /* sub.l $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SWAPQ) : /* swap.q $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ DI tmp_addr;
+ DI tmp_temp;
+ tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
+ tmp_temp = GETMEMDI (current_cpu, pc, tmp_addr);
+ {
+ DI opval = GET_H_GR (FLD (f_dest));
+ SETMEMDI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
+ }
+ {
+ DI opval = tmp_temp;
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SYNCI) : /* synci */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_SYNCO) : /* synco */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.fmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_TRAPA) : /* trapa $rm */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_xori.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+sh64_trapa (current_cpu, GET_H_GR (FLD (f_left)), pc);
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XOR) : /* xor $rm, $rn, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_add.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = XORDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_XORI) : /* xori $rm, $imm6, $rd */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_xori.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = XORDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+#undef FLD
+}
+ NEXT (vpc);
+
+
+ }
+ ENDSWITCH (sem) /* End of semantic switch. */
+
+ /* At this point `vpc' contains the next insn to execute. */
+}
+
+#undef DEFINE_SWITCH
+#endif /* DEFINE_SWITCH */
--- /dev/null
+/* Simulator instruction semantics for sh64.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU sh64
+#define WANT_CPU_SH64
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+#undef GET_ATTR
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
+#else
+#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
+#endif
+
+/* This is used so that we can compile two copies of the semantic code,
+ one with full feature support and one without that runs fast(er).
+ FAST_P, when desired, is defined on the command line, -DFAST_P=1. */
+#if FAST_P
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
+#undef TRACE_RESULT
+#define TRACE_RESULT(cpu, abuf, name, type, val)
+#else
+#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
+#endif
+
+/* x-invalid: --invalid-- */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+ /* Update the recorded pc in the cpu state struct.
+ Only necessary for WITH_SCACHE case, but to avoid the
+ conditional compilation .... */
+ SET_H_PC (pc);
+ /* Virtual insns have zero size. Overwrite vpc with address of next insn
+ using the default-insn-bitsize spec. When executing insns in parallel
+ we may want to queue the fault and continue execution. */
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+ vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-after: --after-- */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_MEDIA
+ sh64_media_pbb_after (current_cpu, sem_arg);
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-before: --before-- */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_MEDIA
+ sh64_media_pbb_before (current_cpu, sem_arg);
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-cti-chain: --cti-chain-- */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_MEDIA
+#ifdef DEFINE_SWITCH
+ vpc = sh64_media_pbb_cti_chain (current_cpu, sem_arg,
+ pbb_br_type, pbb_br_npc);
+ BREAK (sem);
+#else
+ /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
+ vpc = sh64_media_pbb_cti_chain (current_cpu, sem_arg,
+ CPU_PBB_BR_TYPE (current_cpu),
+ CPU_PBB_BR_NPC (current_cpu));
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-chain: --chain-- */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_MEDIA
+ vpc = sh64_media_pbb_chain (current_cpu, sem_arg);
+#ifdef DEFINE_SWITCH
+ BREAK (sem);
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* x-begin: --begin-- */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
+
+ {
+#if WITH_SCACHE_PBB_SH64_MEDIA
+#if defined DEFINE_SWITCH || defined FAST_P
+ /* In the switch case FAST_P is a constant, allowing several optimizations
+ in any called inline functions. */
+ vpc = sh64_media_pbb_begin (current_cpu, FAST_P);
+#else
+#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
+ vpc = sh64_media_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
+#else
+ vpc = sh64_media_pbb_begin (current_cpu, 0);
+#endif
+#endif
+#endif
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* add: add $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* addl: add.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,addl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* addi: addi $rm, $disp10, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* addil: addi.l $rm, $disp10, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,addil) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (ADDSI (EXTSISI (FLD (f_disp10)), SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* addzl: addz.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,addzl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTSIDI (ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* alloco: alloco $rm, $disp6x32 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,alloco) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* and: and $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ANDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* andc: andc $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,andc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ANDDI (GET_H_GR (FLD (f_left)), INVDI (GET_H_GR (FLD (f_right))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* andi: andi $rm, $disp10, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,andi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ANDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* beq: beq$likely $rm, $rn, $tra */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
+ {
+ UDI opval = CPU (h_tr[FLD (f_tra)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* beqi: beqi$likely $rm, $imm6, $tra */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,beqi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beqi.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
+ {
+ UDI opval = CPU (h_tr[FLD (f_tra)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bge: bge$likely $rm, $rn, $tra */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,bge) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
+ {
+ UDI opval = CPU (h_tr[FLD (f_tra)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bgeu: bgeu$likely $rm, $rn, $tra */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,bgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GEUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
+ {
+ UDI opval = CPU (h_tr[FLD (f_tra)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bgt: bgt$likely $rm, $rn, $tra */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,bgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
+ {
+ UDI opval = CPU (h_tr[FLD (f_tra)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bgtu: bgtu$likely $rm, $rn, $tra */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,bgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
+ {
+ UDI opval = CPU (h_tr[FLD (f_tra)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* blink: blink $trb, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,blink) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_blink.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ DI opval = ORDI (ADDDI (pc, 4), 1);
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+ {
+ UDI opval = CPU (h_tr[FLD (f_trb)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bne: bne$likely $rm, $rn, $tra */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NEDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) {
+ {
+ UDI opval = CPU (h_tr[FLD (f_tra)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* bnei: bnei$likely $rm, $imm6, $tra */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,bnei) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beqi.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_BRANCH_INIT
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NEDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)))) {
+ {
+ UDI opval = CPU (h_tr[FLD (f_tra)]);
+ SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
+ written |= (1 << 3);
+ TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ SEM_BRANCH_FINI (vpc);
+ return vpc;
+#undef FLD
+}
+
+/* brk: brk */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,brk) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+sh64_break (current_cpu, pc);
+
+ return vpc;
+#undef FLD
+}
+
+/* byterev: byterev $rm, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,byterev) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_xori.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ DI tmp_source;
+ DI tmp_result;
+ tmp_source = GET_H_GR (FLD (f_left));
+ tmp_result = 0;
+{
+ tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
+ tmp_source = SRLDI (tmp_source, 8);
+}
+{
+ tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
+ tmp_source = SRLDI (tmp_source, 8);
+}
+{
+ tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
+ tmp_source = SRLDI (tmp_source, 8);
+}
+{
+ tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
+ tmp_source = SRLDI (tmp_source, 8);
+}
+{
+ tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
+ tmp_source = SRLDI (tmp_source, 8);
+}
+{
+ tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
+ tmp_source = SRLDI (tmp_source, 8);
+}
+{
+ tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
+ tmp_source = SRLDI (tmp_source, 8);
+}
+{
+ tmp_result = ORDI (SLLDI (tmp_result, 8), ANDDI (tmp_source, 255));
+ tmp_source = SRLDI (tmp_source, 8);
+}
+ {
+ DI opval = tmp_result;
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* cmpeq: cmpeq $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,cmpeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ((EQDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) ? (1) : (0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* cmpgt: cmpgt $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,cmpgt) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ((GTDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) ? (1) : (0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* cmpgtu: cmpgtu $rm,$rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,cmpgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ((GTUDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))) ? (1) : (0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* cmveq: cmveq $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,cmveq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (EQDI (GET_H_GR (FLD (f_left)), 0)) {
+ {
+ DI opval = GET_H_GR (FLD (f_right));
+ SET_H_GR (FLD (f_dest), opval);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* cmvne: cmvne $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,cmvne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (NEDI (GET_H_GR (FLD (f_left)), 0)) {
+ {
+ DI opval = GET_H_GR (FLD (f_right));
+ SET_H_GR (FLD (f_dest), opval);
+ written |= (1 << 2);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* fabsd: fabs.d $drgh, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fabsd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_fabsd (current_cpu, GET_H_DR (FLD (f_left_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fabss: fabs.s $frgh, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fabss) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fabss (current_cpu, CPU (h_fr[FLD (f_left_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* faddd: fadd.d $drg, $drh, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,faddd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_faddd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fadds: fadd.s $frg, $frh, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fadds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fadds (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fcmpeqd: fcmpeq.d $drg, $drh, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fcmpeqd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTBIDI (sh64_fcmpeqd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fcmpeqs: fcmpeq.s $frg, $frh, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fcmpeqs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTBIDI (sh64_fcmpeqs (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fcmpged: fcmpge.d $drg, $drh, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fcmpged) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTBIDI (sh64_fcmpged (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fcmpges: fcmpge.s $frg, $frh, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fcmpges) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTBIDI (sh64_fcmpges (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fcmpgtd: fcmpgt.d $drg, $drh, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fcmpgtd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTBIDI (sh64_fcmpgtd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fcmpgts: fcmpgt.s $frg, $frh, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fcmpgts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTBIDI (sh64_fcmpgts (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fcmpund: fcmpun.d $drg, $drh, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fcmpund) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTBIDI (sh64_fcmpund (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fcmpuns: fcmpun.s $frg, $frh, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fcmpuns) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTBIDI (sh64_fcmpuns (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fcnvds: fcnv.ds $drgh, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fcnvds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fcnvds (current_cpu, GET_H_DR (FLD (f_left_right)));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fcnvsd: fcnv.sd $frgh, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fcnvsd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_fcnvsd (current_cpu, CPU (h_fr[FLD (f_left_right)]));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fdivd: fdiv.d $drg, $drh, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fdivd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_fdivd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fdivs: fdiv.s $frg, $frh, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fdivs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fdivs (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fgetscr: fgetscr $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fgetscr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* fiprs: fipr.s $fvg, $fvh, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fiprs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ UQI tmp_g;
+ UQI tmp_h;
+ SF tmp_temp;
+ tmp_g = FLD (f_left);
+ tmp_h = FLD (f_right);
+ tmp_temp = sh64_fmuls (current_cpu, CPU (h_fr[tmp_g]), CPU (h_fr[tmp_h]));
+ tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 1)]), CPU (h_fr[ADDQI (tmp_h, 1)])));
+ tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 2)]), CPU (h_fr[ADDQI (tmp_h, 2)])));
+ tmp_temp = sh64_fadds (current_cpu, tmp_temp, sh64_fmuls (current_cpu, CPU (h_fr[ADDQI (tmp_g, 3)]), CPU (h_fr[ADDQI (tmp_h, 3)])));
+ {
+ SF opval = tmp_temp;
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* fldd: fld.d $rm, $disp10x8, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fldd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = GETMEMDF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fldp: fld.p $rm, $disp10x8, $fpf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fldp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_f;
+ tmp_f = FLD (f_dest);
+ {
+ SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)));
+ CPU (h_fr[tmp_f]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fr-f", 'f', opval);
+ }
+ {
+ SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDSI (FLD (f_disp10x8), 4)));
+ CPU (h_fr[ADDQI (tmp_f, 1)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fr-add--DFLT-f-1", 'f', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* flds: fld.s $rm, $disp10x4, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,flds) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_flds.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x4)));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fldxd: fldx.d $rm, $rn, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fldxd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = GETMEMDF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fldxp: fldx.p $rm, $rn, $fpf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fldxp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_f;
+ tmp_f = FLD (f_dest);
+ {
+ SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
+ CPU (h_fr[tmp_f]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fr-f", 'f', opval);
+ }
+ {
+ SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDDI (GET_H_GR (FLD (f_right)), 4)));
+ CPU (h_fr[ADDQI (tmp_f, 1)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "fr-add--DFLT-f-1", 'f', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* fldxs: fldx.s $rm, $rn, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fldxs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = GETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* floatld: float.ld $frgh, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,floatld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_floatld (current_cpu, CPU (h_fr[FLD (f_left_right)]));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* floatls: float.ls $frgh, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,floatls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_floatls (current_cpu, CPU (h_fr[FLD (f_left_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* floatqd: float.qd $drgh, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,floatqd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_floatqd (current_cpu, GET_H_DR (FLD (f_left_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* floatqs: float.qs $drgh, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,floatqs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_floatqs (current_cpu, GET_H_DR (FLD (f_left_right)));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fmacs: fmac.s $frg, $frh, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fmacs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fadds (current_cpu, CPU (h_fr[FLD (f_dest)]), sh64_fmuls (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)])));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fmovd: fmov.d $drgh, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fmovd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = GET_H_DR (FLD (f_left_right));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fmovdq: fmov.dq $drgh, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fmovdq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = SUBWORDDFDI (GET_H_DR (FLD (f_left_right)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fmovls: fmov.ls $rm, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fmovls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_xori.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = SUBWORDSISF (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fmovqd: fmov.qd $rm, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fmovqd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_xori.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = SUBWORDDIDF (GET_H_GR (FLD (f_left)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fmovs: fmov.s $frgh, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fmovs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CPU (h_fr[FLD (f_left_right)]);
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fmovsl: fmov.sl $frgh, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fmovsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (SUBWORDSFSI (CPU (h_fr[FLD (f_left_right)])));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fmuld: fmul.d $drg, $drh, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fmuld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_fmuld (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fmuls: fmul.s $frg, $frh, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fmuls) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fmuls (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fnegd: fneg.d $drgh, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fnegd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_fnegd (current_cpu, GET_H_DR (FLD (f_left_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fnegs: fneg.s $frgh, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fnegs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fnegs (current_cpu, CPU (h_fr[FLD (f_left_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fputscr: fputscr $frgh */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fputscr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* fsqrtd: fsqrt.d $drgh, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fsqrtd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_fsqrtd (current_cpu, GET_H_DR (FLD (f_left_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fsqrts: fsqrt.s $frgh, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fsqrts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fsqrts (current_cpu, CPU (h_fr[FLD (f_left_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fstd: fst.d $rm, $disp10x8, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fstd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = GET_H_DR (FLD (f_dest));
+ SETMEMDF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fstp: fst.p $rm, $disp10x8, $fpf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fstp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_f;
+ tmp_f = FLD (f_dest);
+ {
+ SF opval = CPU (h_fr[tmp_f]);
+ SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x8)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+ {
+ SF opval = CPU (h_fr[ADDQI (tmp_f, 1)]);
+ SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDSI (FLD (f_disp10x8), 4)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* fsts: fst.s $rm, $disp10x4, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fsts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_flds.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CPU (h_fr[FLD (f_dest)]);
+ SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp10x4)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fstxd: fstx.d $rm, $rn, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fstxd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = GET_H_DR (FLD (f_dest));
+ SETMEMDF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fstxp: fstx.p $rm, $rn, $fpf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fstxp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_f;
+ tmp_f = FLD (f_dest);
+ {
+ SF opval = CPU (h_fr[tmp_f]);
+ SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+ {
+ SF opval = CPU (h_fr[ADDQI (tmp_f, 1)]);
+ SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), ADDDI (GET_H_GR (FLD (f_right)), 4)), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* fstxs: fstx.s $rm, $rn, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fstxs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = CPU (h_fr[FLD (f_dest)]);
+ SETMEMSF (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fsubd: fsub.d $drg, $drh, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fsubd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_fsubd (current_cpu, GET_H_DR (FLD (f_left)), GET_H_DR (FLD (f_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* fsubs: fsub.s $frg, $frh, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,fsubs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_fsubs (current_cpu, CPU (h_fr[FLD (f_left)]), CPU (h_fr[FLD (f_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ftrcdl: ftrc.dl $drgh, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ftrcdl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_ftrcdl (current_cpu, GET_H_DR (FLD (f_left_right)));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ftrcsl: ftrc.sl $frgh, $frf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ftrcsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SF opval = sh64_ftrcsl (current_cpu, CPU (h_fr[FLD (f_left_right)]));
+ CPU (h_fr[FLD (f_dest)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "frf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ftrcdq: ftrc.dq $drgh, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ftrcdq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_ftrcdq (current_cpu, GET_H_DR (FLD (f_left_right)));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ftrcsq: ftrc.sq $frgh, $drf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ftrcsq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fabsd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DF opval = sh64_ftrcsq (current_cpu, CPU (h_fr[FLD (f_left_right)]));
+ SET_H_DR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "drf", 'f', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ftrvs: ftrv.s $mtrxg, $fvh, $fvf */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ftrvs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+sh64_ftrvs (current_cpu, FLD (f_left), FLD (f_right), FLD (f_dest));
+
+ return vpc;
+#undef FLD
+}
+
+/* getcfg: getcfg $rm, $disp6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,getcfg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* getcon: getcon $crk, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,getcon) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_xori.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = GET_H_CR (FLD (f_left));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* gettr: gettr $trb, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,gettr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_blink.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = CPU (h_tr[FLD (f_trb)]);
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* icbi: icbi $rm, $disp6x32 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,icbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* ldb: ld.b $rm, $disp10, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTQIDI (GETMEMQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldl: ld.l $rm, $disp10x4, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ldl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_flds.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (GETMEMSI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x4)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldq: ld.q $rm, $disp10x8, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ldq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = GETMEMDI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x8))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldub: ld.ub $rm, $disp10, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTQIDI (GETMEMQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* lduw: ld.uw $rm, $disp10x2, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,lduw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lduw.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTHIDI (GETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x2)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldw: ld.w $rm, $disp10x2, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ldw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lduw.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTHIDI (GETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x2)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldhil: ldhi.l $rm, $disp6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ldhil) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* ldhiq: ldhi.q $rm, $disp6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ldhiq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* ldlol: ldlo.l $rm, $disp6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ldlol) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* ldloq: ldlo.q $rm, $disp6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ldloq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* ldxb: ldx.b $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ldxb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTQIDI (GETMEMQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldxl: ldx.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ldxl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (GETMEMSI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldxq: ldx.q $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ldxq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = GETMEMDI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldxub: ldx.ub $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ldxub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTQIDI (GETMEMUQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldxuw: ldx.uw $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ldxuw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ZEXTHIDI (GETMEMUHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ldxw: ldx.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ldxw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTHIDI (GETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mabsl: mabs.l $rm, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mabsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_xori.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = ABSSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1));
+ tmp_result1 = ABSSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mabsw: mabs.w $rm, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mabsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_xori.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = ABSHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3));
+ tmp_result1 = ABSHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2));
+ tmp_result2 = ABSHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1));
+ tmp_result3 = ABSHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* maddl: madd.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,maddl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1));
+ tmp_result1 = ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* maddw: madd.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,maddw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3));
+ tmp_result1 = ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2));
+ tmp_result2 = ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1));
+ tmp_result3 = ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* maddsl: madds.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,maddsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = ((LTSI (ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)), SLLSI (1, SUBSI (32, 1)))) ? (ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_result1 = ((LTSI (ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)), SLLSI (1, SUBSI (32, 1)))) ? (ADDSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* maddsub: madds.ub $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,maddsub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = ((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)), 0)) ? (0) : (((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)), SLLQI (1, 8))) ? (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result1 = ((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)), 0)) ? (0) : (((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)), SLLQI (1, 8))) ? (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result2 = ((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)), 0)) ? (0) : (((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)), SLLQI (1, 8))) ? (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result3 = ((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)), 0)) ? (0) : (((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)), SLLQI (1, 8))) ? (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result4 = ((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)), 0)) ? (0) : (((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)), SLLQI (1, 8))) ? (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result5 = ((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)), 0)) ? (0) : (((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)), SLLQI (1, 8))) ? (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result6 = ((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)), 0)) ? (0) : (((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)), SLLQI (1, 8))) ? (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result7 = ((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)), 0)) ? (0) : (((LTQI (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)), SLLQI (1, 8))) ? (ADDQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))) : (SUBQI (SLLQI (1, 8), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* maddsw: madds.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,maddsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = ((LTHI (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTHI (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)), SLLHI (1, SUBSI (16, 1)))) ? (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result1 = ((LTHI (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTHI (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)), SLLHI (1, SUBSI (16, 1)))) ? (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result2 = ((LTHI (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTHI (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)), SLLHI (1, SUBSI (16, 1)))) ? (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result3 = ((LTHI (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTHI (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)), SLLHI (1, SUBSI (16, 1)))) ? (ADDHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mcmpeqb: mcmpeq.b $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mcmpeqb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))) ? (INVQI (0)) : (0));
+ tmp_result1 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))) ? (INVQI (0)) : (0));
+ tmp_result2 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))) ? (INVQI (0)) : (0));
+ tmp_result3 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))) ? (INVQI (0)) : (0));
+ tmp_result4 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))) ? (INVQI (0)) : (0));
+ tmp_result5 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))) ? (INVQI (0)) : (0));
+ tmp_result6 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))) ? (INVQI (0)) : (0));
+ tmp_result7 = ((EQQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))) ? (INVQI (0)) : (0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mcmpeql: mcmpeq.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mcmpeql) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = ((EQSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))) ? (INVSI (0)) : (0));
+ tmp_result1 = ((EQSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))) ? (INVSI (0)) : (0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mcmpeqw: mcmpeq.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mcmpeqw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = ((EQHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))) ? (INVHI (0)) : (0));
+ tmp_result1 = ((EQHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))) ? (INVHI (0)) : (0));
+ tmp_result2 = ((EQHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))) ? (INVHI (0)) : (0));
+ tmp_result3 = ((EQHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0))) ? (INVHI (0)) : (0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mcmpgtl: mcmpgt.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mcmpgtl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = ((GTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))) ? (INVSI (0)) : (0));
+ tmp_result1 = ((GTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))) ? (INVSI (0)) : (0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mcmpgtub: mcmpgt.ub $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mcmpgtub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))) ? (INVQI (0)) : (0));
+ tmp_result1 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))) ? (INVQI (0)) : (0));
+ tmp_result2 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))) ? (INVQI (0)) : (0));
+ tmp_result3 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))) ? (INVQI (0)) : (0));
+ tmp_result4 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))) ? (INVQI (0)) : (0));
+ tmp_result5 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))) ? (INVQI (0)) : (0));
+ tmp_result6 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))) ? (INVQI (0)) : (0));
+ tmp_result7 = ((GTUQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))) ? (INVQI (0)) : (0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mcmpgtw: mcmpgt.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mcmpgtw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = ((GTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))) ? (INVHI (0)) : (0));
+ tmp_result1 = ((GTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))) ? (INVHI (0)) : (0));
+ tmp_result2 = ((GTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))) ? (INVHI (0)) : (0));
+ tmp_result3 = ((GTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0))) ? (INVHI (0)) : (0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mcmv: mcmv $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mcmv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ORDI (ANDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), ANDDI (GET_H_GR (FLD (f_dest)), INVDI (GET_H_GR (FLD (f_right)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mcnvslw: mcnvs.lw $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mcnvslw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = ((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SLLHI (1, SUBSI (16, 1)))) ? (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result1 = ((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SLLHI (1, SUBSI (16, 1)))) ? (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result2 = ((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0), SLLHI (1, SUBSI (16, 1)))) ? (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result3 = ((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1), SLLHI (1, SUBSI (16, 1)))) ? (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mcnvswb: mcnvs.wb $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mcnvswb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), NEGQI (SLLQI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SLLQI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
+ tmp_result1 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), NEGQI (SLLQI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SLLQI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
+ tmp_result2 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), NEGQI (SLLQI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SLLQI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
+ tmp_result3 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), NEGQI (SLLQI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SLLQI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
+ tmp_result4 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0), NEGQI (SLLQI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0), SLLQI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
+ tmp_result5 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1), NEGQI (SLLQI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1), SLLQI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
+ tmp_result6 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2), NEGQI (SLLQI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2), SLLQI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
+ tmp_result7 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3), NEGQI (SLLQI (1, SUBSI (8, 1))))) ? (NEGQI (SLLQI (1, SUBSI (8, 1)))) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3), SLLQI (1, SUBSI (8, 1)))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)) : (SUBQI (SLLQI (1, SUBSI (8, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mcnvswub: mcnvs.wub $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mcnvswub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), 0)) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SLLQI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result1 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), 0)) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SLLQI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result2 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), 0)) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SLLQI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result3 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), 0)) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SLLQI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result4 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0), 0)) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0), SLLQI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result5 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1), 0)) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1), SLLQI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result6 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2), 0)) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2), SLLQI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result7 = ((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3), 0)) ? (0) : (((LTHI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3), SLLQI (1, 8))) ? (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)) : (SUBQI (SLLQI (1, 8), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mextr1: mextr1 $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mextr1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_count;
+ DI tmp_mask;
+ DI tmp_rhs;
+ tmp_count = MULQI (8, SUBQI (8, 1));
+ tmp_mask = SLLDI (INVSI (0), tmp_count);
+ tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
+ tmp_count = MULQI (8, 1);
+ tmp_mask = SRLDI (INVSI (0), tmp_count);
+ {
+ DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mextr2: mextr2 $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mextr2) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_count;
+ DI tmp_mask;
+ DI tmp_rhs;
+ tmp_count = MULQI (8, SUBQI (8, 2));
+ tmp_mask = SLLDI (INVSI (0), tmp_count);
+ tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
+ tmp_count = MULQI (8, 2);
+ tmp_mask = SRLDI (INVSI (0), tmp_count);
+ {
+ DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mextr3: mextr3 $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mextr3) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_count;
+ DI tmp_mask;
+ DI tmp_rhs;
+ tmp_count = MULQI (8, SUBQI (8, 3));
+ tmp_mask = SLLDI (INVSI (0), tmp_count);
+ tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
+ tmp_count = MULQI (8, 3);
+ tmp_mask = SRLDI (INVSI (0), tmp_count);
+ {
+ DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mextr4: mextr4 $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mextr4) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_count;
+ DI tmp_mask;
+ DI tmp_rhs;
+ tmp_count = MULQI (8, SUBQI (8, 4));
+ tmp_mask = SLLDI (INVSI (0), tmp_count);
+ tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
+ tmp_count = MULQI (8, 4);
+ tmp_mask = SRLDI (INVSI (0), tmp_count);
+ {
+ DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mextr5: mextr5 $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mextr5) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_count;
+ DI tmp_mask;
+ DI tmp_rhs;
+ tmp_count = MULQI (8, SUBQI (8, 5));
+ tmp_mask = SLLDI (INVSI (0), tmp_count);
+ tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
+ tmp_count = MULQI (8, 5);
+ tmp_mask = SRLDI (INVSI (0), tmp_count);
+ {
+ DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mextr6: mextr6 $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mextr6) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_count;
+ DI tmp_mask;
+ DI tmp_rhs;
+ tmp_count = MULQI (8, SUBQI (8, 6));
+ tmp_mask = SLLDI (INVSI (0), tmp_count);
+ tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
+ tmp_count = MULQI (8, 6);
+ tmp_mask = SRLDI (INVSI (0), tmp_count);
+ {
+ DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mextr7: mextr7 $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mextr7) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_count;
+ DI tmp_mask;
+ DI tmp_rhs;
+ tmp_count = MULQI (8, SUBQI (8, 7));
+ tmp_mask = SLLDI (INVSI (0), tmp_count);
+ tmp_rhs = SRLDI (ANDDI (GET_H_GR (FLD (f_left)), tmp_mask), tmp_count);
+ tmp_count = MULQI (8, 7);
+ tmp_mask = SRLDI (INVSI (0), tmp_count);
+ {
+ DI opval = ORDI (tmp_rhs, SLLDI (ANDDI (GET_H_GR (FLD (f_right)), tmp_mask), tmp_count));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mmacfxwl: mmacfx.wl $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mmacfxwl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_temp;
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 0);
+ tmp_result1 = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 1);
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
+ tmp_temp = ((LTSI (SLLSI (tmp_temp, 1), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SLLSI (tmp_temp, 1), SLLSI (1, SUBSI (32, 1)))) ? (SLLSI (tmp_temp, 1)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_result0 = ((LTSI (ADDSI (tmp_result0, tmp_temp), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (ADDSI (tmp_result0, tmp_temp), SLLSI (1, SUBSI (32, 1)))) ? (ADDSI (tmp_result0, tmp_temp)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)));
+ tmp_temp = ((LTSI (SLLSI (tmp_temp, 1), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SLLSI (tmp_temp, 1), SLLSI (1, SUBSI (32, 1)))) ? (SLLSI (tmp_temp, 1)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_result1 = ((LTSI (ADDSI (tmp_result1, tmp_temp), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (ADDSI (tmp_result1, tmp_temp), SLLSI (1, SUBSI (32, 1)))) ? (ADDSI (tmp_result1, tmp_temp)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mmacnfx.wl: mmacnfx.wl $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mmacnfx_wl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_temp;
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 0);
+ tmp_result1 = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 1);
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
+ tmp_temp = ((LTSI (SLLSI (tmp_temp, 1), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SLLSI (tmp_temp, 1), SLLSI (1, SUBSI (32, 1)))) ? (SLLSI (tmp_temp, 1)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_result0 = ((LTSI (SUBSI (tmp_result0, tmp_temp), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SUBSI (tmp_result0, tmp_temp), SLLSI (1, SUBSI (32, 1)))) ? (SUBSI (tmp_result0, tmp_temp)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)));
+ tmp_temp = ((LTSI (SLLSI (tmp_temp, 1), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SLLSI (tmp_temp, 1), SLLSI (1, SUBSI (32, 1)))) ? (SLLSI (tmp_temp, 1)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_result1 = ((LTSI (SUBSI (tmp_result1, tmp_temp), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SUBSI (tmp_result1, tmp_temp), SLLSI (1, SUBSI (32, 1)))) ? (SUBSI (tmp_result1, tmp_temp)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mmull: mmul.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mmull) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = MULSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1));
+ tmp_result1 = MULSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mmulw: mmul.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mmulw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = MULHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3));
+ tmp_result1 = MULHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2));
+ tmp_result2 = MULHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1));
+ tmp_result3 = MULHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mmulfxl: mmulfx.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mmulfxl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ DI tmp_temp;
+ SI tmp_result0;
+ SI tmp_result1;
+ tmp_temp = MULDI (ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0)), ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)));
+ tmp_result0 = ((LTDI (SRADI (tmp_temp, 31), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SRADI (tmp_temp, 31), SLLSI (1, SUBSI (32, 1)))) ? (SRADI (tmp_temp, 31)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_temp = MULDI (ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
+ tmp_result1 = ((LTDI (SRADI (tmp_temp, 31), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTDI (SRADI (tmp_temp, 31), SLLSI (1, SUBSI (32, 1)))) ? (SRADI (tmp_temp, 31)) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mmulfxw: mmulfx.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mmulfxw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_temp;
+ HI tmp_result0;
+ HI tmp_result1;
+ HI tmp_result2;
+ HI tmp_result3;
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
+ tmp_result0 = ((LTSI (SRASI (tmp_temp, 15), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (tmp_temp, 15), SLLHI (1, SUBSI (16, 1)))) ? (SRASI (tmp_temp, 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)));
+ tmp_result1 = ((LTSI (SRASI (tmp_temp, 15), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (tmp_temp, 15), SLLHI (1, SUBSI (16, 1)))) ? (SRASI (tmp_temp, 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)));
+ tmp_result2 = ((LTSI (SRASI (tmp_temp, 15), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (tmp_temp, 15), SLLHI (1, SUBSI (16, 1)))) ? (SRASI (tmp_temp, 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)));
+ tmp_result3 = ((LTSI (SRASI (tmp_temp, 15), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (tmp_temp, 15), SLLHI (1, SUBSI (16, 1)))) ? (SRASI (tmp_temp, 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mmulfxrpw: mmulfxrp.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mmulfxrpw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_temp;
+ HI tmp_result0;
+ HI tmp_result1;
+ HI tmp_result2;
+ HI tmp_result3;
+ HI tmp_c;
+ tmp_c = SLLSI (1, 14);
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
+ tmp_result0 = ((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), SLLHI (1, SUBSI (16, 1)))) ? (SRASI (ADDSI (tmp_temp, tmp_c), 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)));
+ tmp_result1 = ((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), SLLHI (1, SUBSI (16, 1)))) ? (SRASI (ADDSI (tmp_temp, tmp_c), 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)));
+ tmp_result2 = ((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), SLLHI (1, SUBSI (16, 1)))) ? (SRASI (ADDSI (tmp_temp, tmp_c), 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_temp = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)));
+ tmp_result3 = ((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTSI (SRASI (ADDSI (tmp_temp, tmp_c), 15), SLLHI (1, SUBSI (16, 1)))) ? (SRASI (ADDSI (tmp_temp, tmp_c), 15)) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mmulhiwl: mmulhi.wl $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mmulhiwl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2)));
+ tmp_result1 = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3)));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mmullowl: mmullo.wl $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mmullowl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
+ tmp_result1 = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1)));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mmulsumwq: mmulsum.wq $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mmulsumwq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ DI tmp_acc;
+ tmp_acc = MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0)));
+ tmp_acc = ADDDI (tmp_acc, MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1))));
+ tmp_acc = ADDDI (tmp_acc, MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2))));
+ tmp_acc = ADDDI (tmp_acc, MULSI (ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3)), ZEXTHISI (SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3))));
+ {
+ DI opval = ADDDI (GET_H_GR (FLD (f_dest)), tmp_acc);
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* movi: movi $imm16, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,movi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movi.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (FLD (f_imm16));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mpermw: mperm.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mpermw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_control;
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_control = ANDQI (GET_H_GR (FLD (f_right)), 63);
+ tmp_result0 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), SUBSI (3, ANDQI (tmp_control, 3)));
+ tmp_result1 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), SUBSI (3, ANDQI (SRLQI (tmp_control, 2), 3)));
+ tmp_result2 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), SUBSI (3, ANDQI (SRLQI (tmp_control, 4), 3)));
+ tmp_result3 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), SUBSI (3, ANDQI (SRLQI (tmp_control, 6), 3)));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* msadubq: msad.ubq $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,msadubq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ DI tmp_acc;
+ tmp_acc = ABSDI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)));
+ tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))));
+ tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))));
+ tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))));
+ tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))));
+ tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))));
+ tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))));
+ tmp_acc = ADDDI (tmp_acc, ABSQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))));
+ {
+ DI opval = ADDDI (GET_H_GR (FLD (f_dest)), tmp_acc);
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mshaldsl: mshalds.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mshaldsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = ((LTSI (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31)), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31)), SLLSI (1, SUBSI (32, 1)))) ? (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_result1 = ((LTSI (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31)), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31)), SLLSI (1, SUBSI (32, 1)))) ? (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mshaldsw: mshalds.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mshaldsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = ((LTHI (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTHI (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15)), SLLHI (1, SUBSI (16, 1)))) ? (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result1 = ((LTHI (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTHI (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15)), SLLHI (1, SUBSI (16, 1)))) ? (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result2 = ((LTHI (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTHI (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15)), SLLHI (1, SUBSI (16, 1)))) ? (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result3 = ((LTHI (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTHI (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15)), SLLHI (1, SUBSI (16, 1)))) ? (SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mshardl: mshard.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mshardl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = SRASI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31));
+ tmp_result1 = SRASI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mshardw: mshard.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mshardw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = SRAHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result1 = SRAHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result2 = SRAHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result3 = SRAHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mshardsq: mshards.q $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mshardsq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ((LTDI (SRADI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63)), NEGDI (SLLDI (1, SUBSI (16, 1))))) ? (NEGDI (SLLDI (1, SUBSI (16, 1)))) : (((LTDI (SRADI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63)), SLLDI (1, SUBSI (16, 1)))) ? (SRADI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63))) : (SUBDI (SLLDI (1, SUBSI (16, 1)), 1)))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mshfhib: mshfhi.b $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mshfhib) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4);
+ tmp_result1 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4);
+ tmp_result2 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5);
+ tmp_result3 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5);
+ tmp_result4 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6);
+ tmp_result5 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6);
+ tmp_result6 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7);
+ tmp_result7 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7);
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mshfhil: mshfhi.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mshfhil) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = SUBWORDDISI (GET_H_GR (FLD (f_left)), 1);
+ tmp_result1 = SUBWORDDISI (GET_H_GR (FLD (f_right)), 1);
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mshfhiw: mshfhi.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mshfhiw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2);
+ tmp_result1 = SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2);
+ tmp_result2 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3);
+ tmp_result3 = SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3);
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mshflob: mshflo.b $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mshflob) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0);
+ tmp_result1 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0);
+ tmp_result2 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1);
+ tmp_result3 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1);
+ tmp_result4 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2);
+ tmp_result5 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2);
+ tmp_result6 = SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3);
+ tmp_result7 = SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3);
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mshflol: mshflo.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mshflol) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = SUBWORDDISI (GET_H_GR (FLD (f_left)), 0);
+ tmp_result1 = SUBWORDDISI (GET_H_GR (FLD (f_right)), 0);
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mshflow: mshflo.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mshflow) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0);
+ tmp_result1 = SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0);
+ tmp_result2 = SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1);
+ tmp_result3 = SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1);
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mshlldl: mshlld.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mshlldl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31));
+ tmp_result1 = SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mshlldw: mshlld.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mshlldw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result1 = SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result2 = SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result3 = SLLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mshlrdl: mshlrd.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mshlrdl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = SRLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 31));
+ tmp_result1 = SRLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 31));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mshlrdw: mshlrd.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mshlrdw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = SRLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result1 = SRLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result2 = SRLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ tmp_result3 = SRLHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), ANDDI (GET_H_GR (FLD (f_right)), 15));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* msubl: msub.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,msubl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1));
+ tmp_result1 = SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* msubw: msub.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,msubw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ HI tmp_result3;
+ HI tmp_result2;
+ HI tmp_result1;
+ HI tmp_result0;
+ tmp_result0 = SUBHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 3));
+ tmp_result1 = SUBHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 2));
+ tmp_result2 = SUBHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 1));
+ tmp_result3 = SUBHI (SUBWORDDIHI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIHI (GET_H_GR (FLD (f_right)), 0));
+ {
+ DI opval = ORDI (SLLDI (ZEXTHIDI (tmp_result3), 48), ORDI (SLLDI (ZEXTHIDI (tmp_result2), 32), ORDI (SLLDI (ZEXTHIDI (tmp_result1), 16), ZEXTHIDI (tmp_result0))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* msubsl: msubs.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,msubsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_result1;
+ SI tmp_result0;
+ tmp_result0 = ((LTSI (SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)), SLLSI (1, SUBSI (32, 1)))) ? (SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ tmp_result1 = ((LTSI (SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)), NEGSI (SLLSI (1, SUBSI (32, 1))))) ? (NEGSI (SLLSI (1, SUBSI (32, 1)))) : (((LTSI (SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0)), SLLSI (1, SUBSI (32, 1)))) ? (SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 0), SUBWORDDISI (GET_H_GR (FLD (f_right)), 0))) : (SUBSI (SLLSI (1, SUBSI (32, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTSIDI (tmp_result1), 32), ZEXTSIDI (tmp_result0));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* msubsub: msubs.ub $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,msubsub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)), 0)) ? (0) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)), SLLQI (1, 8))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result1 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)), 0)) ? (0) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)), SLLQI (1, 8))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result2 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)), 0)) ? (0) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)), SLLQI (1, 8))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result3 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)), 0)) ? (0) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)), SLLQI (1, 8))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result4 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)), 0)) ? (0) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)), SLLQI (1, 8))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result5 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)), 0)) ? (0) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)), SLLQI (1, 8))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result6 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)), 0)) ? (0) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)), SLLQI (1, 8))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))) : (SUBQI (SLLQI (1, 8), 1)))));
+ tmp_result7 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)), 0)) ? (0) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)), SLLQI (1, 8))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))) : (SUBQI (SLLQI (1, 8), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* msubsw: msubs.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,msubsw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ QI tmp_result7;
+ QI tmp_result6;
+ QI tmp_result5;
+ QI tmp_result4;
+ QI tmp_result3;
+ QI tmp_result2;
+ QI tmp_result1;
+ QI tmp_result0;
+ tmp_result0 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7)), SLLHI (1, SUBSI (16, 1)))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 7), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 7))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result1 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6)), SLLHI (1, SUBSI (16, 1)))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 6), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 6))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result2 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5)), SLLHI (1, SUBSI (16, 1)))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 5), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 5))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result3 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4)), SLLHI (1, SUBSI (16, 1)))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 4), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 4))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result4 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3)), SLLHI (1, SUBSI (16, 1)))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 3), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 3))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result5 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2)), SLLHI (1, SUBSI (16, 1)))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 2), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 2))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result6 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1)), SLLHI (1, SUBSI (16, 1)))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 1), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 1))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ tmp_result7 = ((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)), NEGHI (SLLHI (1, SUBSI (16, 1))))) ? (NEGHI (SLLHI (1, SUBSI (16, 1)))) : (((LTQI (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0)), SLLHI (1, SUBSI (16, 1)))) ? (SUBQI (SUBWORDDIQI (GET_H_GR (FLD (f_left)), 0), SUBWORDDIQI (GET_H_GR (FLD (f_right)), 0))) : (SUBHI (SLLHI (1, SUBSI (16, 1)), 1)))));
+ {
+ DI opval = ORDI (SLLDI (ZEXTQIDI (tmp_result7), 56), ORDI (SLLDI (ZEXTQIDI (tmp_result6), 48), ORDI (SLLDI (ZEXTQIDI (tmp_result5), 40), ORDI (SLLDI (ZEXTQIDI (tmp_result4), 32), ORDI (SLLDI (ZEXTQIDI (tmp_result3), 24), ORDI (SLLDI (ZEXTQIDI (tmp_result2), 16), ORDI (SLLDI (ZEXTQIDI (tmp_result1), 8), ZEXTQIDI (tmp_result0))))))));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* mulsl: muls.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mulsl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = MULDI (EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), EXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* mulul: mulu.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,mulul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = MULDI (ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1)), ZEXTSIDI (SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* nop: nop */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* nsb: nsb $rm, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,nsb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_xori.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = sh64_nsb (current_cpu, GET_H_GR (FLD (f_left)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ocbi: ocbi $rm, $disp6x32 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ocbi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* ocbp: ocbp $rm, $disp6x32 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ocbp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* ocbwb: ocbwb $rm, $disp6x32 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ocbwb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* or: or $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ORDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ori: ori $rm, $imm10, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ori.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ORDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm10)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* prefi: prefi $rm, $disp6x32 */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,prefi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* pta: pta$likely $disp16, $tra */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,pta) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_pta.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ADDSI (FLD (f_disp16), 1);
+ CPU (h_tr[FLD (f_tra)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "tra", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ptabs: ptabs$likely $rn, $tra */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ptabs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = GET_H_GR (FLD (f_right));
+ CPU (h_tr[FLD (f_tra)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "tra", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ptb: ptb$likely $disp16, $tra */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ptb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_pta.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = FLD (f_disp16);
+ CPU (h_tr[FLD (f_tra)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "tra", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* ptrel: ptrel$likely $rn, $tra */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,ptrel) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ADDDI (pc, GET_H_GR (FLD (f_right)));
+ CPU (h_tr[FLD (f_tra)]) = opval;
+ TRACE_RESULT (current_cpu, abuf, "tra", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* putcfg: putcfg $rm, $disp6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,putcfg) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* putcon: putcon $rm, $crj */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,putcon) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_xori.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = GET_H_GR (FLD (f_left));
+ SET_H_CR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "crj", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* rte: rte */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* shard: shard $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,shard) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = SRADI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shardl: shard.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,shardl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (SRASI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 63)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shari: shari $rm, $uimm6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,shari) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_shari.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = SRADI (GET_H_GR (FLD (f_left)), FLD (f_uimm6));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* sharil: shari.l $rm, $uimm6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,sharil) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_shari.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (SRASI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDSI (FLD (f_uimm6), 63)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shlld: shlld $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,shlld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = SLLDI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shlldl: shlld.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,shlldl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 63)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shlli: shlli $rm, $uimm6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,shlli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_shari.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = SLLDI (GET_H_GR (FLD (f_left)), FLD (f_uimm6));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shllil: shlli.l $rm, $uimm6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,shllil) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_shari.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (SLLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDSI (FLD (f_uimm6), 63)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shlrd: shlrd $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,shlrd) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = SRLDI (GET_H_GR (FLD (f_left)), ANDDI (GET_H_GR (FLD (f_right)), 63));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shlrdl: shlrd.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,shlrdl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (SRLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDDI (GET_H_GR (FLD (f_right)), 63)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shlri: shlri $rm, $uimm6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,shlri) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_shari.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = SRLDI (GET_H_GR (FLD (f_left)), FLD (f_uimm6));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shlril: shlri.l $rm, $uimm6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,shlril) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_shari.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (SRLSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), ANDSI (FLD (f_uimm6), 63)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* shori: shori $uimm16, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,shori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_shori.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = ORDI (SLLDI (GET_H_GR (FLD (f_dest)), 16), ZEXTSIDI (FLD (f_uimm16)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* sleep: sleep */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,sleep) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* stb: st.b $rm, $disp10, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addi.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ UQI opval = ANDQI (GET_H_GR (FLD (f_dest)), 255);
+ SETMEMUQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stl: st.l $rm, $disp10x4, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,stl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_flds.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = ANDSI (GET_H_GR (FLD (f_dest)), 0xffffffff);
+ SETMEMSI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x4))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stq: st.q $rm, $disp10x8, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,stq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fldd.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = GET_H_GR (FLD (f_dest));
+ SETMEMDI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x8))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stw: st.w $rm, $disp10x2, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,stw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lduw.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ HI opval = ANDHI (GET_H_GR (FLD (f_dest)), 65535);
+ SETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_disp10x2))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* sthil: sthi.l $rm, $disp6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,sthil) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_sthil.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ DI tmp_addr;
+ QI tmp_bytecount;
+ DI tmp_val;
+ tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
+ tmp_bytecount = ADDDI (ANDDI (tmp_addr, 3), 1);
+if (GET_H_ENDIAN ()) {
+ tmp_val = GET_H_GR (FLD (f_dest));
+} else {
+ tmp_val = SRLDI (GET_H_GR (FLD (f_dest)), SUBSI (32, MULSI (8, tmp_bytecount)));
+}
+ tmp_addr = ADDDI (SUBDI (tmp_addr, tmp_bytecount), 1);
+if (GTQI (tmp_bytecount, 3)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 2)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 1)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 0)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* sthiq: sthi.q $rm, $disp6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,sthiq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_sthil.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ DI tmp_addr;
+ QI tmp_bytecount;
+ DI tmp_val;
+ tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), FLD (f_disp6));
+ tmp_bytecount = ADDDI (ANDDI (tmp_addr, 7), 1);
+if (GET_H_ENDIAN ()) {
+ tmp_val = GET_H_GR (FLD (f_dest));
+} else {
+ tmp_val = SRLDI (GET_H_GR (FLD (f_dest)), SUBSI (64, MULSI (8, tmp_bytecount)));
+}
+ tmp_addr = ADDDI (SUBDI (tmp_addr, tmp_bytecount), 1);
+if (GTQI (tmp_bytecount, 7)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 6)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 5)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 4)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 3)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 2)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 1)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+if (GTQI (tmp_bytecount, 0)) {
+{
+ {
+ UQI opval = ANDQI (tmp_val, 255);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 4);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+ tmp_val = SRLDI (tmp_val, 8);
+ tmp_addr = ADDDI (tmp_addr, 1);
+}
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* stlol: stlo.l $rm, $disp6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,stlol) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* stloq: stlo.q $rm, $disp6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,stloq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* stxb: stx.b $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,stxb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ UQI opval = SUBWORDDIQI (GET_H_GR (FLD (f_dest)), 7);
+ SETMEMUQI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stxl: stx.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,stxl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ SI opval = SUBWORDDISI (GET_H_GR (FLD (f_dest)), 1);
+ SETMEMSI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stxq: stx.q $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,stxq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = GET_H_GR (FLD (f_dest));
+ SETMEMDI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* stxw: stx.w $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,stxw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ HI opval = SUBWORDDIHI (GET_H_GR (FLD (f_dest)), 3);
+ SETMEMHI (current_cpu, pc, ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right))), opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* sub: sub $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = SUBDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* subl: sub.l $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,subl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = EXTSIDI (SUBSI (SUBWORDDISI (GET_H_GR (FLD (f_left)), 1), SUBWORDDISI (GET_H_GR (FLD (f_right)), 1)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* swapq: swap.q $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,swapq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ DI tmp_addr;
+ DI tmp_temp;
+ tmp_addr = ADDDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
+ tmp_temp = GETMEMDI (current_cpu, pc, tmp_addr);
+ {
+ DI opval = GET_H_GR (FLD (f_dest));
+ SETMEMDI (current_cpu, pc, tmp_addr, opval);
+ TRACE_RESULT (current_cpu, abuf, "memory", 'D', opval);
+ }
+ {
+ DI opval = tmp_temp;
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+}
+
+ return vpc;
+#undef FLD
+}
+
+/* synci: synci */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,synci) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* synco: synco */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,synco) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* trapa: trapa $rm */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,trapa) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_xori.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+sh64_trapa (current_cpu, GET_H_GR (FLD (f_left)), pc);
+
+ return vpc;
+#undef FLD
+}
+
+/* xor: xor $rm, $rn, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_add.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = XORDI (GET_H_GR (FLD (f_left)), GET_H_GR (FLD (f_right)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* xori: xori $rm, $imm6, $rd */
+
+static SEM_PC
+SEM_FN_NAME (sh64_media,xori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_xori.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+ {
+ DI opval = XORDI (GET_H_GR (FLD (f_left)), EXTSIDI (FLD (f_imm6)));
+ SET_H_GR (FLD (f_dest), opval);
+ TRACE_RESULT (current_cpu, abuf, "rd", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* Table of all semantic fns. */
+
+static const struct sem_fn_desc sem_fns[] = {
+ { SH64_MEDIA_INSN_X_INVALID, SEM_FN_NAME (sh64_media,x_invalid) },
+ { SH64_MEDIA_INSN_X_AFTER, SEM_FN_NAME (sh64_media,x_after) },
+ { SH64_MEDIA_INSN_X_BEFORE, SEM_FN_NAME (sh64_media,x_before) },
+ { SH64_MEDIA_INSN_X_CTI_CHAIN, SEM_FN_NAME (sh64_media,x_cti_chain) },
+ { SH64_MEDIA_INSN_X_CHAIN, SEM_FN_NAME (sh64_media,x_chain) },
+ { SH64_MEDIA_INSN_X_BEGIN, SEM_FN_NAME (sh64_media,x_begin) },
+ { SH64_MEDIA_INSN_ADD, SEM_FN_NAME (sh64_media,add) },
+ { SH64_MEDIA_INSN_ADDL, SEM_FN_NAME (sh64_media,addl) },
+ { SH64_MEDIA_INSN_ADDI, SEM_FN_NAME (sh64_media,addi) },
+ { SH64_MEDIA_INSN_ADDIL, SEM_FN_NAME (sh64_media,addil) },
+ { SH64_MEDIA_INSN_ADDZL, SEM_FN_NAME (sh64_media,addzl) },
+ { SH64_MEDIA_INSN_ALLOCO, SEM_FN_NAME (sh64_media,alloco) },
+ { SH64_MEDIA_INSN_AND, SEM_FN_NAME (sh64_media,and) },
+ { SH64_MEDIA_INSN_ANDC, SEM_FN_NAME (sh64_media,andc) },
+ { SH64_MEDIA_INSN_ANDI, SEM_FN_NAME (sh64_media,andi) },
+ { SH64_MEDIA_INSN_BEQ, SEM_FN_NAME (sh64_media,beq) },
+ { SH64_MEDIA_INSN_BEQI, SEM_FN_NAME (sh64_media,beqi) },
+ { SH64_MEDIA_INSN_BGE, SEM_FN_NAME (sh64_media,bge) },
+ { SH64_MEDIA_INSN_BGEU, SEM_FN_NAME (sh64_media,bgeu) },
+ { SH64_MEDIA_INSN_BGT, SEM_FN_NAME (sh64_media,bgt) },
+ { SH64_MEDIA_INSN_BGTU, SEM_FN_NAME (sh64_media,bgtu) },
+ { SH64_MEDIA_INSN_BLINK, SEM_FN_NAME (sh64_media,blink) },
+ { SH64_MEDIA_INSN_BNE, SEM_FN_NAME (sh64_media,bne) },
+ { SH64_MEDIA_INSN_BNEI, SEM_FN_NAME (sh64_media,bnei) },
+ { SH64_MEDIA_INSN_BRK, SEM_FN_NAME (sh64_media,brk) },
+ { SH64_MEDIA_INSN_BYTEREV, SEM_FN_NAME (sh64_media,byterev) },
+ { SH64_MEDIA_INSN_CMPEQ, SEM_FN_NAME (sh64_media,cmpeq) },
+ { SH64_MEDIA_INSN_CMPGT, SEM_FN_NAME (sh64_media,cmpgt) },
+ { SH64_MEDIA_INSN_CMPGTU, SEM_FN_NAME (sh64_media,cmpgtu) },
+ { SH64_MEDIA_INSN_CMVEQ, SEM_FN_NAME (sh64_media,cmveq) },
+ { SH64_MEDIA_INSN_CMVNE, SEM_FN_NAME (sh64_media,cmvne) },
+ { SH64_MEDIA_INSN_FABSD, SEM_FN_NAME (sh64_media,fabsd) },
+ { SH64_MEDIA_INSN_FABSS, SEM_FN_NAME (sh64_media,fabss) },
+ { SH64_MEDIA_INSN_FADDD, SEM_FN_NAME (sh64_media,faddd) },
+ { SH64_MEDIA_INSN_FADDS, SEM_FN_NAME (sh64_media,fadds) },
+ { SH64_MEDIA_INSN_FCMPEQD, SEM_FN_NAME (sh64_media,fcmpeqd) },
+ { SH64_MEDIA_INSN_FCMPEQS, SEM_FN_NAME (sh64_media,fcmpeqs) },
+ { SH64_MEDIA_INSN_FCMPGED, SEM_FN_NAME (sh64_media,fcmpged) },
+ { SH64_MEDIA_INSN_FCMPGES, SEM_FN_NAME (sh64_media,fcmpges) },
+ { SH64_MEDIA_INSN_FCMPGTD, SEM_FN_NAME (sh64_media,fcmpgtd) },
+ { SH64_MEDIA_INSN_FCMPGTS, SEM_FN_NAME (sh64_media,fcmpgts) },
+ { SH64_MEDIA_INSN_FCMPUND, SEM_FN_NAME (sh64_media,fcmpund) },
+ { SH64_MEDIA_INSN_FCMPUNS, SEM_FN_NAME (sh64_media,fcmpuns) },
+ { SH64_MEDIA_INSN_FCNVDS, SEM_FN_NAME (sh64_media,fcnvds) },
+ { SH64_MEDIA_INSN_FCNVSD, SEM_FN_NAME (sh64_media,fcnvsd) },
+ { SH64_MEDIA_INSN_FDIVD, SEM_FN_NAME (sh64_media,fdivd) },
+ { SH64_MEDIA_INSN_FDIVS, SEM_FN_NAME (sh64_media,fdivs) },
+ { SH64_MEDIA_INSN_FGETSCR, SEM_FN_NAME (sh64_media,fgetscr) },
+ { SH64_MEDIA_INSN_FIPRS, SEM_FN_NAME (sh64_media,fiprs) },
+ { SH64_MEDIA_INSN_FLDD, SEM_FN_NAME (sh64_media,fldd) },
+ { SH64_MEDIA_INSN_FLDP, SEM_FN_NAME (sh64_media,fldp) },
+ { SH64_MEDIA_INSN_FLDS, SEM_FN_NAME (sh64_media,flds) },
+ { SH64_MEDIA_INSN_FLDXD, SEM_FN_NAME (sh64_media,fldxd) },
+ { SH64_MEDIA_INSN_FLDXP, SEM_FN_NAME (sh64_media,fldxp) },
+ { SH64_MEDIA_INSN_FLDXS, SEM_FN_NAME (sh64_media,fldxs) },
+ { SH64_MEDIA_INSN_FLOATLD, SEM_FN_NAME (sh64_media,floatld) },
+ { SH64_MEDIA_INSN_FLOATLS, SEM_FN_NAME (sh64_media,floatls) },
+ { SH64_MEDIA_INSN_FLOATQD, SEM_FN_NAME (sh64_media,floatqd) },
+ { SH64_MEDIA_INSN_FLOATQS, SEM_FN_NAME (sh64_media,floatqs) },
+ { SH64_MEDIA_INSN_FMACS, SEM_FN_NAME (sh64_media,fmacs) },
+ { SH64_MEDIA_INSN_FMOVD, SEM_FN_NAME (sh64_media,fmovd) },
+ { SH64_MEDIA_INSN_FMOVDQ, SEM_FN_NAME (sh64_media,fmovdq) },
+ { SH64_MEDIA_INSN_FMOVLS, SEM_FN_NAME (sh64_media,fmovls) },
+ { SH64_MEDIA_INSN_FMOVQD, SEM_FN_NAME (sh64_media,fmovqd) },
+ { SH64_MEDIA_INSN_FMOVS, SEM_FN_NAME (sh64_media,fmovs) },
+ { SH64_MEDIA_INSN_FMOVSL, SEM_FN_NAME (sh64_media,fmovsl) },
+ { SH64_MEDIA_INSN_FMULD, SEM_FN_NAME (sh64_media,fmuld) },
+ { SH64_MEDIA_INSN_FMULS, SEM_FN_NAME (sh64_media,fmuls) },
+ { SH64_MEDIA_INSN_FNEGD, SEM_FN_NAME (sh64_media,fnegd) },
+ { SH64_MEDIA_INSN_FNEGS, SEM_FN_NAME (sh64_media,fnegs) },
+ { SH64_MEDIA_INSN_FPUTSCR, SEM_FN_NAME (sh64_media,fputscr) },
+ { SH64_MEDIA_INSN_FSQRTD, SEM_FN_NAME (sh64_media,fsqrtd) },
+ { SH64_MEDIA_INSN_FSQRTS, SEM_FN_NAME (sh64_media,fsqrts) },
+ { SH64_MEDIA_INSN_FSTD, SEM_FN_NAME (sh64_media,fstd) },
+ { SH64_MEDIA_INSN_FSTP, SEM_FN_NAME (sh64_media,fstp) },
+ { SH64_MEDIA_INSN_FSTS, SEM_FN_NAME (sh64_media,fsts) },
+ { SH64_MEDIA_INSN_FSTXD, SEM_FN_NAME (sh64_media,fstxd) },
+ { SH64_MEDIA_INSN_FSTXP, SEM_FN_NAME (sh64_media,fstxp) },
+ { SH64_MEDIA_INSN_FSTXS, SEM_FN_NAME (sh64_media,fstxs) },
+ { SH64_MEDIA_INSN_FSUBD, SEM_FN_NAME (sh64_media,fsubd) },
+ { SH64_MEDIA_INSN_FSUBS, SEM_FN_NAME (sh64_media,fsubs) },
+ { SH64_MEDIA_INSN_FTRCDL, SEM_FN_NAME (sh64_media,ftrcdl) },
+ { SH64_MEDIA_INSN_FTRCSL, SEM_FN_NAME (sh64_media,ftrcsl) },
+ { SH64_MEDIA_INSN_FTRCDQ, SEM_FN_NAME (sh64_media,ftrcdq) },
+ { SH64_MEDIA_INSN_FTRCSQ, SEM_FN_NAME (sh64_media,ftrcsq) },
+ { SH64_MEDIA_INSN_FTRVS, SEM_FN_NAME (sh64_media,ftrvs) },
+ { SH64_MEDIA_INSN_GETCFG, SEM_FN_NAME (sh64_media,getcfg) },
+ { SH64_MEDIA_INSN_GETCON, SEM_FN_NAME (sh64_media,getcon) },
+ { SH64_MEDIA_INSN_GETTR, SEM_FN_NAME (sh64_media,gettr) },
+ { SH64_MEDIA_INSN_ICBI, SEM_FN_NAME (sh64_media,icbi) },
+ { SH64_MEDIA_INSN_LDB, SEM_FN_NAME (sh64_media,ldb) },
+ { SH64_MEDIA_INSN_LDL, SEM_FN_NAME (sh64_media,ldl) },
+ { SH64_MEDIA_INSN_LDQ, SEM_FN_NAME (sh64_media,ldq) },
+ { SH64_MEDIA_INSN_LDUB, SEM_FN_NAME (sh64_media,ldub) },
+ { SH64_MEDIA_INSN_LDUW, SEM_FN_NAME (sh64_media,lduw) },
+ { SH64_MEDIA_INSN_LDW, SEM_FN_NAME (sh64_media,ldw) },
+ { SH64_MEDIA_INSN_LDHIL, SEM_FN_NAME (sh64_media,ldhil) },
+ { SH64_MEDIA_INSN_LDHIQ, SEM_FN_NAME (sh64_media,ldhiq) },
+ { SH64_MEDIA_INSN_LDLOL, SEM_FN_NAME (sh64_media,ldlol) },
+ { SH64_MEDIA_INSN_LDLOQ, SEM_FN_NAME (sh64_media,ldloq) },
+ { SH64_MEDIA_INSN_LDXB, SEM_FN_NAME (sh64_media,ldxb) },
+ { SH64_MEDIA_INSN_LDXL, SEM_FN_NAME (sh64_media,ldxl) },
+ { SH64_MEDIA_INSN_LDXQ, SEM_FN_NAME (sh64_media,ldxq) },
+ { SH64_MEDIA_INSN_LDXUB, SEM_FN_NAME (sh64_media,ldxub) },
+ { SH64_MEDIA_INSN_LDXUW, SEM_FN_NAME (sh64_media,ldxuw) },
+ { SH64_MEDIA_INSN_LDXW, SEM_FN_NAME (sh64_media,ldxw) },
+ { SH64_MEDIA_INSN_MABSL, SEM_FN_NAME (sh64_media,mabsl) },
+ { SH64_MEDIA_INSN_MABSW, SEM_FN_NAME (sh64_media,mabsw) },
+ { SH64_MEDIA_INSN_MADDL, SEM_FN_NAME (sh64_media,maddl) },
+ { SH64_MEDIA_INSN_MADDW, SEM_FN_NAME (sh64_media,maddw) },
+ { SH64_MEDIA_INSN_MADDSL, SEM_FN_NAME (sh64_media,maddsl) },
+ { SH64_MEDIA_INSN_MADDSUB, SEM_FN_NAME (sh64_media,maddsub) },
+ { SH64_MEDIA_INSN_MADDSW, SEM_FN_NAME (sh64_media,maddsw) },
+ { SH64_MEDIA_INSN_MCMPEQB, SEM_FN_NAME (sh64_media,mcmpeqb) },
+ { SH64_MEDIA_INSN_MCMPEQL, SEM_FN_NAME (sh64_media,mcmpeql) },
+ { SH64_MEDIA_INSN_MCMPEQW, SEM_FN_NAME (sh64_media,mcmpeqw) },
+ { SH64_MEDIA_INSN_MCMPGTL, SEM_FN_NAME (sh64_media,mcmpgtl) },
+ { SH64_MEDIA_INSN_MCMPGTUB, SEM_FN_NAME (sh64_media,mcmpgtub) },
+ { SH64_MEDIA_INSN_MCMPGTW, SEM_FN_NAME (sh64_media,mcmpgtw) },
+ { SH64_MEDIA_INSN_MCMV, SEM_FN_NAME (sh64_media,mcmv) },
+ { SH64_MEDIA_INSN_MCNVSLW, SEM_FN_NAME (sh64_media,mcnvslw) },
+ { SH64_MEDIA_INSN_MCNVSWB, SEM_FN_NAME (sh64_media,mcnvswb) },
+ { SH64_MEDIA_INSN_MCNVSWUB, SEM_FN_NAME (sh64_media,mcnvswub) },
+ { SH64_MEDIA_INSN_MEXTR1, SEM_FN_NAME (sh64_media,mextr1) },
+ { SH64_MEDIA_INSN_MEXTR2, SEM_FN_NAME (sh64_media,mextr2) },
+ { SH64_MEDIA_INSN_MEXTR3, SEM_FN_NAME (sh64_media,mextr3) },
+ { SH64_MEDIA_INSN_MEXTR4, SEM_FN_NAME (sh64_media,mextr4) },
+ { SH64_MEDIA_INSN_MEXTR5, SEM_FN_NAME (sh64_media,mextr5) },
+ { SH64_MEDIA_INSN_MEXTR6, SEM_FN_NAME (sh64_media,mextr6) },
+ { SH64_MEDIA_INSN_MEXTR7, SEM_FN_NAME (sh64_media,mextr7) },
+ { SH64_MEDIA_INSN_MMACFXWL, SEM_FN_NAME (sh64_media,mmacfxwl) },
+ { SH64_MEDIA_INSN_MMACNFX_WL, SEM_FN_NAME (sh64_media,mmacnfx_wl) },
+ { SH64_MEDIA_INSN_MMULL, SEM_FN_NAME (sh64_media,mmull) },
+ { SH64_MEDIA_INSN_MMULW, SEM_FN_NAME (sh64_media,mmulw) },
+ { SH64_MEDIA_INSN_MMULFXL, SEM_FN_NAME (sh64_media,mmulfxl) },
+ { SH64_MEDIA_INSN_MMULFXW, SEM_FN_NAME (sh64_media,mmulfxw) },
+ { SH64_MEDIA_INSN_MMULFXRPW, SEM_FN_NAME (sh64_media,mmulfxrpw) },
+ { SH64_MEDIA_INSN_MMULHIWL, SEM_FN_NAME (sh64_media,mmulhiwl) },
+ { SH64_MEDIA_INSN_MMULLOWL, SEM_FN_NAME (sh64_media,mmullowl) },
+ { SH64_MEDIA_INSN_MMULSUMWQ, SEM_FN_NAME (sh64_media,mmulsumwq) },
+ { SH64_MEDIA_INSN_MOVI, SEM_FN_NAME (sh64_media,movi) },
+ { SH64_MEDIA_INSN_MPERMW, SEM_FN_NAME (sh64_media,mpermw) },
+ { SH64_MEDIA_INSN_MSADUBQ, SEM_FN_NAME (sh64_media,msadubq) },
+ { SH64_MEDIA_INSN_MSHALDSL, SEM_FN_NAME (sh64_media,mshaldsl) },
+ { SH64_MEDIA_INSN_MSHALDSW, SEM_FN_NAME (sh64_media,mshaldsw) },
+ { SH64_MEDIA_INSN_MSHARDL, SEM_FN_NAME (sh64_media,mshardl) },
+ { SH64_MEDIA_INSN_MSHARDW, SEM_FN_NAME (sh64_media,mshardw) },
+ { SH64_MEDIA_INSN_MSHARDSQ, SEM_FN_NAME (sh64_media,mshardsq) },
+ { SH64_MEDIA_INSN_MSHFHIB, SEM_FN_NAME (sh64_media,mshfhib) },
+ { SH64_MEDIA_INSN_MSHFHIL, SEM_FN_NAME (sh64_media,mshfhil) },
+ { SH64_MEDIA_INSN_MSHFHIW, SEM_FN_NAME (sh64_media,mshfhiw) },
+ { SH64_MEDIA_INSN_MSHFLOB, SEM_FN_NAME (sh64_media,mshflob) },
+ { SH64_MEDIA_INSN_MSHFLOL, SEM_FN_NAME (sh64_media,mshflol) },
+ { SH64_MEDIA_INSN_MSHFLOW, SEM_FN_NAME (sh64_media,mshflow) },
+ { SH64_MEDIA_INSN_MSHLLDL, SEM_FN_NAME (sh64_media,mshlldl) },
+ { SH64_MEDIA_INSN_MSHLLDW, SEM_FN_NAME (sh64_media,mshlldw) },
+ { SH64_MEDIA_INSN_MSHLRDL, SEM_FN_NAME (sh64_media,mshlrdl) },
+ { SH64_MEDIA_INSN_MSHLRDW, SEM_FN_NAME (sh64_media,mshlrdw) },
+ { SH64_MEDIA_INSN_MSUBL, SEM_FN_NAME (sh64_media,msubl) },
+ { SH64_MEDIA_INSN_MSUBW, SEM_FN_NAME (sh64_media,msubw) },
+ { SH64_MEDIA_INSN_MSUBSL, SEM_FN_NAME (sh64_media,msubsl) },
+ { SH64_MEDIA_INSN_MSUBSUB, SEM_FN_NAME (sh64_media,msubsub) },
+ { SH64_MEDIA_INSN_MSUBSW, SEM_FN_NAME (sh64_media,msubsw) },
+ { SH64_MEDIA_INSN_MULSL, SEM_FN_NAME (sh64_media,mulsl) },
+ { SH64_MEDIA_INSN_MULUL, SEM_FN_NAME (sh64_media,mulul) },
+ { SH64_MEDIA_INSN_NOP, SEM_FN_NAME (sh64_media,nop) },
+ { SH64_MEDIA_INSN_NSB, SEM_FN_NAME (sh64_media,nsb) },
+ { SH64_MEDIA_INSN_OCBI, SEM_FN_NAME (sh64_media,ocbi) },
+ { SH64_MEDIA_INSN_OCBP, SEM_FN_NAME (sh64_media,ocbp) },
+ { SH64_MEDIA_INSN_OCBWB, SEM_FN_NAME (sh64_media,ocbwb) },
+ { SH64_MEDIA_INSN_OR, SEM_FN_NAME (sh64_media,or) },
+ { SH64_MEDIA_INSN_ORI, SEM_FN_NAME (sh64_media,ori) },
+ { SH64_MEDIA_INSN_PREFI, SEM_FN_NAME (sh64_media,prefi) },
+ { SH64_MEDIA_INSN_PTA, SEM_FN_NAME (sh64_media,pta) },
+ { SH64_MEDIA_INSN_PTABS, SEM_FN_NAME (sh64_media,ptabs) },
+ { SH64_MEDIA_INSN_PTB, SEM_FN_NAME (sh64_media,ptb) },
+ { SH64_MEDIA_INSN_PTREL, SEM_FN_NAME (sh64_media,ptrel) },
+ { SH64_MEDIA_INSN_PUTCFG, SEM_FN_NAME (sh64_media,putcfg) },
+ { SH64_MEDIA_INSN_PUTCON, SEM_FN_NAME (sh64_media,putcon) },
+ { SH64_MEDIA_INSN_RTE, SEM_FN_NAME (sh64_media,rte) },
+ { SH64_MEDIA_INSN_SHARD, SEM_FN_NAME (sh64_media,shard) },
+ { SH64_MEDIA_INSN_SHARDL, SEM_FN_NAME (sh64_media,shardl) },
+ { SH64_MEDIA_INSN_SHARI, SEM_FN_NAME (sh64_media,shari) },
+ { SH64_MEDIA_INSN_SHARIL, SEM_FN_NAME (sh64_media,sharil) },
+ { SH64_MEDIA_INSN_SHLLD, SEM_FN_NAME (sh64_media,shlld) },
+ { SH64_MEDIA_INSN_SHLLDL, SEM_FN_NAME (sh64_media,shlldl) },
+ { SH64_MEDIA_INSN_SHLLI, SEM_FN_NAME (sh64_media,shlli) },
+ { SH64_MEDIA_INSN_SHLLIL, SEM_FN_NAME (sh64_media,shllil) },
+ { SH64_MEDIA_INSN_SHLRD, SEM_FN_NAME (sh64_media,shlrd) },
+ { SH64_MEDIA_INSN_SHLRDL, SEM_FN_NAME (sh64_media,shlrdl) },
+ { SH64_MEDIA_INSN_SHLRI, SEM_FN_NAME (sh64_media,shlri) },
+ { SH64_MEDIA_INSN_SHLRIL, SEM_FN_NAME (sh64_media,shlril) },
+ { SH64_MEDIA_INSN_SHORI, SEM_FN_NAME (sh64_media,shori) },
+ { SH64_MEDIA_INSN_SLEEP, SEM_FN_NAME (sh64_media,sleep) },
+ { SH64_MEDIA_INSN_STB, SEM_FN_NAME (sh64_media,stb) },
+ { SH64_MEDIA_INSN_STL, SEM_FN_NAME (sh64_media,stl) },
+ { SH64_MEDIA_INSN_STQ, SEM_FN_NAME (sh64_media,stq) },
+ { SH64_MEDIA_INSN_STW, SEM_FN_NAME (sh64_media,stw) },
+ { SH64_MEDIA_INSN_STHIL, SEM_FN_NAME (sh64_media,sthil) },
+ { SH64_MEDIA_INSN_STHIQ, SEM_FN_NAME (sh64_media,sthiq) },
+ { SH64_MEDIA_INSN_STLOL, SEM_FN_NAME (sh64_media,stlol) },
+ { SH64_MEDIA_INSN_STLOQ, SEM_FN_NAME (sh64_media,stloq) },
+ { SH64_MEDIA_INSN_STXB, SEM_FN_NAME (sh64_media,stxb) },
+ { SH64_MEDIA_INSN_STXL, SEM_FN_NAME (sh64_media,stxl) },
+ { SH64_MEDIA_INSN_STXQ, SEM_FN_NAME (sh64_media,stxq) },
+ { SH64_MEDIA_INSN_STXW, SEM_FN_NAME (sh64_media,stxw) },
+ { SH64_MEDIA_INSN_SUB, SEM_FN_NAME (sh64_media,sub) },
+ { SH64_MEDIA_INSN_SUBL, SEM_FN_NAME (sh64_media,subl) },
+ { SH64_MEDIA_INSN_SWAPQ, SEM_FN_NAME (sh64_media,swapq) },
+ { SH64_MEDIA_INSN_SYNCI, SEM_FN_NAME (sh64_media,synci) },
+ { SH64_MEDIA_INSN_SYNCO, SEM_FN_NAME (sh64_media,synco) },
+ { SH64_MEDIA_INSN_TRAPA, SEM_FN_NAME (sh64_media,trapa) },
+ { SH64_MEDIA_INSN_XOR, SEM_FN_NAME (sh64_media,xor) },
+ { SH64_MEDIA_INSN_XORI, SEM_FN_NAME (sh64_media,xori) },
+ { 0, 0 }
+};
+
+/* Add the semantic fns to IDESC_TABLE. */
+
+void
+SEM_FN_NAME (sh64_media,init_idesc_table) (SIM_CPU *current_cpu)
+{
+ IDESC *idesc_table = CPU_IDESC (current_cpu);
+ const struct sem_fn_desc *sf;
+ int mach_num = MACH_NUM (CPU_MACH (current_cpu));
+
+ for (sf = &sem_fns[0]; sf->fn != 0; ++sf)
+ {
+ const CGEN_INSN *insn = idesc_table[sf->index].idata;
+ int valid_p = (CGEN_INSN_VIRTUAL_P (insn)
+ || CGEN_INSN_MACH_HAS_P (insn, mach_num));
+#if FAST_P
+ if (valid_p)
+ idesc_table[sf->index].sem_fast = sf->fn;
+ else
+ idesc_table[sf->index].sem_fast = SEM_FN_NAME (sh64_media,x_invalid);
+#else
+ if (valid_p)
+ idesc_table[sf->index].sem_full = sf->fn;
+ else
+ idesc_table[sf->index].sem_full = SEM_FN_NAME (sh64_media,x_invalid);
+#endif
+ }
+}
+
--- /dev/null
+/* CPU data for sh.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sysdep.h"
+#include <ctype.h>
+#include <stdio.h>
+#include <stdarg.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "sh-desc.h"
+#include "sh-opc.h"
+#include "opintl.h"
+#include "libiberty.h"
+
+/* Attributes. */
+
+static const CGEN_ATTR_ENTRY bool_attr[] =
+{
+ { "#f", 0 },
+ { "#t", 1 },
+ { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY MACH_attr[] =
+{
+ { "base", MACH_BASE },
+ { "sh2", MACH_SH2 },
+ { "sh3", MACH_SH3 },
+ { "sh3e", MACH_SH3E },
+ { "sh4", MACH_SH4 },
+ { "sh5", MACH_SH5 },
+ { "max", MACH_MAX },
+ { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY ISA_attr[] =
+{
+ { "compact", ISA_COMPACT },
+ { "media", ISA_MEDIA },
+ { "max", ISA_MAX },
+ { 0, 0 }
+};
+
+const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "ISA", & ISA_attr[0], & ISA_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "RESERVED", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "PC", &bool_attr[0], &bool_attr[0] },
+ { "PROFILE", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE sh_cgen_operand_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "ISA", & ISA_attr[0], & ISA_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+ { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+ { "SIGNED", &bool_attr[0], &bool_attr[0] },
+ { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
+ { "RELAX", &bool_attr[0], &bool_attr[0] },
+ { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[] =
+{
+ { "MACH", & MACH_attr[0], & MACH_attr[0] },
+ { "ISA", & ISA_attr[0], & ISA_attr[0] },
+ { "ALIAS", &bool_attr[0], &bool_attr[0] },
+ { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+ { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "COND-CTI", &bool_attr[0], &bool_attr[0] },
+ { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
+ { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
+ { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
+ { "RELAX", &bool_attr[0], &bool_attr[0] },
+ { "NO-DIS", &bool_attr[0], &bool_attr[0] },
+ { "PBB", &bool_attr[0], &bool_attr[0] },
+ { "ILLSLOT", &bool_attr[0], &bool_attr[0] },
+ { "FP-INSN", &bool_attr[0], &bool_attr[0] },
+ { 0, 0, 0 }
+};
+
+/* Instruction set variants. */
+
+static const CGEN_ISA sh_cgen_isa_table[] = {
+ { "media", 32, 32, 32, 32 },
+ { "compact", 16, 16, 16, 16 },
+ { 0, 0, 0, 0, 0 }
+};
+
+/* Machine variants. */
+
+static const CGEN_MACH sh_cgen_mach_table[] = {
+ { "sh2", "sh2", MACH_SH2 },
+ { "sh3", "sh3", MACH_SH3 },
+ { "sh3e", "sh3e", MACH_SH3E },
+ { "sh4", "sh4", MACH_SH4 },
+ { "sh5", "sh5", MACH_SH5 },
+ { 0, 0, 0 }
+};
+
+static CGEN_KEYWORD_ENTRY sh_cgen_opval_frc_names_entries[] =
+{
+ { "fr0", 0, {0, {0}}, 0, 0 },
+ { "fr1", 1, {0, {0}}, 0, 0 },
+ { "fr2", 2, {0, {0}}, 0, 0 },
+ { "fr3", 3, {0, {0}}, 0, 0 },
+ { "fr4", 4, {0, {0}}, 0, 0 },
+ { "fr5", 5, {0, {0}}, 0, 0 },
+ { "fr6", 6, {0, {0}}, 0, 0 },
+ { "fr7", 7, {0, {0}}, 0, 0 },
+ { "fr8", 8, {0, {0}}, 0, 0 },
+ { "fr9", 9, {0, {0}}, 0, 0 },
+ { "fr10", 10, {0, {0}}, 0, 0 },
+ { "fr11", 11, {0, {0}}, 0, 0 },
+ { "fr12", 12, {0, {0}}, 0, 0 },
+ { "fr13", 13, {0, {0}}, 0, 0 },
+ { "fr14", 14, {0, {0}}, 0, 0 },
+ { "fr15", 15, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD sh_cgen_opval_frc_names =
+{
+ & sh_cgen_opval_frc_names_entries[0],
+ 16,
+ 0, 0, 0, 0
+};
+
+static CGEN_KEYWORD_ENTRY sh_cgen_opval_drc_names_entries[] =
+{
+ { "dr0", 0, {0, {0}}, 0, 0 },
+ { "dr2", 2, {0, {0}}, 0, 0 },
+ { "dr4", 4, {0, {0}}, 0, 0 },
+ { "dr6", 6, {0, {0}}, 0, 0 },
+ { "dr8", 8, {0, {0}}, 0, 0 },
+ { "dr10", 10, {0, {0}}, 0, 0 },
+ { "dr12", 12, {0, {0}}, 0, 0 },
+ { "dr14", 14, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD sh_cgen_opval_drc_names =
+{
+ & sh_cgen_opval_drc_names_entries[0],
+ 8,
+ 0, 0, 0, 0
+};
+
+static CGEN_KEYWORD_ENTRY sh_cgen_opval_xf_names_entries[] =
+{
+ { "xf0", 0, {0, {0}}, 0, 0 },
+ { "xf1", 1, {0, {0}}, 0, 0 },
+ { "xf2", 2, {0, {0}}, 0, 0 },
+ { "xf3", 3, {0, {0}}, 0, 0 },
+ { "xf4", 4, {0, {0}}, 0, 0 },
+ { "xf5", 5, {0, {0}}, 0, 0 },
+ { "xf6", 6, {0, {0}}, 0, 0 },
+ { "xf7", 7, {0, {0}}, 0, 0 },
+ { "xf8", 8, {0, {0}}, 0, 0 },
+ { "xf9", 9, {0, {0}}, 0, 0 },
+ { "xf10", 10, {0, {0}}, 0, 0 },
+ { "xf11", 11, {0, {0}}, 0, 0 },
+ { "xf12", 12, {0, {0}}, 0, 0 },
+ { "xf13", 13, {0, {0}}, 0, 0 },
+ { "xf14", 14, {0, {0}}, 0, 0 },
+ { "xf15", 15, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD sh_cgen_opval_xf_names =
+{
+ & sh_cgen_opval_xf_names_entries[0],
+ 16,
+ 0, 0, 0, 0
+};
+
+static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_gr_entries[] =
+{
+ { "r0", 0, {0, {0}}, 0, 0 },
+ { "r1", 1, {0, {0}}, 0, 0 },
+ { "r2", 2, {0, {0}}, 0, 0 },
+ { "r3", 3, {0, {0}}, 0, 0 },
+ { "r4", 4, {0, {0}}, 0, 0 },
+ { "r5", 5, {0, {0}}, 0, 0 },
+ { "r6", 6, {0, {0}}, 0, 0 },
+ { "r7", 7, {0, {0}}, 0, 0 },
+ { "r8", 8, {0, {0}}, 0, 0 },
+ { "r9", 9, {0, {0}}, 0, 0 },
+ { "r10", 10, {0, {0}}, 0, 0 },
+ { "r11", 11, {0, {0}}, 0, 0 },
+ { "r12", 12, {0, {0}}, 0, 0 },
+ { "r13", 13, {0, {0}}, 0, 0 },
+ { "r14", 14, {0, {0}}, 0, 0 },
+ { "r15", 15, {0, {0}}, 0, 0 },
+ { "r16", 16, {0, {0}}, 0, 0 },
+ { "r17", 17, {0, {0}}, 0, 0 },
+ { "r18", 18, {0, {0}}, 0, 0 },
+ { "r19", 19, {0, {0}}, 0, 0 },
+ { "r20", 20, {0, {0}}, 0, 0 },
+ { "r21", 21, {0, {0}}, 0, 0 },
+ { "r22", 22, {0, {0}}, 0, 0 },
+ { "r23", 23, {0, {0}}, 0, 0 },
+ { "r24", 24, {0, {0}}, 0, 0 },
+ { "r25", 25, {0, {0}}, 0, 0 },
+ { "r26", 26, {0, {0}}, 0, 0 },
+ { "r27", 27, {0, {0}}, 0, 0 },
+ { "r28", 28, {0, {0}}, 0, 0 },
+ { "r29", 29, {0, {0}}, 0, 0 },
+ { "r30", 30, {0, {0}}, 0, 0 },
+ { "r31", 31, {0, {0}}, 0, 0 },
+ { "r32", 32, {0, {0}}, 0, 0 },
+ { "r33", 33, {0, {0}}, 0, 0 },
+ { "r34", 34, {0, {0}}, 0, 0 },
+ { "r35", 35, {0, {0}}, 0, 0 },
+ { "r36", 36, {0, {0}}, 0, 0 },
+ { "r37", 37, {0, {0}}, 0, 0 },
+ { "r38", 38, {0, {0}}, 0, 0 },
+ { "r39", 39, {0, {0}}, 0, 0 },
+ { "r40", 40, {0, {0}}, 0, 0 },
+ { "r41", 41, {0, {0}}, 0, 0 },
+ { "r42", 42, {0, {0}}, 0, 0 },
+ { "r43", 43, {0, {0}}, 0, 0 },
+ { "r44", 44, {0, {0}}, 0, 0 },
+ { "r45", 45, {0, {0}}, 0, 0 },
+ { "r46", 46, {0, {0}}, 0, 0 },
+ { "r47", 47, {0, {0}}, 0, 0 },
+ { "r48", 48, {0, {0}}, 0, 0 },
+ { "r49", 49, {0, {0}}, 0, 0 },
+ { "r50", 50, {0, {0}}, 0, 0 },
+ { "r51", 51, {0, {0}}, 0, 0 },
+ { "r52", 52, {0, {0}}, 0, 0 },
+ { "r53", 53, {0, {0}}, 0, 0 },
+ { "r54", 54, {0, {0}}, 0, 0 },
+ { "r55", 55, {0, {0}}, 0, 0 },
+ { "r56", 56, {0, {0}}, 0, 0 },
+ { "r57", 57, {0, {0}}, 0, 0 },
+ { "r58", 58, {0, {0}}, 0, 0 },
+ { "r59", 59, {0, {0}}, 0, 0 },
+ { "r60", 60, {0, {0}}, 0, 0 },
+ { "r61", 61, {0, {0}}, 0, 0 },
+ { "r62", 62, {0, {0}}, 0, 0 },
+ { "r63", 63, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD sh_cgen_opval_h_gr =
+{
+ & sh_cgen_opval_h_gr_entries[0],
+ 64,
+ 0, 0, 0, 0
+};
+
+static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_grc_entries[] =
+{
+ { "r0", 0, {0, {0}}, 0, 0 },
+ { "r1", 1, {0, {0}}, 0, 0 },
+ { "r2", 2, {0, {0}}, 0, 0 },
+ { "r3", 3, {0, {0}}, 0, 0 },
+ { "r4", 4, {0, {0}}, 0, 0 },
+ { "r5", 5, {0, {0}}, 0, 0 },
+ { "r6", 6, {0, {0}}, 0, 0 },
+ { "r7", 7, {0, {0}}, 0, 0 },
+ { "r8", 8, {0, {0}}, 0, 0 },
+ { "r9", 9, {0, {0}}, 0, 0 },
+ { "r10", 10, {0, {0}}, 0, 0 },
+ { "r11", 11, {0, {0}}, 0, 0 },
+ { "r12", 12, {0, {0}}, 0, 0 },
+ { "r13", 13, {0, {0}}, 0, 0 },
+ { "r14", 14, {0, {0}}, 0, 0 },
+ { "r15", 15, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD sh_cgen_opval_h_grc =
+{
+ & sh_cgen_opval_h_grc_entries[0],
+ 16,
+ 0, 0, 0, 0
+};
+
+static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_cr_entries[] =
+{
+ { "cr0", 0, {0, {0}}, 0, 0 },
+ { "cr1", 1, {0, {0}}, 0, 0 },
+ { "cr2", 2, {0, {0}}, 0, 0 },
+ { "cr3", 3, {0, {0}}, 0, 0 },
+ { "cr4", 4, {0, {0}}, 0, 0 },
+ { "cr5", 5, {0, {0}}, 0, 0 },
+ { "cr6", 6, {0, {0}}, 0, 0 },
+ { "cr7", 7, {0, {0}}, 0, 0 },
+ { "cr8", 8, {0, {0}}, 0, 0 },
+ { "cr9", 9, {0, {0}}, 0, 0 },
+ { "cr10", 10, {0, {0}}, 0, 0 },
+ { "cr11", 11, {0, {0}}, 0, 0 },
+ { "cr12", 12, {0, {0}}, 0, 0 },
+ { "cr13", 13, {0, {0}}, 0, 0 },
+ { "cr14", 14, {0, {0}}, 0, 0 },
+ { "cr15", 15, {0, {0}}, 0, 0 },
+ { "cr16", 16, {0, {0}}, 0, 0 },
+ { "cr17", 17, {0, {0}}, 0, 0 },
+ { "cr18", 18, {0, {0}}, 0, 0 },
+ { "cr19", 19, {0, {0}}, 0, 0 },
+ { "cr20", 20, {0, {0}}, 0, 0 },
+ { "cr21", 21, {0, {0}}, 0, 0 },
+ { "cr22", 22, {0, {0}}, 0, 0 },
+ { "cr23", 23, {0, {0}}, 0, 0 },
+ { "cr24", 24, {0, {0}}, 0, 0 },
+ { "cr25", 25, {0, {0}}, 0, 0 },
+ { "cr26", 26, {0, {0}}, 0, 0 },
+ { "cr27", 27, {0, {0}}, 0, 0 },
+ { "cr28", 28, {0, {0}}, 0, 0 },
+ { "cr29", 29, {0, {0}}, 0, 0 },
+ { "cr30", 30, {0, {0}}, 0, 0 },
+ { "cr31", 31, {0, {0}}, 0, 0 },
+ { "cr32", 32, {0, {0}}, 0, 0 },
+ { "cr33", 33, {0, {0}}, 0, 0 },
+ { "cr34", 34, {0, {0}}, 0, 0 },
+ { "cr35", 35, {0, {0}}, 0, 0 },
+ { "cr36", 36, {0, {0}}, 0, 0 },
+ { "cr37", 37, {0, {0}}, 0, 0 },
+ { "cr38", 38, {0, {0}}, 0, 0 },
+ { "cr39", 39, {0, {0}}, 0, 0 },
+ { "cr40", 40, {0, {0}}, 0, 0 },
+ { "cr41", 41, {0, {0}}, 0, 0 },
+ { "cr42", 42, {0, {0}}, 0, 0 },
+ { "cr43", 43, {0, {0}}, 0, 0 },
+ { "cr44", 44, {0, {0}}, 0, 0 },
+ { "cr45", 45, {0, {0}}, 0, 0 },
+ { "cr46", 46, {0, {0}}, 0, 0 },
+ { "cr47", 47, {0, {0}}, 0, 0 },
+ { "cr48", 48, {0, {0}}, 0, 0 },
+ { "cr49", 49, {0, {0}}, 0, 0 },
+ { "cr50", 50, {0, {0}}, 0, 0 },
+ { "cr51", 51, {0, {0}}, 0, 0 },
+ { "cr52", 52, {0, {0}}, 0, 0 },
+ { "cr53", 53, {0, {0}}, 0, 0 },
+ { "cr54", 54, {0, {0}}, 0, 0 },
+ { "cr55", 55, {0, {0}}, 0, 0 },
+ { "cr56", 56, {0, {0}}, 0, 0 },
+ { "cr57", 57, {0, {0}}, 0, 0 },
+ { "cr58", 58, {0, {0}}, 0, 0 },
+ { "cr59", 59, {0, {0}}, 0, 0 },
+ { "cr60", 60, {0, {0}}, 0, 0 },
+ { "cr61", 61, {0, {0}}, 0, 0 },
+ { "cr62", 62, {0, {0}}, 0, 0 },
+ { "cr63", 63, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD sh_cgen_opval_h_cr =
+{
+ & sh_cgen_opval_h_cr_entries[0],
+ 64,
+ 0, 0, 0, 0
+};
+
+static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fr_entries[] =
+{
+ { "fr0", 0, {0, {0}}, 0, 0 },
+ { "fr1", 1, {0, {0}}, 0, 0 },
+ { "fr2", 2, {0, {0}}, 0, 0 },
+ { "fr3", 3, {0, {0}}, 0, 0 },
+ { "fr4", 4, {0, {0}}, 0, 0 },
+ { "fr5", 5, {0, {0}}, 0, 0 },
+ { "fr6", 6, {0, {0}}, 0, 0 },
+ { "fr7", 7, {0, {0}}, 0, 0 },
+ { "fr8", 8, {0, {0}}, 0, 0 },
+ { "fr9", 9, {0, {0}}, 0, 0 },
+ { "fr10", 10, {0, {0}}, 0, 0 },
+ { "fr11", 11, {0, {0}}, 0, 0 },
+ { "fr12", 12, {0, {0}}, 0, 0 },
+ { "fr13", 13, {0, {0}}, 0, 0 },
+ { "fr14", 14, {0, {0}}, 0, 0 },
+ { "fr15", 15, {0, {0}}, 0, 0 },
+ { "fr16", 16, {0, {0}}, 0, 0 },
+ { "fr17", 17, {0, {0}}, 0, 0 },
+ { "fr18", 18, {0, {0}}, 0, 0 },
+ { "fr19", 19, {0, {0}}, 0, 0 },
+ { "fr20", 20, {0, {0}}, 0, 0 },
+ { "fr21", 21, {0, {0}}, 0, 0 },
+ { "fr22", 22, {0, {0}}, 0, 0 },
+ { "fr23", 23, {0, {0}}, 0, 0 },
+ { "fr24", 24, {0, {0}}, 0, 0 },
+ { "fr25", 25, {0, {0}}, 0, 0 },
+ { "fr26", 26, {0, {0}}, 0, 0 },
+ { "fr27", 27, {0, {0}}, 0, 0 },
+ { "fr28", 28, {0, {0}}, 0, 0 },
+ { "fr29", 29, {0, {0}}, 0, 0 },
+ { "fr30", 30, {0, {0}}, 0, 0 },
+ { "fr31", 31, {0, {0}}, 0, 0 },
+ { "fr32", 32, {0, {0}}, 0, 0 },
+ { "fr33", 33, {0, {0}}, 0, 0 },
+ { "fr34", 34, {0, {0}}, 0, 0 },
+ { "fr35", 35, {0, {0}}, 0, 0 },
+ { "fr36", 36, {0, {0}}, 0, 0 },
+ { "fr37", 37, {0, {0}}, 0, 0 },
+ { "fr38", 38, {0, {0}}, 0, 0 },
+ { "fr39", 39, {0, {0}}, 0, 0 },
+ { "fr40", 40, {0, {0}}, 0, 0 },
+ { "fr41", 41, {0, {0}}, 0, 0 },
+ { "fr42", 42, {0, {0}}, 0, 0 },
+ { "fr43", 43, {0, {0}}, 0, 0 },
+ { "fr44", 44, {0, {0}}, 0, 0 },
+ { "fr45", 45, {0, {0}}, 0, 0 },
+ { "fr46", 46, {0, {0}}, 0, 0 },
+ { "fr47", 47, {0, {0}}, 0, 0 },
+ { "fr48", 48, {0, {0}}, 0, 0 },
+ { "fr49", 49, {0, {0}}, 0, 0 },
+ { "fr50", 50, {0, {0}}, 0, 0 },
+ { "fr51", 51, {0, {0}}, 0, 0 },
+ { "fr52", 52, {0, {0}}, 0, 0 },
+ { "fr53", 53, {0, {0}}, 0, 0 },
+ { "fr54", 54, {0, {0}}, 0, 0 },
+ { "fr55", 55, {0, {0}}, 0, 0 },
+ { "fr56", 56, {0, {0}}, 0, 0 },
+ { "fr57", 57, {0, {0}}, 0, 0 },
+ { "fr58", 58, {0, {0}}, 0, 0 },
+ { "fr59", 59, {0, {0}}, 0, 0 },
+ { "fr60", 60, {0, {0}}, 0, 0 },
+ { "fr61", 61, {0, {0}}, 0, 0 },
+ { "fr62", 62, {0, {0}}, 0, 0 },
+ { "fr63", 63, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD sh_cgen_opval_h_fr =
+{
+ & sh_cgen_opval_h_fr_entries[0],
+ 64,
+ 0, 0, 0, 0
+};
+
+static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fp_entries[] =
+{
+ { "fp0", 0, {0, {0}}, 0, 0 },
+ { "fp1", 1, {0, {0}}, 0, 0 },
+ { "fp2", 2, {0, {0}}, 0, 0 },
+ { "fp3", 3, {0, {0}}, 0, 0 },
+ { "fp4", 4, {0, {0}}, 0, 0 },
+ { "fp5", 5, {0, {0}}, 0, 0 },
+ { "fp6", 6, {0, {0}}, 0, 0 },
+ { "fp7", 7, {0, {0}}, 0, 0 },
+ { "fp8", 8, {0, {0}}, 0, 0 },
+ { "fp9", 9, {0, {0}}, 0, 0 },
+ { "fp10", 10, {0, {0}}, 0, 0 },
+ { "fp11", 11, {0, {0}}, 0, 0 },
+ { "fp12", 12, {0, {0}}, 0, 0 },
+ { "fp13", 13, {0, {0}}, 0, 0 },
+ { "fp14", 14, {0, {0}}, 0, 0 },
+ { "fp15", 15, {0, {0}}, 0, 0 },
+ { "fp16", 16, {0, {0}}, 0, 0 },
+ { "fp17", 17, {0, {0}}, 0, 0 },
+ { "fp18", 18, {0, {0}}, 0, 0 },
+ { "fp19", 19, {0, {0}}, 0, 0 },
+ { "fp20", 20, {0, {0}}, 0, 0 },
+ { "fp21", 21, {0, {0}}, 0, 0 },
+ { "fp22", 22, {0, {0}}, 0, 0 },
+ { "fp23", 23, {0, {0}}, 0, 0 },
+ { "fp24", 24, {0, {0}}, 0, 0 },
+ { "fp25", 25, {0, {0}}, 0, 0 },
+ { "fp26", 26, {0, {0}}, 0, 0 },
+ { "fp27", 27, {0, {0}}, 0, 0 },
+ { "fp28", 28, {0, {0}}, 0, 0 },
+ { "fp29", 29, {0, {0}}, 0, 0 },
+ { "fp30", 30, {0, {0}}, 0, 0 },
+ { "fp31", 31, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD sh_cgen_opval_h_fp =
+{
+ & sh_cgen_opval_h_fp_entries[0],
+ 32,
+ 0, 0, 0, 0
+};
+
+static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fv_entries[] =
+{
+ { "fv0", 0, {0, {0}}, 0, 0 },
+ { "fv1", 1, {0, {0}}, 0, 0 },
+ { "fv2", 2, {0, {0}}, 0, 0 },
+ { "fv3", 3, {0, {0}}, 0, 0 },
+ { "fv4", 4, {0, {0}}, 0, 0 },
+ { "fv5", 5, {0, {0}}, 0, 0 },
+ { "fv6", 6, {0, {0}}, 0, 0 },
+ { "fv7", 7, {0, {0}}, 0, 0 },
+ { "fv8", 8, {0, {0}}, 0, 0 },
+ { "fv9", 9, {0, {0}}, 0, 0 },
+ { "fv10", 10, {0, {0}}, 0, 0 },
+ { "fv11", 11, {0, {0}}, 0, 0 },
+ { "fv12", 12, {0, {0}}, 0, 0 },
+ { "fv13", 13, {0, {0}}, 0, 0 },
+ { "fv14", 14, {0, {0}}, 0, 0 },
+ { "fv15", 15, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD sh_cgen_opval_h_fv =
+{
+ & sh_cgen_opval_h_fv_entries[0],
+ 16,
+ 0, 0, 0, 0
+};
+
+static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fmtx_entries[] =
+{
+ { "mtrx0", 0, {0, {0}}, 0, 0 },
+ { "mtrx1", 1, {0, {0}}, 0, 0 },
+ { "mtrx2", 2, {0, {0}}, 0, 0 },
+ { "mtrx3", 3, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD sh_cgen_opval_h_fmtx =
+{
+ & sh_cgen_opval_h_fmtx_entries[0],
+ 4,
+ 0, 0, 0, 0
+};
+
+static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_dr_entries[] =
+{
+ { "dr0", 0, {0, {0}}, 0, 0 },
+ { "dr1", 1, {0, {0}}, 0, 0 },
+ { "dr2", 2, {0, {0}}, 0, 0 },
+ { "dr3", 3, {0, {0}}, 0, 0 },
+ { "dr4", 4, {0, {0}}, 0, 0 },
+ { "dr5", 5, {0, {0}}, 0, 0 },
+ { "dr6", 6, {0, {0}}, 0, 0 },
+ { "dr7", 7, {0, {0}}, 0, 0 },
+ { "dr8", 8, {0, {0}}, 0, 0 },
+ { "dr9", 9, {0, {0}}, 0, 0 },
+ { "dr10", 10, {0, {0}}, 0, 0 },
+ { "dr11", 11, {0, {0}}, 0, 0 },
+ { "dr12", 12, {0, {0}}, 0, 0 },
+ { "dr13", 13, {0, {0}}, 0, 0 },
+ { "dr14", 14, {0, {0}}, 0, 0 },
+ { "dr15", 15, {0, {0}}, 0, 0 },
+ { "dr16", 16, {0, {0}}, 0, 0 },
+ { "dr17", 17, {0, {0}}, 0, 0 },
+ { "dr18", 18, {0, {0}}, 0, 0 },
+ { "dr19", 19, {0, {0}}, 0, 0 },
+ { "dr20", 20, {0, {0}}, 0, 0 },
+ { "dr21", 21, {0, {0}}, 0, 0 },
+ { "dr22", 22, {0, {0}}, 0, 0 },
+ { "dr23", 23, {0, {0}}, 0, 0 },
+ { "dr24", 24, {0, {0}}, 0, 0 },
+ { "dr25", 25, {0, {0}}, 0, 0 },
+ { "dr26", 26, {0, {0}}, 0, 0 },
+ { "dr27", 27, {0, {0}}, 0, 0 },
+ { "dr28", 28, {0, {0}}, 0, 0 },
+ { "dr29", 29, {0, {0}}, 0, 0 },
+ { "dr30", 30, {0, {0}}, 0, 0 },
+ { "dr31", 31, {0, {0}}, 0, 0 },
+ { "dr32", 32, {0, {0}}, 0, 0 },
+ { "dr33", 33, {0, {0}}, 0, 0 },
+ { "dr34", 34, {0, {0}}, 0, 0 },
+ { "dr35", 35, {0, {0}}, 0, 0 },
+ { "dr36", 36, {0, {0}}, 0, 0 },
+ { "dr37", 37, {0, {0}}, 0, 0 },
+ { "dr38", 38, {0, {0}}, 0, 0 },
+ { "dr39", 39, {0, {0}}, 0, 0 },
+ { "dr40", 40, {0, {0}}, 0, 0 },
+ { "dr41", 41, {0, {0}}, 0, 0 },
+ { "dr42", 42, {0, {0}}, 0, 0 },
+ { "dr43", 43, {0, {0}}, 0, 0 },
+ { "dr44", 44, {0, {0}}, 0, 0 },
+ { "dr45", 45, {0, {0}}, 0, 0 },
+ { "dr46", 46, {0, {0}}, 0, 0 },
+ { "dr47", 47, {0, {0}}, 0, 0 },
+ { "dr48", 48, {0, {0}}, 0, 0 },
+ { "dr49", 49, {0, {0}}, 0, 0 },
+ { "dr50", 50, {0, {0}}, 0, 0 },
+ { "dr51", 51, {0, {0}}, 0, 0 },
+ { "dr52", 52, {0, {0}}, 0, 0 },
+ { "dr53", 53, {0, {0}}, 0, 0 },
+ { "dr54", 54, {0, {0}}, 0, 0 },
+ { "dr55", 55, {0, {0}}, 0, 0 },
+ { "dr56", 56, {0, {0}}, 0, 0 },
+ { "dr57", 57, {0, {0}}, 0, 0 },
+ { "dr58", 58, {0, {0}}, 0, 0 },
+ { "dr59", 59, {0, {0}}, 0, 0 },
+ { "dr60", 60, {0, {0}}, 0, 0 },
+ { "dr61", 61, {0, {0}}, 0, 0 },
+ { "dr62", 62, {0, {0}}, 0, 0 },
+ { "dr63", 63, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD sh_cgen_opval_h_dr =
+{
+ & sh_cgen_opval_h_dr_entries[0],
+ 64,
+ 0, 0, 0, 0
+};
+
+static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_tr_entries[] =
+{
+ { "tr0", 0, {0, {0}}, 0, 0 },
+ { "tr1", 1, {0, {0}}, 0, 0 },
+ { "tr2", 2, {0, {0}}, 0, 0 },
+ { "tr3", 3, {0, {0}}, 0, 0 },
+ { "tr4", 4, {0, {0}}, 0, 0 },
+ { "tr5", 5, {0, {0}}, 0, 0 },
+ { "tr6", 6, {0, {0}}, 0, 0 },
+ { "tr7", 7, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD sh_cgen_opval_h_tr =
+{
+ & sh_cgen_opval_h_tr_entries[0],
+ 8,
+ 0, 0, 0, 0
+};
+
+static CGEN_KEYWORD_ENTRY sh_cgen_opval_h_fvc_entries[] =
+{
+ { "fv0", 0, {0, {0}}, 0, 0 },
+ { "fv4", 4, {0, {0}}, 0, 0 },
+ { "fv8", 8, {0, {0}}, 0, 0 },
+ { "fv12", 12, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD sh_cgen_opval_h_fvc =
+{
+ & sh_cgen_opval_h_fvc_entries[0],
+ 4,
+ 0, 0, 0, 0
+};
+
+
+/* The hardware table. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_HW_##a)
+#else
+#define A(a) (1 << CGEN_HW_/**/a)
+#endif
+
+const CGEN_HW_ENTRY sh_cgen_hw_table[] =
+{
+ { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE) } } },
+ { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_gr, { 0, { (1<<MACH_BASE) } } },
+ { "h-grc", HW_H_GRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_grc, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_cr, { 0, { (1<<MACH_BASE) } } },
+ { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-fpscr", HW_H_FPSCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-frbit", HW_H_FRBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-szbit", HW_H_SZBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-prbit", HW_H_PRBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-mbit", HW_H_MBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-qbit", HW_H_QBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fr, { 0, { (1<<MACH_BASE) } } },
+ { "h-fp", HW_H_FP, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fp, { 0, { (1<<MACH_BASE) } } },
+ { "h-fv", HW_H_FV, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fv, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-fmtx", HW_H_FMTX, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fmtx, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_dr, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-tr", HW_H_TR, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_tr, { 0, { (1<<MACH_BASE) } } },
+ { "h-endian", HW_H_ENDIAN, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-ism", HW_H_ISM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+ { "h-frc", HW_H_FRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_frc_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-drc", HW_H_DRC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_drc_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-xf", HW_H_XF, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_xf_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-xd", HW_H_XD, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_frc_names, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-fvc", HW_H_FVC, CGEN_ASM_KEYWORD, (PTR) & sh_cgen_opval_h_fvc, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-fpccr", HW_H_FPCCR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-gbr", HW_H_GBR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-pr", HW_H_PR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-macl", HW_H_MACL, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-mach", HW_H_MACH, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
+};
+
+#undef A
+
+
+/* The instruction field table. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_IFLD_##a)
+#else
+#define A(a) (1 << CGEN_IFLD_/**/a)
+#endif
+
+const CGEN_IFLD sh_cgen_ifld_table[] =
+{
+ { SH_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_OP4, "f-op4", 0, 16, 15, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_OP8, "f-op8", 0, 16, 15, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_OP16, "f-op16", 0, 16, 15, 16, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_SUB4, "f-sub4", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_SUB8, "f-sub8", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_SUB10, "f-sub10", 0, 16, 9, 10, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_RN, "f-rn", 0, 16, 11, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_RM, "f-rm", 0, 16, 7, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_8_1, "f-8-1", 0, 16, 8, 1, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_DISP8, "f-disp8", 0, 16, 7, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_DISP12, "f-disp12", 0, 16, 11, 12, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_IMM8, "f-imm8", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_IMM4, "f-imm4", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_IMM4X2, "f-imm4x2", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_IMM4X4, "f-imm4x4", 0, 16, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_IMM8X2, "f-imm8x2", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_IMM8X4, "f-imm8x4", 0, 16, 7, 8, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_DN, "f-dn", 0, 16, 11, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_DM, "f-dm", 0, 16, 7, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_VN, "f-vn", 0, 16, 11, 2, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_VM, "f-vm", 0, 16, 9, 2, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_XN, "f-xn", 0, 16, 11, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_XM, "f-xm", 0, 16, 7, 3, { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+ { SH_F_OP, "f-op", 0, 32, 31, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_EXT, "f-ext", 0, 32, 19, 4, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_RSVD, "f-rsvd", 0, 32, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_LEFT, "f-left", 0, 32, 25, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_RIGHT, "f-right", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_DEST, "f-dest", 0, 32, 9, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_TRA, "f-tra", 0, 32, 6, 3, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_TRB, "f-trb", 0, 32, 22, 3, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_LIKELY, "f-likely", 0, 32, 9, 1, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_25, "f-25", 0, 32, 25, 3, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_8_2, "f-8-2", 0, 32, 8, 2, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_IMM6, "f-imm6", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_IMM10, "f-imm10", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_IMM16, "f-imm16", 0, 32, 25, 16, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_UIMM6, "f-uimm6", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_UIMM16, "f-uimm16", 0, 32, 25, 16, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_DISP6, "f-disp6", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_DISP6X32, "f-disp6x32", 0, 32, 15, 6, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_DISP10, "f-disp10", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_DISP10X8, "f-disp10x8", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_DISP10X4, "f-disp10x4", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_DISP10X2, "f-disp10x2", 0, 32, 19, 10, { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { SH_F_DISP16, "f-disp16", 0, 32, 25, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { 0, 0, 0, 0, 0, 0, {0, {0}} }
+};
+
+#undef A
+
+
+/* The operand table. */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_OPERAND_##a)
+#else
+#define A(a) (1 << CGEN_OPERAND_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) SH_OPERAND_##op
+#else
+#define OPERAND(op) SH_OPERAND_/**/op
+#endif
+
+const CGEN_OPERAND sh_cgen_operand_table[] =
+{
+/* pc: program counter */
+ { "pc", SH_OPERAND_PC, HW_H_PC, 0, 0,
+ { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* endian: Endian mode */
+ { "endian", SH_OPERAND_ENDIAN, HW_H_ENDIAN, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT)|(1<<ISA_MEDIA) } } },
+/* ism: Instruction set mode */
+ { "ism", SH_OPERAND_ISM, HW_H_ISM, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT)|(1<<ISA_MEDIA) } } },
+/* rm: Left general purpose register */
+ { "rm", SH_OPERAND_RM, HW_H_GRC, 7, 4,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* rn: Right general purpose register */
+ { "rn", SH_OPERAND_RN, HW_H_GRC, 11, 4,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* r0: Register 0 */
+ { "r0", SH_OPERAND_R0, HW_H_GRC, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* frn: Single precision register */
+ { "frn", SH_OPERAND_FRN, HW_H_FRC, 11, 4,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* frm: Single precision register */
+ { "frm", SH_OPERAND_FRM, HW_H_FRC, 7, 4,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* fvn: Left floating point vector */
+ { "fvn", SH_OPERAND_FVN, HW_H_FVC, 11, 2,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* fvm: Right floating point vector */
+ { "fvm", SH_OPERAND_FVM, HW_H_FVC, 9, 2,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* drn: Left double precision register */
+ { "drn", SH_OPERAND_DRN, HW_H_DRC, 11, 3,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* drm: Right double precision register */
+ { "drm", SH_OPERAND_DRM, HW_H_DRC, 7, 3,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* imm4: Immediate value (4 bits) */
+ { "imm4", SH_OPERAND_IMM4, HW_H_SINT, 3, 4,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* imm8: Immediate value (8 bits) */
+ { "imm8", SH_OPERAND_IMM8, HW_H_SINT, 7, 8,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* uimm8: Immediate value (8 bits unsigned) */
+ { "uimm8", SH_OPERAND_UIMM8, HW_H_UINT, 7, 8,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* imm4x2: Immediate value (4 bits, 2x scale) */
+ { "imm4x2", SH_OPERAND_IMM4X2, HW_H_UINT, 3, 4,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* imm4x4: Immediate value (4 bits, 4x scale) */
+ { "imm4x4", SH_OPERAND_IMM4X4, HW_H_UINT, 3, 4,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* imm8x2: Immediate value (8 bits, 2x scale) */
+ { "imm8x2", SH_OPERAND_IMM8X2, HW_H_UINT, 7, 8,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* imm8x4: Immediate value (8 bits, 4x scale) */
+ { "imm8x4", SH_OPERAND_IMM8X4, HW_H_UINT, 7, 8,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* disp8: Displacement (8 bits) */
+ { "disp8", SH_OPERAND_DISP8, HW_H_IADDR, 7, 8,
+ { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* disp12: Displacement (12 bits) */
+ { "disp12", SH_OPERAND_DISP12, HW_H_IADDR, 11, 12,
+ { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* rm64: Register m (64 bits) */
+ { "rm64", SH_OPERAND_RM64, HW_H_GR, 7, 4,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* rn64: Register n (64 bits) */
+ { "rn64", SH_OPERAND_RN64, HW_H_GR, 11, 4,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* gbr: Global base register */
+ { "gbr", SH_OPERAND_GBR, HW_H_GBR, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* pr: Procedure link register */
+ { "pr", SH_OPERAND_PR, HW_H_PR, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* fpscr: Floating point status/control register */
+ { "fpscr", SH_OPERAND_FPSCR, HW_H_FPCCR, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* tbit: Condition code flag */
+ { "tbit", SH_OPERAND_TBIT, HW_H_TBIT, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* sbit: Multiply-accumulate saturation flag */
+ { "sbit", SH_OPERAND_SBIT, HW_H_SBIT, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* mbit: Divide-step M flag */
+ { "mbit", SH_OPERAND_MBIT, HW_H_MBIT, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* qbit: Divide-step Q flag */
+ { "qbit", SH_OPERAND_QBIT, HW_H_QBIT, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* fpul: Floating point ??? */
+ { "fpul", SH_OPERAND_FPUL, HW_H_FR, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* frbit: Floating point register bank bit */
+ { "frbit", SH_OPERAND_FRBIT, HW_H_FRBIT, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* szbit: Floating point transfer size bit */
+ { "szbit", SH_OPERAND_SZBIT, HW_H_SZBIT, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* prbit: Floating point precision bit */
+ { "prbit", SH_OPERAND_PRBIT, HW_H_PRBIT, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* macl: Multiply-accumulate low register */
+ { "macl", SH_OPERAND_MACL, HW_H_MACL, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* mach: Multiply-accumulate high register */
+ { "mach", SH_OPERAND_MACH, HW_H_MACH, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* fsdm: bar */
+ { "fsdm", SH_OPERAND_FSDM, HW_H_FRC, 7, 4,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* fsdn: bar */
+ { "fsdn", SH_OPERAND_FSDN, HW_H_FRC, 11, 4,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } } },
+/* rm: Left general purpose reg */
+ { "rm", SH_OPERAND_RM, HW_H_GR, 25, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* rn: Right general purpose reg */
+ { "rn", SH_OPERAND_RN, HW_H_GR, 15, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* rd: Destination general purpose reg */
+ { "rd", SH_OPERAND_RD, HW_H_GR, 9, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* frg: Left single precision register */
+ { "frg", SH_OPERAND_FRG, HW_H_FR, 25, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* frh: Right single precision register */
+ { "frh", SH_OPERAND_FRH, HW_H_FR, 15, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* frf: Destination single precision reg */
+ { "frf", SH_OPERAND_FRF, HW_H_FR, 9, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* frgh: Single precision register pair */
+ { "frgh", SH_OPERAND_FRGH, HW_H_FR, 15, 12,
+ { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* fpf: Pair of single precision registers */
+ { "fpf", SH_OPERAND_FPF, HW_H_FP, 9, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* fvg: Left single precision vector */
+ { "fvg", SH_OPERAND_FVG, HW_H_FV, 25, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* fvh: Right single precision vector */
+ { "fvh", SH_OPERAND_FVH, HW_H_FV, 15, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* fvf: Destination single precision vector */
+ { "fvf", SH_OPERAND_FVF, HW_H_FV, 9, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* mtrxg: Left single precision matrix */
+ { "mtrxg", SH_OPERAND_MTRXG, HW_H_FMTX, 25, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* drg: Left double precision register */
+ { "drg", SH_OPERAND_DRG, HW_H_DR, 25, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* drh: Right double precision register */
+ { "drh", SH_OPERAND_DRH, HW_H_DR, 15, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* drf: Destination double precision reg */
+ { "drf", SH_OPERAND_DRF, HW_H_DR, 9, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* drgh: Double precision register pair */
+ { "drgh", SH_OPERAND_DRGH, HW_H_DR, 15, 12,
+ { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* fpscr: Floating point status register */
+ { "fpscr", SH_OPERAND_FPSCR, HW_H_FPSCR, 0, 0,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* crj: Control register j */
+ { "crj", SH_OPERAND_CRJ, HW_H_CR, 9, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* crk: Control register k */
+ { "crk", SH_OPERAND_CRK, HW_H_CR, 25, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* tra: Target register a */
+ { "tra", SH_OPERAND_TRA, HW_H_TR, 6, 3,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* trb: Target register b */
+ { "trb", SH_OPERAND_TRB, HW_H_TR, 22, 3,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* disp6: Displacement (6 bits) */
+ { "disp6", SH_OPERAND_DISP6, HW_H_SINT, 15, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* disp6x32: Displacement (6 bits, scale 32) */
+ { "disp6x32", SH_OPERAND_DISP6X32, HW_H_SINT, 15, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* disp10: Displacement (10 bits) */
+ { "disp10", SH_OPERAND_DISP10, HW_H_SINT, 19, 10,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* disp10x2: Displacement (10 bits, scale 2) */
+ { "disp10x2", SH_OPERAND_DISP10X2, HW_H_SINT, 19, 10,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* disp10x4: Displacement (10 bits, scale 4) */
+ { "disp10x4", SH_OPERAND_DISP10X4, HW_H_SINT, 19, 10,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* disp10x8: Displacement (10 bits, scale 8) */
+ { "disp10x8", SH_OPERAND_DISP10X8, HW_H_SINT, 19, 10,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* disp16: Displacement (16 bits) */
+ { "disp16", SH_OPERAND_DISP16, HW_H_SINT, 25, 16,
+ { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* imm6: Immediate (6 bits) */
+ { "imm6", SH_OPERAND_IMM6, HW_H_SINT, 15, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* imm10: Immediate (10 bits) */
+ { "imm10", SH_OPERAND_IMM10, HW_H_SINT, 19, 10,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* imm16: Immediate (16 bits) */
+ { "imm16", SH_OPERAND_IMM16, HW_H_SINT, 25, 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* uimm6: Immediate (6 bits) */
+ { "uimm6", SH_OPERAND_UIMM6, HW_H_UINT, 15, 6,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* uimm16: Unsigned immediate (16 bits) */
+ { "uimm16", SH_OPERAND_UIMM16, HW_H_UINT, 25, 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+/* likely: Likely branch? */
+ { "likely", SH_OPERAND_LIKELY, HW_H_UINT, 9, 1,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } } },
+ { 0, 0, 0, 0, 0, {0, {0}} }
+};
+
+#undef A
+
+
+/* The instruction table. */
+
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+
+static const CGEN_IBASE sh_cgen_insn_table[MAX_INSNS] =
+{
+ /* Special null first entry.
+ A `num' value of zero is thus invalid.
+ Also, the special `invalid' insn resides here. */
+ { 0, 0, 0, 0, {0, {0}} },
+/* add $rm, $rn */
+ {
+ SH_INSN_ADD_COMPACT, "add-compact", "add", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* add #$imm8, $rn */
+ {
+ SH_INSN_ADDI_COMPACT, "addi-compact", "add", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* addc $rm, $rn */
+ {
+ SH_INSN_ADDC_COMPACT, "addc-compact", "addc", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* addv $rm, $rn */
+ {
+ SH_INSN_ADDV_COMPACT, "addv-compact", "addv", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* and $rm64, $rn64 */
+ {
+ SH_INSN_AND_COMPACT, "and-compact", "and", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* and #$uimm8, r0 */
+ {
+ SH_INSN_ANDI_COMPACT, "andi-compact", "and", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* and.b #$imm8, @(r0, gbr) */
+ {
+ SH_INSN_ANDB_COMPACT, "andb-compact", "and.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* bf $disp8 */
+ {
+ SH_INSN_BF_COMPACT, "bf-compact", "bf", 16,
+ { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* bf/s $disp8 */
+ {
+ SH_INSN_BFS_COMPACT, "bfs-compact", "bf/s", 16,
+ { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* bra $disp12 */
+ {
+ SH_INSN_BRA_COMPACT, "bra-compact", "bra", 16,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* braf $rn */
+ {
+ SH_INSN_BRAF_COMPACT, "braf-compact", "braf", 16,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* brk */
+ {
+ SH_INSN_BRK_COMPACT, "brk-compact", "brk", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* bsr $disp12 */
+ {
+ SH_INSN_BSR_COMPACT, "bsr-compact", "bsr", 16,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* bsrf $rn */
+ {
+ SH_INSN_BSRF_COMPACT, "bsrf-compact", "bsrf", 16,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* bt $disp8 */
+ {
+ SH_INSN_BT_COMPACT, "bt-compact", "bt", 16,
+ { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* bt/s $disp8 */
+ {
+ SH_INSN_BTS_COMPACT, "bts-compact", "bt/s", 16,
+ { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* clrmac */
+ {
+ SH_INSN_CLRMAC_COMPACT, "clrmac-compact", "clrmac", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* clrs */
+ {
+ SH_INSN_CLRS_COMPACT, "clrs-compact", "clrs", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* clrt */
+ {
+ SH_INSN_CLRT_COMPACT, "clrt-compact", "clrt", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* cmp/eq $rm, $rn */
+ {
+ SH_INSN_CMPEQ_COMPACT, "cmpeq-compact", "cmp/eq", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* cmp/eq #$imm8, r0 */
+ {
+ SH_INSN_CMPEQI_COMPACT, "cmpeqi-compact", "cmp/eq", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* cmp/ge $rm, $rn */
+ {
+ SH_INSN_CMPGE_COMPACT, "cmpge-compact", "cmp/ge", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* cmp/gt $rm, $rn */
+ {
+ SH_INSN_CMPGT_COMPACT, "cmpgt-compact", "cmp/gt", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* cmp/hi $rm, $rn */
+ {
+ SH_INSN_CMPHI_COMPACT, "cmphi-compact", "cmp/hi", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* cmp/hs $rm, $rn */
+ {
+ SH_INSN_CMPHS_COMPACT, "cmphs-compact", "cmp/hs", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* cmp/pl $rn */
+ {
+ SH_INSN_CMPPL_COMPACT, "cmppl-compact", "cmp/pl", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* cmp/pz $rn */
+ {
+ SH_INSN_CMPPZ_COMPACT, "cmppz-compact", "cmp/pz", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* cmp/str $rm, $rn */
+ {
+ SH_INSN_CMPSTR_COMPACT, "cmpstr-compact", "cmp/str", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* div0s $rm, $rn */
+ {
+ SH_INSN_DIV0S_COMPACT, "div0s-compact", "div0s", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* div0u */
+ {
+ SH_INSN_DIV0U_COMPACT, "div0u-compact", "div0u", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* div1 $rm, $rn */
+ {
+ SH_INSN_DIV1_COMPACT, "div1-compact", "div1", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* dmuls.l $rm, $rn */
+ {
+ SH_INSN_DMULSL_COMPACT, "dmulsl-compact", "dmuls.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* dmulu.l $rm, $rn */
+ {
+ SH_INSN_DMULUL_COMPACT, "dmulul-compact", "dmulu.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* dt $rn */
+ {
+ SH_INSN_DT_COMPACT, "dt-compact", "dt", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* exts.b $rm, $rn */
+ {
+ SH_INSN_EXTSB_COMPACT, "extsb-compact", "exts.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* exts.w $rm, $rn */
+ {
+ SH_INSN_EXTSW_COMPACT, "extsw-compact", "exts.w", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* extu.b $rm, $rn */
+ {
+ SH_INSN_EXTUB_COMPACT, "extub-compact", "extu.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* extu.w $rm, $rn */
+ {
+ SH_INSN_EXTUW_COMPACT, "extuw-compact", "extu.w", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fabs $fsdn */
+ {
+ SH_INSN_FABS_COMPACT, "fabs-compact", "fabs", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fadd $fsdm, $fsdn */
+ {
+ SH_INSN_FADD_COMPACT, "fadd-compact", "fadd", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fcmp/eq $fsdm, $fsdn */
+ {
+ SH_INSN_FCMPEQ_COMPACT, "fcmpeq-compact", "fcmp/eq", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fcmp/gt $fsdm, $fsdn */
+ {
+ SH_INSN_FCMPGT_COMPACT, "fcmpgt-compact", "fcmp/gt", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fcnvds $drn, fpul */
+ {
+ SH_INSN_FCNVDS_COMPACT, "fcnvds-compact", "fcnvds", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fcnvsd fpul, $drn */
+ {
+ SH_INSN_FCNVSD_COMPACT, "fcnvsd-compact", "fcnvsd", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fdiv $fsdm, $fsdn */
+ {
+ SH_INSN_FDIV_COMPACT, "fdiv-compact", "fdiv", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fipr $fvm, $fvn */
+ {
+ SH_INSN_FIPR_COMPACT, "fipr-compact", "fipr", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* flds $frn */
+ {
+ SH_INSN_FLDS_COMPACT, "flds-compact", "flds", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fldi0 $frn */
+ {
+ SH_INSN_FLDI0_COMPACT, "fldi0-compact", "fldi0", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fldi1 $frn */
+ {
+ SH_INSN_FLDI1_COMPACT, "fldi1-compact", "fldi1", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* float fpul, $fsdn */
+ {
+ SH_INSN_FLOAT_COMPACT, "float-compact", "float", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fmac fr0, $frm, $frn */
+ {
+ SH_INSN_FMAC_COMPACT, "fmac-compact", "fmac", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fmov $frm, $frn */
+ {
+ SH_INSN_FMOV1_COMPACT, "fmov1-compact", "fmov", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fmov @$rm, $frn */
+ {
+ SH_INSN_FMOV2_COMPACT, "fmov2-compact", "fmov", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fmov @${rm}+, frn */
+ {
+ SH_INSN_FMOV3_COMPACT, "fmov3-compact", "fmov", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fmov @(r0, $rm), $frn */
+ {
+ SH_INSN_FMOV4_COMPACT, "fmov4-compact", "fmov", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fmov $frm, @$rn */
+ {
+ SH_INSN_FMOV5_COMPACT, "fmov5-compact", "fmov", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fmov $frm, @-$rn */
+ {
+ SH_INSN_FMOV6_COMPACT, "fmov6-compact", "fmov", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fmov $frm, @(r0, $rn) */
+ {
+ SH_INSN_FMOV7_COMPACT, "fmov7-compact", "fmov", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fmul $fsdm, $fsdn */
+ {
+ SH_INSN_FMUL_COMPACT, "fmul-compact", "fmul", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fneg $fsdn */
+ {
+ SH_INSN_FNEG_COMPACT, "fneg-compact", "fneg", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* frchg */
+ {
+ SH_INSN_FRCHG_COMPACT, "frchg-compact", "frchg", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fschg */
+ {
+ SH_INSN_FSCHG_COMPACT, "fschg-compact", "fschg", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fsqrt $fsdn */
+ {
+ SH_INSN_FSQRT_COMPACT, "fsqrt-compact", "fsqrt", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fsts fpul, $frn */
+ {
+ SH_INSN_FSTS_COMPACT, "fsts-compact", "fsts", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* fsub $fsdm, $fsdn */
+ {
+ SH_INSN_FSUB_COMPACT, "fsub-compact", "fsub", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* ftrc $fsdn, fpul */
+ {
+ SH_INSN_FTRC_COMPACT, "ftrc-compact", "ftrc", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* ftrv xmtrx, $fvn */
+ {
+ SH_INSN_FTRV_COMPACT, "ftrv-compact", "ftrv", 16,
+ { 0|A(FP_INSN), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* jmp @$rn */
+ {
+ SH_INSN_JMP_COMPACT, "jmp-compact", "jmp", 16,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* jsr @$rn */
+ {
+ SH_INSN_JSR_COMPACT, "jsr-compact", "jsr", 16,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* ldc $rn, gbr */
+ {
+ SH_INSN_LDC_COMPACT, "ldc-compact", "ldc", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* ldc.l @${rn}+, gbr */
+ {
+ SH_INSN_LDCL_COMPACT, "ldcl-compact", "ldc.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* lds $rn, fpscr */
+ {
+ SH_INSN_LDS_FPSCR_COMPACT, "lds-fpscr-compact", "lds", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* lds.l @${rn}+, fpscr */
+ {
+ SH_INSN_LDSL_FPSCR_COMPACT, "ldsl-fpscr-compact", "lds.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* lds $rn, fpul */
+ {
+ SH_INSN_LDS_FPUL_COMPACT, "lds-fpul-compact", "lds", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* lds.l @${rn}+, fpul */
+ {
+ SH_INSN_LDSL_FPUL_COMPACT, "ldsl-fpul-compact", "lds.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* lds $rn, mach */
+ {
+ SH_INSN_LDS_MACH_COMPACT, "lds-mach-compact", "lds", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* lds.l @${rn}+, mach */
+ {
+ SH_INSN_LDSL_MACH_COMPACT, "ldsl-mach-compact", "lds.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* lds $rn, macl */
+ {
+ SH_INSN_LDS_MACL_COMPACT, "lds-macl-compact", "lds", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* lds.l @${rn}+, macl */
+ {
+ SH_INSN_LDSL_MACL_COMPACT, "ldsl-macl-compact", "lds.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* lds $rn, pr */
+ {
+ SH_INSN_LDS_PR_COMPACT, "lds-pr-compact", "lds", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* lds.l @${rn}+, pr */
+ {
+ SH_INSN_LDSL_PR_COMPACT, "ldsl-pr-compact", "lds.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mac.l @${rm}+, @${rn}+ */
+ {
+ SH_INSN_MACL_COMPACT, "macl-compact", "mac.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mac.w @${rm}+, @${rn}+ */
+ {
+ SH_INSN_MACW_COMPACT, "macw-compact", "mac.w", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov $rm64, $rn64 */
+ {
+ SH_INSN_MOV_COMPACT, "mov-compact", "mov", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov #$imm8, $rn */
+ {
+ SH_INSN_MOVI_COMPACT, "movi-compact", "mov", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.b $rm, @$rn */
+ {
+ SH_INSN_MOVB1_COMPACT, "movb1-compact", "mov.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.b $rm, @-$rn */
+ {
+ SH_INSN_MOVB2_COMPACT, "movb2-compact", "mov.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.b $rm, @(r0,$rn) */
+ {
+ SH_INSN_MOVB3_COMPACT, "movb3-compact", "mov.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.b r0, @($imm8, gbr) */
+ {
+ SH_INSN_MOVB4_COMPACT, "movb4-compact", "mov.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.b r0, @($imm4, $rm) */
+ {
+ SH_INSN_MOVB5_COMPACT, "movb5-compact", "mov.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.b @$rm, $rn */
+ {
+ SH_INSN_MOVB6_COMPACT, "movb6-compact", "mov.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.b @${rm}+, $rn */
+ {
+ SH_INSN_MOVB7_COMPACT, "movb7-compact", "mov.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.b @(r0, $rm), $rn */
+ {
+ SH_INSN_MOVB8_COMPACT, "movb8-compact", "mov.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.b @($imm8, gbr), r0 */
+ {
+ SH_INSN_MOVB9_COMPACT, "movb9-compact", "mov.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.b @($imm4, $rm), r0 */
+ {
+ SH_INSN_MOVB10_COMPACT, "movb10-compact", "mov.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.l $rm, @$rn */
+ {
+ SH_INSN_MOVL1_COMPACT, "movl1-compact", "mov.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.l $rm, @-$rn */
+ {
+ SH_INSN_MOVL2_COMPACT, "movl2-compact", "mov.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.l $rm, @(r0, $rn) */
+ {
+ SH_INSN_MOVL3_COMPACT, "movl3-compact", "mov.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.l r0, @($imm8x4, gbr) */
+ {
+ SH_INSN_MOVL4_COMPACT, "movl4-compact", "mov.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.l $rm, @($imm4x4, $rn) */
+ {
+ SH_INSN_MOVL5_COMPACT, "movl5-compact", "mov.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.l @$rm, $rn */
+ {
+ SH_INSN_MOVL6_COMPACT, "movl6-compact", "mov.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.l @${rm}+, $rn */
+ {
+ SH_INSN_MOVL7_COMPACT, "movl7-compact", "mov.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.l @(r0, $rm), $rn */
+ {
+ SH_INSN_MOVL8_COMPACT, "movl8-compact", "mov.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.l @($imm8x4, gbr), r0 */
+ {
+ SH_INSN_MOVL9_COMPACT, "movl9-compact", "mov.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.l @($imm8x4, pc), $rn */
+ {
+ SH_INSN_MOVL10_COMPACT, "movl10-compact", "mov.l", 16,
+ { 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.l @($imm4x4, $rm), $rn */
+ {
+ SH_INSN_MOVL11_COMPACT, "movl11-compact", "mov.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.w $rm, @$rn */
+ {
+ SH_INSN_MOVW1_COMPACT, "movw1-compact", "mov.w", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.w $rm, @-$rn */
+ {
+ SH_INSN_MOVW2_COMPACT, "movw2-compact", "mov.w", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.w $rm, @(r0, $rn) */
+ {
+ SH_INSN_MOVW3_COMPACT, "movw3-compact", "mov.w", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.w r0, @($imm8x2, gbr) */
+ {
+ SH_INSN_MOVW4_COMPACT, "movw4-compact", "mov.w", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.w r0, @($imm4x2, $rn) */
+ {
+ SH_INSN_MOVW5_COMPACT, "movw5-compact", "mov.w", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.w @$rm, $rn */
+ {
+ SH_INSN_MOVW6_COMPACT, "movw6-compact", "mov.w", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.w @${rm}+, $rn */
+ {
+ SH_INSN_MOVW7_COMPACT, "movw7-compact", "mov.w", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.w @(r0, $rm), $rn */
+ {
+ SH_INSN_MOVW8_COMPACT, "movw8-compact", "mov.w", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.w @($imm8x2, gbr), r0 */
+ {
+ SH_INSN_MOVW9_COMPACT, "movw9-compact", "mov.w", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.w @($imm8x2, pc), $rn */
+ {
+ SH_INSN_MOVW10_COMPACT, "movw10-compact", "mov.w", 16,
+ { 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mov.w @($imm4x2, $rm), r0 */
+ {
+ SH_INSN_MOVW11_COMPACT, "movw11-compact", "mov.w", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mova @($imm8x4, pc), r0 */
+ {
+ SH_INSN_MOVA_COMPACT, "mova-compact", "mova", 16,
+ { 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* movca.l r0, @$rn */
+ {
+ SH_INSN_MOVCAL_COMPACT, "movcal-compact", "movca.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* movt $rn */
+ {
+ SH_INSN_MOVT_COMPACT, "movt-compact", "movt", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mul.l $rm, $rn */
+ {
+ SH_INSN_MULL_COMPACT, "mull-compact", "mul.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* muls.w $rm, $rn */
+ {
+ SH_INSN_MULSW_COMPACT, "mulsw-compact", "muls.w", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* mulu.w $rm, $rn */
+ {
+ SH_INSN_MULUW_COMPACT, "muluw-compact", "mulu.w", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* neg $rm, $rn */
+ {
+ SH_INSN_NEG_COMPACT, "neg-compact", "neg", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* negc $rm, $rn */
+ {
+ SH_INSN_NEGC_COMPACT, "negc-compact", "negc", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* nop */
+ {
+ SH_INSN_NOP_COMPACT, "nop-compact", "nop", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* not $rm64, $rn64 */
+ {
+ SH_INSN_NOT_COMPACT, "not-compact", "not", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* ocbi @$rn */
+ {
+ SH_INSN_OCBI_COMPACT, "ocbi-compact", "ocbi", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* ocbp @$rn */
+ {
+ SH_INSN_OCBP_COMPACT, "ocbp-compact", "ocbp", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* ocbwb @$rn */
+ {
+ SH_INSN_OCBWB_COMPACT, "ocbwb-compact", "ocbwb", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* or $rm64, $rn64 */
+ {
+ SH_INSN_OR_COMPACT, "or-compact", "or", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* or #$uimm8, r0 */
+ {
+ SH_INSN_ORI_COMPACT, "ori-compact", "or", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* or.b #$imm8, @(r0, gbr) */
+ {
+ SH_INSN_ORB_COMPACT, "orb-compact", "or.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* pref @$rn */
+ {
+ SH_INSN_PREF_COMPACT, "pref-compact", "pref", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* rotcl $rn */
+ {
+ SH_INSN_ROTCL_COMPACT, "rotcl-compact", "rotcl", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* rotcr $rn */
+ {
+ SH_INSN_ROTCR_COMPACT, "rotcr-compact", "rotcr", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* rotl $rn */
+ {
+ SH_INSN_ROTL_COMPACT, "rotl-compact", "rotl", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* rotr $rn */
+ {
+ SH_INSN_ROTR_COMPACT, "rotr-compact", "rotr", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* rts */
+ {
+ SH_INSN_RTS_COMPACT, "rts-compact", "rts", 16,
+ { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* sets */
+ {
+ SH_INSN_SETS_COMPACT, "sets-compact", "sets", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* sett */
+ {
+ SH_INSN_SETT_COMPACT, "sett-compact", "sett", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* shad $rm, $rn */
+ {
+ SH_INSN_SHAD_COMPACT, "shad-compact", "shad", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* shal $rn */
+ {
+ SH_INSN_SHAL_COMPACT, "shal-compact", "shal", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* shar $rn */
+ {
+ SH_INSN_SHAR_COMPACT, "shar-compact", "shar", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* shld $rm, $rn */
+ {
+ SH_INSN_SHLD_COMPACT, "shld-compact", "shld", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* shll $rn */
+ {
+ SH_INSN_SHLL_COMPACT, "shll-compact", "shll", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* shll2 $rn */
+ {
+ SH_INSN_SHLL2_COMPACT, "shll2-compact", "shll2", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* shll8 $rn */
+ {
+ SH_INSN_SHLL8_COMPACT, "shll8-compact", "shll8", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* shll16 $rn */
+ {
+ SH_INSN_SHLL16_COMPACT, "shll16-compact", "shll16", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* shlr $rn */
+ {
+ SH_INSN_SHLR_COMPACT, "shlr-compact", "shlr", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* shlr2 $rn */
+ {
+ SH_INSN_SHLR2_COMPACT, "shlr2-compact", "shlr2", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* shlr8 $rn */
+ {
+ SH_INSN_SHLR8_COMPACT, "shlr8-compact", "shlr8", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* shlr16 $rn */
+ {
+ SH_INSN_SHLR16_COMPACT, "shlr16-compact", "shlr16", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* stc gbr, $rn */
+ {
+ SH_INSN_STC_GBR_COMPACT, "stc-gbr-compact", "stc", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* stc.l gbr, @-$rn */
+ {
+ SH_INSN_STCL_GBR_COMPACT, "stcl-gbr-compact", "stc.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* sts fpscr, $rn */
+ {
+ SH_INSN_STS_FPSCR_COMPACT, "sts-fpscr-compact", "sts", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* sts.l fpscr, @-$rn */
+ {
+ SH_INSN_STSL_FPSCR_COMPACT, "stsl-fpscr-compact", "sts.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* sts fpul, $rn */
+ {
+ SH_INSN_STS_FPUL_COMPACT, "sts-fpul-compact", "sts", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* sts.l fpul, @-$rn */
+ {
+ SH_INSN_STSL_FPUL_COMPACT, "stsl-fpul-compact", "sts.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* sts mach, $rn */
+ {
+ SH_INSN_STS_MACH_COMPACT, "sts-mach-compact", "sts", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* sts.l mach, @-$rn */
+ {
+ SH_INSN_STSL_MACH_COMPACT, "stsl-mach-compact", "sts.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* sts macl, $rn */
+ {
+ SH_INSN_STS_MACL_COMPACT, "sts-macl-compact", "sts", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* sts.l macl, @-$rn */
+ {
+ SH_INSN_STSL_MACL_COMPACT, "stsl-macl-compact", "sts.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* sts pr, $rn */
+ {
+ SH_INSN_STS_PR_COMPACT, "sts-pr-compact", "sts", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* sts.l pr, @-$rn */
+ {
+ SH_INSN_STSL_PR_COMPACT, "stsl-pr-compact", "sts.l", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* sub $rm, $rn */
+ {
+ SH_INSN_SUB_COMPACT, "sub-compact", "sub", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* subc $rm, $rn */
+ {
+ SH_INSN_SUBC_COMPACT, "subc-compact", "subc", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* subv $rm, $rn */
+ {
+ SH_INSN_SUBV_COMPACT, "subv-compact", "subv", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* swap.b $rm, $rn */
+ {
+ SH_INSN_SWAPB_COMPACT, "swapb-compact", "swap.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* swap.w $rm, $rn */
+ {
+ SH_INSN_SWAPW_COMPACT, "swapw-compact", "swap.w", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* tas.b @$rn */
+ {
+ SH_INSN_TASB_COMPACT, "tasb-compact", "tas.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* trapa #$uimm8 */
+ {
+ SH_INSN_TRAPA_COMPACT, "trapa-compact", "trapa", 16,
+ { 0|A(ILLSLOT), { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* tst $rm, $rn */
+ {
+ SH_INSN_TST_COMPACT, "tst-compact", "tst", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* tst #$uimm8, r0 */
+ {
+ SH_INSN_TSTI_COMPACT, "tsti-compact", "tst", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* tst.b #$imm8, @(r0, gbr) */
+ {
+ SH_INSN_TSTB_COMPACT, "tstb-compact", "tst.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* xor $rm64, $rn64 */
+ {
+ SH_INSN_XOR_COMPACT, "xor-compact", "xor", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* xor #$uimm8, r0 */
+ {
+ SH_INSN_XORI_COMPACT, "xori-compact", "xor", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* xor.b #$imm8, @(r0, gbr) */
+ {
+ SH_INSN_XORB_COMPACT, "xorb-compact", "xor.b", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* xtrct $rm, $rn */
+ {
+ SH_INSN_XTRCT_COMPACT, "xtrct-compact", "xtrct", 16,
+ { 0, { (1<<MACH_BASE), (1<<ISA_COMPACT) } }
+ },
+/* add $rm, $rn, $rd */
+ {
+ SH_INSN_ADD, "add", "add", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* add.l $rm, $rn, $rd */
+ {
+ SH_INSN_ADDL, "addl", "add.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* addi $rm, $disp10, $rd */
+ {
+ SH_INSN_ADDI, "addi", "addi", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* addi.l $rm, $disp10, $rd */
+ {
+ SH_INSN_ADDIL, "addil", "addi.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* addz.l $rm, $rn, $rd */
+ {
+ SH_INSN_ADDZL, "addzl", "addz.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* alloco $rm, $disp6x32 */
+ {
+ SH_INSN_ALLOCO, "alloco", "alloco", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* and $rm, $rn, $rd */
+ {
+ SH_INSN_AND, "and", "and", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* andc $rm, $rn, $rd */
+ {
+ SH_INSN_ANDC, "andc", "andc", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* andi $rm, $disp10, $rd */
+ {
+ SH_INSN_ANDI, "andi", "andi", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* beq$likely $rm, $rn, $tra */
+ {
+ SH_INSN_BEQ, "beq", "beq", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* beqi$likely $rm, $imm6, $tra */
+ {
+ SH_INSN_BEQI, "beqi", "beqi", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* bge$likely $rm, $rn, $tra */
+ {
+ SH_INSN_BGE, "bge", "bge", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* bgeu$likely $rm, $rn, $tra */
+ {
+ SH_INSN_BGEU, "bgeu", "bgeu", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* bgt$likely $rm, $rn, $tra */
+ {
+ SH_INSN_BGT, "bgt", "bgt", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* bgtu$likely $rm, $rn, $tra */
+ {
+ SH_INSN_BGTU, "bgtu", "bgtu", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* blink $trb, $rd */
+ {
+ SH_INSN_BLINK, "blink", "blink", 32,
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* bne$likely $rm, $rn, $tra */
+ {
+ SH_INSN_BNE, "bne", "bne", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* bnei$likely $rm, $imm6, $tra */
+ {
+ SH_INSN_BNEI, "bnei", "bnei", 32,
+ { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* brk */
+ {
+ SH_INSN_BRK, "brk", "brk", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* byterev $rm, $rd */
+ {
+ SH_INSN_BYTEREV, "byterev", "byterev", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* cmpeq $rm, $rn, $rd */
+ {
+ SH_INSN_CMPEQ, "cmpeq", "cmpeq", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* cmpgt $rm, $rn, $rd */
+ {
+ SH_INSN_CMPGT, "cmpgt", "cmpgt", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* cmpgtu $rm,$rn, $rd */
+ {
+ SH_INSN_CMPGTU, "cmpgtu", "cmpgtu", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* cmveq $rm, $rn, $rd */
+ {
+ SH_INSN_CMVEQ, "cmveq", "cmveq", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* cmvne $rm, $rn, $rd */
+ {
+ SH_INSN_CMVNE, "cmvne", "cmvne", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fabs.d $drgh, $drf */
+ {
+ SH_INSN_FABSD, "fabsd", "fabs.d", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fabs.s $frgh, $frf */
+ {
+ SH_INSN_FABSS, "fabss", "fabs.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fadd.d $drg, $drh, $drf */
+ {
+ SH_INSN_FADDD, "faddd", "fadd.d", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fadd.s $frg, $frh, $frf */
+ {
+ SH_INSN_FADDS, "fadds", "fadd.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fcmpeq.d $drg, $drh, $rd */
+ {
+ SH_INSN_FCMPEQD, "fcmpeqd", "fcmpeq.d", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fcmpeq.s $frg, $frh, $rd */
+ {
+ SH_INSN_FCMPEQS, "fcmpeqs", "fcmpeq.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fcmpge.d $drg, $drh, $rd */
+ {
+ SH_INSN_FCMPGED, "fcmpged", "fcmpge.d", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fcmpge.s $frg, $frh, $rd */
+ {
+ SH_INSN_FCMPGES, "fcmpges", "fcmpge.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fcmpgt.d $drg, $drh, $rd */
+ {
+ SH_INSN_FCMPGTD, "fcmpgtd", "fcmpgt.d", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fcmpgt.s $frg, $frh, $rd */
+ {
+ SH_INSN_FCMPGTS, "fcmpgts", "fcmpgt.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fcmpun.d $drg, $drh, $rd */
+ {
+ SH_INSN_FCMPUND, "fcmpund", "fcmpun.d", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fcmpun.s $frg, $frh, $rd */
+ {
+ SH_INSN_FCMPUNS, "fcmpuns", "fcmpun.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fcnv.ds $drgh, $frf */
+ {
+ SH_INSN_FCNVDS, "fcnvds", "fcnv.ds", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fcnv.sd $frgh, $drf */
+ {
+ SH_INSN_FCNVSD, "fcnvsd", "fcnv.sd", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fdiv.d $drg, $drh, $drf */
+ {
+ SH_INSN_FDIVD, "fdivd", "fdiv.d", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fdiv.s $frg, $frh, $frf */
+ {
+ SH_INSN_FDIVS, "fdivs", "fdiv.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fgetscr $frf */
+ {
+ SH_INSN_FGETSCR, "fgetscr", "fgetscr", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fipr.s $fvg, $fvh, $frf */
+ {
+ SH_INSN_FIPRS, "fiprs", "fipr.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fld.d $rm, $disp10x8, $drf */
+ {
+ SH_INSN_FLDD, "fldd", "fld.d", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fld.p $rm, $disp10x8, $fpf */
+ {
+ SH_INSN_FLDP, "fldp", "fld.p", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fld.s $rm, $disp10x4, $frf */
+ {
+ SH_INSN_FLDS, "flds", "fld.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fldx.d $rm, $rn, $drf */
+ {
+ SH_INSN_FLDXD, "fldxd", "fldx.d", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fldx.p $rm, $rn, $fpf */
+ {
+ SH_INSN_FLDXP, "fldxp", "fldx.p", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fldx.s $rm, $rn, $frf */
+ {
+ SH_INSN_FLDXS, "fldxs", "fldx.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* float.ld $frgh, $drf */
+ {
+ SH_INSN_FLOATLD, "floatld", "float.ld", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* float.ls $frgh, $frf */
+ {
+ SH_INSN_FLOATLS, "floatls", "float.ls", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* float.qd $drgh, $drf */
+ {
+ SH_INSN_FLOATQD, "floatqd", "float.qd", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* float.qs $drgh, $frf */
+ {
+ SH_INSN_FLOATQS, "floatqs", "float.qs", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fmac.s $frg, $frh, $frf */
+ {
+ SH_INSN_FMACS, "fmacs", "fmac.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fmov.d $drgh, $drf */
+ {
+ SH_INSN_FMOVD, "fmovd", "fmov.d", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fmov.dq $drgh, $rd */
+ {
+ SH_INSN_FMOVDQ, "fmovdq", "fmov.dq", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fmov.ls $rm, $frf */
+ {
+ SH_INSN_FMOVLS, "fmovls", "fmov.ls", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fmov.qd $rm, $drf */
+ {
+ SH_INSN_FMOVQD, "fmovqd", "fmov.qd", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fmov.s $frgh, $frf */
+ {
+ SH_INSN_FMOVS, "fmovs", "fmov.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fmov.sl $frgh, $rd */
+ {
+ SH_INSN_FMOVSL, "fmovsl", "fmov.sl", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fmul.d $drg, $drh, $drf */
+ {
+ SH_INSN_FMULD, "fmuld", "fmul.d", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fmul.s $frg, $frh, $frf */
+ {
+ SH_INSN_FMULS, "fmuls", "fmul.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fneg.d $drgh, $drf */
+ {
+ SH_INSN_FNEGD, "fnegd", "fneg.d", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fneg.s $frgh, $frf */
+ {
+ SH_INSN_FNEGS, "fnegs", "fneg.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fputscr $frgh */
+ {
+ SH_INSN_FPUTSCR, "fputscr", "fputscr", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fsqrt.d $drgh, $drf */
+ {
+ SH_INSN_FSQRTD, "fsqrtd", "fsqrt.d", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fsqrt.s $frgh, $frf */
+ {
+ SH_INSN_FSQRTS, "fsqrts", "fsqrt.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fst.d $rm, $disp10x8, $drf */
+ {
+ SH_INSN_FSTD, "fstd", "fst.d", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fst.p $rm, $disp10x8, $fpf */
+ {
+ SH_INSN_FSTP, "fstp", "fst.p", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fst.s $rm, $disp10x4, $frf */
+ {
+ SH_INSN_FSTS, "fsts", "fst.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fstx.d $rm, $rn, $drf */
+ {
+ SH_INSN_FSTXD, "fstxd", "fstx.d", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fstx.p $rm, $rn, $fpf */
+ {
+ SH_INSN_FSTXP, "fstxp", "fstx.p", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fstx.s $rm, $rn, $frf */
+ {
+ SH_INSN_FSTXS, "fstxs", "fstx.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fsub.d $drg, $drh, $drf */
+ {
+ SH_INSN_FSUBD, "fsubd", "fsub.d", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* fsub.s $frg, $frh, $frf */
+ {
+ SH_INSN_FSUBS, "fsubs", "fsub.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ftrc.dl $drgh, $frf */
+ {
+ SH_INSN_FTRCDL, "ftrcdl", "ftrc.dl", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ftrc.sl $frgh, $frf */
+ {
+ SH_INSN_FTRCSL, "ftrcsl", "ftrc.sl", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ftrc.dq $drgh, $drf */
+ {
+ SH_INSN_FTRCDQ, "ftrcdq", "ftrc.dq", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ftrc.sq $frgh, $drf */
+ {
+ SH_INSN_FTRCSQ, "ftrcsq", "ftrc.sq", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ftrv.s $mtrxg, $fvh, $fvf */
+ {
+ SH_INSN_FTRVS, "ftrvs", "ftrv.s", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* getcfg $rm, $disp6, $rd */
+ {
+ SH_INSN_GETCFG, "getcfg", "getcfg", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* getcon $crk, $rd */
+ {
+ SH_INSN_GETCON, "getcon", "getcon", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* gettr $trb, $rd */
+ {
+ SH_INSN_GETTR, "gettr", "gettr", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* icbi $rm, $disp6x32 */
+ {
+ SH_INSN_ICBI, "icbi", "icbi", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ld.b $rm, $disp10, $rd */
+ {
+ SH_INSN_LDB, "ldb", "ld.b", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ld.l $rm, $disp10x4, $rd */
+ {
+ SH_INSN_LDL, "ldl", "ld.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ld.q $rm, $disp10x8, $rd */
+ {
+ SH_INSN_LDQ, "ldq", "ld.q", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ld.ub $rm, $disp10, $rd */
+ {
+ SH_INSN_LDUB, "ldub", "ld.ub", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ld.uw $rm, $disp10x2, $rd */
+ {
+ SH_INSN_LDUW, "lduw", "ld.uw", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ld.w $rm, $disp10x2, $rd */
+ {
+ SH_INSN_LDW, "ldw", "ld.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ldhi.l $rm, $disp6, $rd */
+ {
+ SH_INSN_LDHIL, "ldhil", "ldhi.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ldhi.q $rm, $disp6, $rd */
+ {
+ SH_INSN_LDHIQ, "ldhiq", "ldhi.q", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ldlo.l $rm, $disp6, $rd */
+ {
+ SH_INSN_LDLOL, "ldlol", "ldlo.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ldlo.q $rm, $disp6, $rd */
+ {
+ SH_INSN_LDLOQ, "ldloq", "ldlo.q", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ldx.b $rm, $rn, $rd */
+ {
+ SH_INSN_LDXB, "ldxb", "ldx.b", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ldx.l $rm, $rn, $rd */
+ {
+ SH_INSN_LDXL, "ldxl", "ldx.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ldx.q $rm, $rn, $rd */
+ {
+ SH_INSN_LDXQ, "ldxq", "ldx.q", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ldx.ub $rm, $rn, $rd */
+ {
+ SH_INSN_LDXUB, "ldxub", "ldx.ub", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ldx.uw $rm, $rn, $rd */
+ {
+ SH_INSN_LDXUW, "ldxuw", "ldx.uw", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ldx.w $rm, $rn, $rd */
+ {
+ SH_INSN_LDXW, "ldxw", "ldx.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mabs.l $rm, $rd */
+ {
+ SH_INSN_MABSL, "mabsl", "mabs.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mabs.w $rm, $rd */
+ {
+ SH_INSN_MABSW, "mabsw", "mabs.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* madd.l $rm, $rn, $rd */
+ {
+ SH_INSN_MADDL, "maddl", "madd.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* madd.w $rm, $rn, $rd */
+ {
+ SH_INSN_MADDW, "maddw", "madd.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* madds.l $rm, $rn, $rd */
+ {
+ SH_INSN_MADDSL, "maddsl", "madds.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* madds.ub $rm, $rn, $rd */
+ {
+ SH_INSN_MADDSUB, "maddsub", "madds.ub", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* madds.w $rm, $rn, $rd */
+ {
+ SH_INSN_MADDSW, "maddsw", "madds.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mcmpeq.b $rm, $rn, $rd */
+ {
+ SH_INSN_MCMPEQB, "mcmpeqb", "mcmpeq.b", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mcmpeq.l $rm, $rn, $rd */
+ {
+ SH_INSN_MCMPEQL, "mcmpeql", "mcmpeq.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mcmpeq.w $rm, $rn, $rd */
+ {
+ SH_INSN_MCMPEQW, "mcmpeqw", "mcmpeq.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mcmpgt.l $rm, $rn, $rd */
+ {
+ SH_INSN_MCMPGTL, "mcmpgtl", "mcmpgt.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mcmpgt.ub $rm, $rn, $rd */
+ {
+ SH_INSN_MCMPGTUB, "mcmpgtub", "mcmpgt.ub", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mcmpgt.w $rm, $rn, $rd */
+ {
+ SH_INSN_MCMPGTW, "mcmpgtw", "mcmpgt.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mcmv $rm, $rn, $rd */
+ {
+ SH_INSN_MCMV, "mcmv", "mcmv", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mcnvs.lw $rm, $rn, $rd */
+ {
+ SH_INSN_MCNVSLW, "mcnvslw", "mcnvs.lw", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mcnvs.wb $rm, $rn, $rd */
+ {
+ SH_INSN_MCNVSWB, "mcnvswb", "mcnvs.wb", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mcnvs.wub $rm, $rn, $rd */
+ {
+ SH_INSN_MCNVSWUB, "mcnvswub", "mcnvs.wub", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mextr1 $rm, $rn, $rd */
+ {
+ SH_INSN_MEXTR1, "mextr1", "mextr1", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mextr2 $rm, $rn, $rd */
+ {
+ SH_INSN_MEXTR2, "mextr2", "mextr2", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mextr3 $rm, $rn, $rd */
+ {
+ SH_INSN_MEXTR3, "mextr3", "mextr3", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mextr4 $rm, $rn, $rd */
+ {
+ SH_INSN_MEXTR4, "mextr4", "mextr4", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mextr5 $rm, $rn, $rd */
+ {
+ SH_INSN_MEXTR5, "mextr5", "mextr5", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mextr6 $rm, $rn, $rd */
+ {
+ SH_INSN_MEXTR6, "mextr6", "mextr6", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mextr7 $rm, $rn, $rd */
+ {
+ SH_INSN_MEXTR7, "mextr7", "mextr7", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mmacfx.wl $rm, $rn, $rd */
+ {
+ SH_INSN_MMACFXWL, "mmacfxwl", "mmacfx.wl", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mmacnfx.wl $rm, $rn, $rd */
+ {
+ SH_INSN_MMACNFX_WL, "mmacnfx.wl", "mmacnfx.wl", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mmul.l $rm, $rn, $rd */
+ {
+ SH_INSN_MMULL, "mmull", "mmul.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mmul.w $rm, $rn, $rd */
+ {
+ SH_INSN_MMULW, "mmulw", "mmul.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mmulfx.l $rm, $rn, $rd */
+ {
+ SH_INSN_MMULFXL, "mmulfxl", "mmulfx.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mmulfx.w $rm, $rn, $rd */
+ {
+ SH_INSN_MMULFXW, "mmulfxw", "mmulfx.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mmulfxrp.w $rm, $rn, $rd */
+ {
+ SH_INSN_MMULFXRPW, "mmulfxrpw", "mmulfxrp.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mmulhi.wl $rm, $rn, $rd */
+ {
+ SH_INSN_MMULHIWL, "mmulhiwl", "mmulhi.wl", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mmullo.wl $rm, $rn, $rd */
+ {
+ SH_INSN_MMULLOWL, "mmullowl", "mmullo.wl", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mmulsum.wq $rm, $rn, $rd */
+ {
+ SH_INSN_MMULSUMWQ, "mmulsumwq", "mmulsum.wq", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* movi $imm16, $rd */
+ {
+ SH_INSN_MOVI, "movi", "movi", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mperm.w $rm, $rn, $rd */
+ {
+ SH_INSN_MPERMW, "mpermw", "mperm.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* msad.ubq $rm, $rn, $rd */
+ {
+ SH_INSN_MSADUBQ, "msadubq", "msad.ubq", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mshalds.l $rm, $rn, $rd */
+ {
+ SH_INSN_MSHALDSL, "mshaldsl", "mshalds.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mshalds.w $rm, $rn, $rd */
+ {
+ SH_INSN_MSHALDSW, "mshaldsw", "mshalds.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mshard.l $rm, $rn, $rd */
+ {
+ SH_INSN_MSHARDL, "mshardl", "mshard.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mshard.w $rm, $rn, $rd */
+ {
+ SH_INSN_MSHARDW, "mshardw", "mshard.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mshards.q $rm, $rn, $rd */
+ {
+ SH_INSN_MSHARDSQ, "mshardsq", "mshards.q", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mshfhi.b $rm, $rn, $rd */
+ {
+ SH_INSN_MSHFHIB, "mshfhib", "mshfhi.b", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mshfhi.l $rm, $rn, $rd */
+ {
+ SH_INSN_MSHFHIL, "mshfhil", "mshfhi.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mshfhi.w $rm, $rn, $rd */
+ {
+ SH_INSN_MSHFHIW, "mshfhiw", "mshfhi.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mshflo.b $rm, $rn, $rd */
+ {
+ SH_INSN_MSHFLOB, "mshflob", "mshflo.b", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mshflo.l $rm, $rn, $rd */
+ {
+ SH_INSN_MSHFLOL, "mshflol", "mshflo.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mshflo.w $rm, $rn, $rd */
+ {
+ SH_INSN_MSHFLOW, "mshflow", "mshflo.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mshlld.l $rm, $rn, $rd */
+ {
+ SH_INSN_MSHLLDL, "mshlldl", "mshlld.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mshlld.w $rm, $rn, $rd */
+ {
+ SH_INSN_MSHLLDW, "mshlldw", "mshlld.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mshlrd.l $rm, $rn, $rd */
+ {
+ SH_INSN_MSHLRDL, "mshlrdl", "mshlrd.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mshlrd.w $rm, $rn, $rd */
+ {
+ SH_INSN_MSHLRDW, "mshlrdw", "mshlrd.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* msub.l $rm, $rn, $rd */
+ {
+ SH_INSN_MSUBL, "msubl", "msub.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* msub.w $rm, $rn, $rd */
+ {
+ SH_INSN_MSUBW, "msubw", "msub.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* msubs.l $rm, $rn, $rd */
+ {
+ SH_INSN_MSUBSL, "msubsl", "msubs.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* msubs.ub $rm, $rn, $rd */
+ {
+ SH_INSN_MSUBSUB, "msubsub", "msubs.ub", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* msubs.w $rm, $rn, $rd */
+ {
+ SH_INSN_MSUBSW, "msubsw", "msubs.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* muls.l $rm, $rn, $rd */
+ {
+ SH_INSN_MULSL, "mulsl", "muls.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* mulu.l $rm, $rn, $rd */
+ {
+ SH_INSN_MULUL, "mulul", "mulu.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* nop */
+ {
+ SH_INSN_NOP, "nop", "nop", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* nsb $rm, $rd */
+ {
+ SH_INSN_NSB, "nsb", "nsb", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ocbi $rm, $disp6x32 */
+ {
+ SH_INSN_OCBI, "ocbi", "ocbi", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ocbp $rm, $disp6x32 */
+ {
+ SH_INSN_OCBP, "ocbp", "ocbp", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ocbwb $rm, $disp6x32 */
+ {
+ SH_INSN_OCBWB, "ocbwb", "ocbwb", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* or $rm, $rn, $rd */
+ {
+ SH_INSN_OR, "or", "or", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ori $rm, $imm10, $rd */
+ {
+ SH_INSN_ORI, "ori", "ori", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* prefi $rm, $disp6x32 */
+ {
+ SH_INSN_PREFI, "prefi", "prefi", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* pta$likely $disp16, $tra */
+ {
+ SH_INSN_PTA, "pta", "pta", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ptabs$likely $rn, $tra */
+ {
+ SH_INSN_PTABS, "ptabs", "ptabs", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ptb$likely $disp16, $tra */
+ {
+ SH_INSN_PTB, "ptb", "ptb", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* ptrel$likely $rn, $tra */
+ {
+ SH_INSN_PTREL, "ptrel", "ptrel", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* putcfg $rm, $disp6, $rd */
+ {
+ SH_INSN_PUTCFG, "putcfg", "putcfg", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* putcon $rm, $crj */
+ {
+ SH_INSN_PUTCON, "putcon", "putcon", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* rte */
+ {
+ SH_INSN_RTE, "rte", "rte", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* shard $rm, $rn, $rd */
+ {
+ SH_INSN_SHARD, "shard", "shard", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* shard.l $rm, $rn, $rd */
+ {
+ SH_INSN_SHARDL, "shardl", "shard.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* shari $rm, $uimm6, $rd */
+ {
+ SH_INSN_SHARI, "shari", "shari", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* shari.l $rm, $uimm6, $rd */
+ {
+ SH_INSN_SHARIL, "sharil", "shari.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* shlld $rm, $rn, $rd */
+ {
+ SH_INSN_SHLLD, "shlld", "shlld", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* shlld.l $rm, $rn, $rd */
+ {
+ SH_INSN_SHLLDL, "shlldl", "shlld.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* shlli $rm, $uimm6, $rd */
+ {
+ SH_INSN_SHLLI, "shlli", "shlli", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* shlli.l $rm, $uimm6, $rd */
+ {
+ SH_INSN_SHLLIL, "shllil", "shlli.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* shlrd $rm, $rn, $rd */
+ {
+ SH_INSN_SHLRD, "shlrd", "shlrd", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* shlrd.l $rm, $rn, $rd */
+ {
+ SH_INSN_SHLRDL, "shlrdl", "shlrd.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* shlri $rm, $uimm6, $rd */
+ {
+ SH_INSN_SHLRI, "shlri", "shlri", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* shlri.l $rm, $uimm6, $rd */
+ {
+ SH_INSN_SHLRIL, "shlril", "shlri.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* shori $uimm16, $rd */
+ {
+ SH_INSN_SHORI, "shori", "shori", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* sleep */
+ {
+ SH_INSN_SLEEP, "sleep", "sleep", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* st.b $rm, $disp10, $rd */
+ {
+ SH_INSN_STB, "stb", "st.b", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* st.l $rm, $disp10x4, $rd */
+ {
+ SH_INSN_STL, "stl", "st.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* st.q $rm, $disp10x8, $rd */
+ {
+ SH_INSN_STQ, "stq", "st.q", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* st.w $rm, $disp10x2, $rd */
+ {
+ SH_INSN_STW, "stw", "st.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* sthi.l $rm, $disp6, $rd */
+ {
+ SH_INSN_STHIL, "sthil", "sthi.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* sthi.q $rm, $disp6, $rd */
+ {
+ SH_INSN_STHIQ, "sthiq", "sthi.q", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* stlo.l $rm, $disp6, $rd */
+ {
+ SH_INSN_STLOL, "stlol", "stlo.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* stlo.q $rm, $disp6, $rd */
+ {
+ SH_INSN_STLOQ, "stloq", "stlo.q", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* stx.b $rm, $rn, $rd */
+ {
+ SH_INSN_STXB, "stxb", "stx.b", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* stx.l $rm, $rn, $rd */
+ {
+ SH_INSN_STXL, "stxl", "stx.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* stx.q $rm, $rn, $rd */
+ {
+ SH_INSN_STXQ, "stxq", "stx.q", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* stx.w $rm, $rn, $rd */
+ {
+ SH_INSN_STXW, "stxw", "stx.w", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* sub $rm, $rn, $rd */
+ {
+ SH_INSN_SUB, "sub", "sub", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* sub.l $rm, $rn, $rd */
+ {
+ SH_INSN_SUBL, "subl", "sub.l", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* swap.q $rm, $rn, $rd */
+ {
+ SH_INSN_SWAPQ, "swapq", "swap.q", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* synci */
+ {
+ SH_INSN_SYNCI, "synci", "synci", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* synco */
+ {
+ SH_INSN_SYNCO, "synco", "synco", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* trapa $rm */
+ {
+ SH_INSN_TRAPA, "trapa", "trapa", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* xor $rm, $rn, $rd */
+ {
+ SH_INSN_XOR, "xor", "xor", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+/* xori $rm, $imm6, $rd */
+ {
+ SH_INSN_XORI, "xori", "xori", 32,
+ { 0, { (1<<MACH_BASE), (1<<ISA_MEDIA) } }
+ },
+};
+
+#undef OP
+#undef A
+
+/* Initialize anything needed to be done once, before any cpu_open call. */
+
+static void
+init_tables ()
+{
+}
+
+/* Subroutine of sh_cgen_cpu_open to look up a mach via its bfd name. */
+
+static const CGEN_MACH *
+lookup_mach_via_bfd_name (table, name)
+ const CGEN_MACH *table;
+ const char *name;
+{
+ while (table->name)
+ {
+ if (strcmp (name, table->bfd_name) == 0)
+ return table;
+ ++table;
+ }
+ abort ();
+}
+
+/* Subroutine of sh_cgen_cpu_open to build the hardware table. */
+
+static void
+build_hw_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ int machs = cd->machs;
+ const CGEN_HW_ENTRY *init = & sh_cgen_hw_table[0];
+ /* MAX_HW is only an upper bound on the number of selected entries.
+ However each entry is indexed by it's enum so there can be holes in
+ the table. */
+ const CGEN_HW_ENTRY **selected =
+ (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
+
+ cd->hw_table.init_entries = init;
+ cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
+ memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
+ /* ??? For now we just use machs to determine which ones we want. */
+ for (i = 0; init[i].name != NULL; ++i)
+ if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
+ & machs)
+ selected[init[i].type] = &init[i];
+ cd->hw_table.entries = selected;
+ cd->hw_table.num_entries = MAX_HW;
+}
+
+/* Subroutine of sh_cgen_cpu_open to build the hardware table. */
+
+static void
+build_ifield_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ cd->ifld_table = & sh_cgen_ifld_table[0];
+}
+
+/* Subroutine of sh_cgen_cpu_open to build the hardware table. */
+
+static void
+build_operand_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ int machs = cd->machs;
+ const CGEN_OPERAND *init = & sh_cgen_operand_table[0];
+ /* MAX_OPERANDS is only an upper bound on the number of selected entries.
+ However each entry is indexed by it's enum so there can be holes in
+ the table. */
+ const CGEN_OPERAND **selected =
+ (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+
+ cd->operand_table.init_entries = init;
+ cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
+ memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+ /* ??? For now we just use mach to determine which ones we want. */
+ for (i = 0; init[i].name != NULL; ++i)
+ if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
+ & machs)
+ selected[init[i].type] = &init[i];
+ cd->operand_table.entries = selected;
+ cd->operand_table.num_entries = MAX_OPERANDS;
+}
+
+/* Subroutine of sh_cgen_cpu_open to build the hardware table.
+ ??? This could leave out insns not supported by the specified mach/isa,
+ but that would cause errors like "foo only supported by bar" to become
+ "unknown insn", so for now we include all insns and require the app to
+ do the checking later.
+ ??? On the other hand, parsing of such insns may require their hardware or
+ operand elements to be in the table [which they mightn't be]. */
+
+static void
+build_insn_table (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i;
+ const CGEN_IBASE *ib = & sh_cgen_insn_table[0];
+ CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+
+ memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
+ for (i = 0; i < MAX_INSNS; ++i)
+ insns[i].base = &ib[i];
+ cd->insn_table.init_entries = insns;
+ cd->insn_table.entry_size = sizeof (CGEN_IBASE);
+ cd->insn_table.num_init_entries = MAX_INSNS;
+}
+
+/* Subroutine of sh_cgen_cpu_open to rebuild the tables. */
+
+static void
+sh_cgen_rebuild_tables (cd)
+ CGEN_CPU_TABLE *cd;
+{
+ int i,n_isas;
+ unsigned int isas = cd->isas;
+#if 0
+ unsigned int machs = cd->machs;
+#endif
+
+ cd->int_insn_p = CGEN_INT_INSN_P;
+
+ /* Data derived from the isa spec. */
+#define UNSET (CGEN_SIZE_UNKNOWN + 1)
+ cd->default_insn_bitsize = UNSET;
+ cd->base_insn_bitsize = UNSET;
+ cd->min_insn_bitsize = 65535; /* some ridiculously big number */
+ cd->max_insn_bitsize = 0;
+ for (i = 0; i < MAX_ISAS; ++i)
+ if (((1 << i) & isas) != 0)
+ {
+ const CGEN_ISA *isa = & sh_cgen_isa_table[i];
+
+ /* Default insn sizes of all selected isas must be equal or we set
+ the result to 0, meaning "unknown". */
+ if (cd->default_insn_bitsize == UNSET)
+ cd->default_insn_bitsize = isa->default_insn_bitsize;
+ else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
+ ; /* this is ok */
+ else
+ cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+ /* Base insn sizes of all selected isas must be equal or we set
+ the result to 0, meaning "unknown". */
+ if (cd->base_insn_bitsize == UNSET)
+ cd->base_insn_bitsize = isa->base_insn_bitsize;
+ else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
+ ; /* this is ok */
+ else
+ cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+ /* Set min,max insn sizes. */
+ if (isa->min_insn_bitsize < cd->min_insn_bitsize)
+ cd->min_insn_bitsize = isa->min_insn_bitsize;
+ if (isa->max_insn_bitsize > cd->max_insn_bitsize)
+ cd->max_insn_bitsize = isa->max_insn_bitsize;
+
+ ++n_isas;
+ }
+
+#if 0 /* Does nothing?? */
+ /* Data derived from the mach spec. */
+ for (i = 0; i < MAX_MACHS; ++i)
+ if (((1 << i) & machs) != 0)
+ {
+ const CGEN_MACH *mach = & sh_cgen_mach_table[i];
+
+ ++n_machs;
+ }
+#endif
+
+ /* Determine which hw elements are used by MACH. */
+ build_hw_table (cd);
+
+ /* Build the ifield table. */
+ build_ifield_table (cd);
+
+ /* Determine which operands are used by MACH/ISA. */
+ build_operand_table (cd);
+
+ /* Build the instruction table. */
+ build_insn_table (cd);
+}
+
+/* Initialize a cpu table and return a descriptor.
+ It's much like opening a file, and must be the first function called.
+ The arguments are a set of (type/value) pairs, terminated with
+ CGEN_CPU_OPEN_END.
+
+ Currently supported values:
+ CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
+ CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
+ CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
+ CGEN_CPU_OPEN_ENDIAN: specify endian choice
+ CGEN_CPU_OPEN_END: terminates arguments
+
+ ??? Simultaneous multiple isas might not make sense, but it's not (yet)
+ precluded.
+
+ ??? We only support ISO C stdargs here, not K&R.
+ Laziness, plus experiment to see if anything requires K&R - eventually
+ K&R will no longer be supported - e.g. GDB is currently trying this. */
+
+CGEN_CPU_DESC
+sh_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+{
+ CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
+ static int init_p;
+ unsigned int isas = 0; /* 0 = "unspecified" */
+ unsigned int machs = 0; /* 0 = "unspecified" */
+ enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
+ va_list ap;
+
+ if (! init_p)
+ {
+ init_tables ();
+ init_p = 1;
+ }
+
+ memset (cd, 0, sizeof (*cd));
+
+ va_start (ap, arg_type);
+ while (arg_type != CGEN_CPU_OPEN_END)
+ {
+ switch (arg_type)
+ {
+ case CGEN_CPU_OPEN_ISAS :
+ isas = va_arg (ap, unsigned int);
+ break;
+ case CGEN_CPU_OPEN_MACHS :
+ machs = va_arg (ap, unsigned int);
+ break;
+ case CGEN_CPU_OPEN_BFDMACH :
+ {
+ const char *name = va_arg (ap, const char *);
+ const CGEN_MACH *mach =
+ lookup_mach_via_bfd_name (sh_cgen_mach_table, name);
+
+ machs |= mach->num << 1;
+ break;
+ }
+ case CGEN_CPU_OPEN_ENDIAN :
+ endian = va_arg (ap, enum cgen_endian);
+ break;
+ default :
+ fprintf (stderr, "sh_cgen_cpu_open: unsupported argument `%d'\n",
+ arg_type);
+ abort (); /* ??? return NULL? */
+ }
+ arg_type = va_arg (ap, enum cgen_cpu_open_arg);
+ }
+ va_end (ap);
+
+ /* mach unspecified means "all" */
+ if (machs == 0)
+ machs = (1 << MAX_MACHS) - 1;
+ /* base mach is always selected */
+ machs |= 1;
+ /* isa unspecified means "all" */
+ if (isas == 0)
+ isas = (1 << MAX_ISAS) - 1;
+ if (endian == CGEN_ENDIAN_UNKNOWN)
+ {
+ /* ??? If target has only one, could have a default. */
+ fprintf (stderr, "sh_cgen_cpu_open: no endianness specified\n");
+ abort ();
+ }
+
+ cd->isas = isas;
+ cd->machs = machs;
+ cd->endian = endian;
+ /* FIXME: for the sparc case we can determine insn-endianness statically.
+ The worry here is where both data and insn endian can be independently
+ chosen, in which case this function will need another argument.
+ Actually, will want to allow for more arguments in the future anyway. */
+ cd->insn_endian = endian;
+
+ /* Table (re)builder. */
+ cd->rebuild_tables = sh_cgen_rebuild_tables;
+ sh_cgen_rebuild_tables (cd);
+
+ /* Default to not allowing signed overflow. */
+ cd->signed_overflow_ok_p = 0;
+
+ return (CGEN_CPU_DESC) cd;
+}
+
+/* Cover fn to sh_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
+ MACH_NAME is the bfd name of the mach. */
+
+CGEN_CPU_DESC
+sh_cgen_cpu_open_1 (mach_name, endian)
+ const char *mach_name;
+ enum cgen_endian endian;
+{
+ return sh_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
+ CGEN_CPU_OPEN_ENDIAN, endian,
+ CGEN_CPU_OPEN_END);
+}
+
+/* Close a cpu table.
+ ??? This can live in a machine independent file, but there's currently
+ no place to put this file (there's no libcgen). libopcodes is the wrong
+ place as some simulator ports use this but they don't use libopcodes. */
+
+void
+sh_cgen_cpu_close (cd)
+ CGEN_CPU_DESC cd;
+{
+ if (cd->insn_table.init_entries)
+ free ((CGEN_INSN *) cd->insn_table.init_entries);
+ if (cd->hw_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+ free (cd);
+}
+
--- /dev/null
+/* CPU data header for sh.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef SH_CPU_H
+#define SH_CPU_H
+
+#define CGEN_ARCH sh
+
+/* Given symbol S, return sh_cgen_<S>. */
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define CGEN_SYM(s) sh##_cgen_##s
+#else
+#define CGEN_SYM(s) sh/**/_cgen_/**/s
+#endif
+
+
+/* Selected cpu families. */
+#define HAVE_CPU_SH64
+
+#define CGEN_INSN_LSB0_P 1
+
+/* Minimum size of any insn (in bytes). */
+#define CGEN_MIN_INSN_SIZE 2
+
+/* Maximum size of any insn (in bytes). */
+#define CGEN_MAX_INSN_SIZE 4
+
+#define CGEN_INT_INSN_P 1
+
+/* Maximum nymber of syntax bytes in an instruction. */
+#define CGEN_ACTUAL_MAX_SYNTAX_BYTES 22
+
+/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
+ e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
+ we can't hash on everything up to the space. */
+#define CGEN_MNEMONIC_OPERANDS
+
+/* Maximum number of fields in an instruction. */
+#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8
+
+/* Enums. */
+
+/* Enum declaration for . */
+typedef enum frc_names {
+ H_FRC_FR0, H_FRC_FR1, H_FRC_FR2, H_FRC_FR3
+ , H_FRC_FR4, H_FRC_FR5, H_FRC_FR6, H_FRC_FR7
+ , H_FRC_FR8, H_FRC_FR9, H_FRC_FR10, H_FRC_FR11
+ , H_FRC_FR12, H_FRC_FR13, H_FRC_FR14, H_FRC_FR15
+} FRC_NAMES;
+
+/* Enum declaration for . */
+typedef enum drc_names {
+ H_DRC_DR0 = 0, H_DRC_DR2 = 2, H_DRC_DR4 = 4, H_DRC_DR6 = 6
+ , H_DRC_DR8 = 8, H_DRC_DR10 = 10, H_DRC_DR12 = 12, H_DRC_DR14 = 14
+} DRC_NAMES;
+
+/* Enum declaration for . */
+typedef enum xf_names {
+ H_XF_XF0, H_XF_XF1, H_XF_XF2, H_XF_XF3
+ , H_XF_XF4, H_XF_XF5, H_XF_XF6, H_XF_XF7
+ , H_XF_XF8, H_XF_XF9, H_XF_XF10, H_XF_XF11
+ , H_XF_XF12, H_XF_XF13, H_XF_XF14, H_XF_XF15
+} XF_NAMES;
+
+/* Attributes. */
+
+/* Enum declaration for machine type selection. */
+typedef enum mach_attr {
+ MACH_BASE, MACH_SH2, MACH_SH3, MACH_SH3E
+ , MACH_SH4, MACH_SH5, MACH_MAX
+} MACH_ATTR;
+
+/* Enum declaration for instruction set selection. */
+typedef enum isa_attr {
+ ISA_COMPACT, ISA_MEDIA, ISA_MAX
+} ISA_ATTR;
+
+/* Number of architecture variants. */
+#define MAX_ISAS ((int) ISA_MAX)
+#define MAX_MACHS ((int) MACH_MAX)
+
+/* Ifield support. */
+
+extern const struct cgen_ifld sh_cgen_ifld_table[];
+
+/* Ifield attribute indices. */
+
+/* Enum declaration for cgen_ifld attrs. */
+typedef enum cgen_ifld_attr {
+ CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
+ , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
+ , CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS
+} CGEN_IFLD_ATTR;
+
+/* Number of non-boolean elements in cgen_ifld_attr. */
+#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
+
+/* Enum declaration for sh ifield types. */
+typedef enum ifield_type {
+ SH_F_NIL, SH_F_ANYOF, SH_F_OP4, SH_F_OP8
+ , SH_F_OP16, SH_F_SUB4, SH_F_SUB8, SH_F_SUB10
+ , SH_F_RN, SH_F_RM, SH_F_8_1, SH_F_DISP8
+ , SH_F_DISP12, SH_F_IMM8, SH_F_IMM4, SH_F_IMM4X2
+ , SH_F_IMM4X4, SH_F_IMM8X2, SH_F_IMM8X4, SH_F_DN
+ , SH_F_DM, SH_F_VN, SH_F_VM, SH_F_XN
+ , SH_F_XM, SH_F_OP, SH_F_EXT, SH_F_RSVD
+ , SH_F_LEFT, SH_F_RIGHT, SH_F_DEST, SH_F_LEFT_RIGHT
+ , SH_F_TRA, SH_F_TRB, SH_F_LIKELY, SH_F_25
+ , SH_F_8_2, SH_F_IMM6, SH_F_IMM10, SH_F_IMM16
+ , SH_F_UIMM6, SH_F_UIMM16, SH_F_DISP6, SH_F_DISP6X32
+ , SH_F_DISP10, SH_F_DISP10X8, SH_F_DISP10X4, SH_F_DISP10X2
+ , SH_F_DISP16, SH_F_MAX
+} IFIELD_TYPE;
+
+#define MAX_IFLD ((int) SH_F_MAX)
+
+/* Hardware attribute indices. */
+
+/* Enum declaration for cgen_hw attrs. */
+typedef enum cgen_hw_attr {
+ CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
+ , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
+} CGEN_HW_ATTR;
+
+/* Number of non-boolean elements in cgen_hw_attr. */
+#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
+
+/* Enum declaration for sh hardware types. */
+typedef enum cgen_hw_type {
+ HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
+ , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GRC
+ , HW_H_CR, HW_H_SR, HW_H_FPSCR, HW_H_FRBIT
+ , HW_H_SZBIT, HW_H_PRBIT, HW_H_SBIT, HW_H_MBIT
+ , HW_H_QBIT, HW_H_FR, HW_H_FP, HW_H_FV
+ , HW_H_FMTX, HW_H_DR, HW_H_TR, HW_H_ENDIAN
+ , HW_H_ISM, HW_H_FRC, HW_H_DRC, HW_H_XF
+ , HW_H_XD, HW_H_FVC, HW_H_FPCCR, HW_H_GBR
+ , HW_H_PR, HW_H_MACL, HW_H_MACH, HW_H_TBIT
+ , HW_MAX
+} CGEN_HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Operand attribute indices. */
+
+/* Enum declaration for cgen_operand attrs. */
+typedef enum cgen_operand_attr {
+ CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
+ , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
+ , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA
+ , CGEN_OPERAND_END_NBOOLS
+} CGEN_OPERAND_ATTR;
+
+/* Number of non-boolean elements in cgen_operand_attr. */
+#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
+
+/* Enum declaration for sh operand types. */
+typedef enum cgen_operand_type {
+ SH_OPERAND_PC, SH_OPERAND_ENDIAN, SH_OPERAND_ISM, SH_OPERAND_RM
+ , SH_OPERAND_RN, SH_OPERAND_R0, SH_OPERAND_FRN, SH_OPERAND_FRM
+ , SH_OPERAND_FVN, SH_OPERAND_FVM, SH_OPERAND_DRN, SH_OPERAND_DRM
+ , SH_OPERAND_IMM4, SH_OPERAND_IMM8, SH_OPERAND_UIMM8, SH_OPERAND_IMM4X2
+ , SH_OPERAND_IMM4X4, SH_OPERAND_IMM8X2, SH_OPERAND_IMM8X4, SH_OPERAND_DISP8
+ , SH_OPERAND_DISP12, SH_OPERAND_RM64, SH_OPERAND_RN64, SH_OPERAND_GBR
+ , SH_OPERAND_PR, SH_OPERAND_FPSCR, SH_OPERAND_TBIT, SH_OPERAND_SBIT
+ , SH_OPERAND_MBIT, SH_OPERAND_QBIT, SH_OPERAND_FPUL, SH_OPERAND_FRBIT
+ , SH_OPERAND_SZBIT, SH_OPERAND_PRBIT, SH_OPERAND_MACL, SH_OPERAND_MACH
+ , SH_OPERAND_FSDM, SH_OPERAND_FSDN, SH_OPERAND_RD, SH_OPERAND_FRG
+ , SH_OPERAND_FRH, SH_OPERAND_FRF, SH_OPERAND_FRGH, SH_OPERAND_FPF
+ , SH_OPERAND_FVG, SH_OPERAND_FVH, SH_OPERAND_FVF, SH_OPERAND_MTRXG
+ , SH_OPERAND_DRG, SH_OPERAND_DRH, SH_OPERAND_DRF, SH_OPERAND_DRGH
+ , SH_OPERAND_CRJ, SH_OPERAND_CRK, SH_OPERAND_TRA, SH_OPERAND_TRB
+ , SH_OPERAND_DISP6, SH_OPERAND_DISP6X32, SH_OPERAND_DISP10, SH_OPERAND_DISP10X2
+ , SH_OPERAND_DISP10X4, SH_OPERAND_DISP10X8, SH_OPERAND_DISP16, SH_OPERAND_IMM6
+ , SH_OPERAND_IMM10, SH_OPERAND_IMM16, SH_OPERAND_UIMM6, SH_OPERAND_UIMM16
+ , SH_OPERAND_LIKELY, SH_OPERAND_MAX
+} CGEN_OPERAND_TYPE;
+
+/* Number of operands types. */
+#define MAX_OPERANDS 72
+
+/* Maximum number of operands referenced by any insn. */
+#define MAX_OPERAND_INSTANCES 8
+
+/* Insn attribute indices. */
+
+/* Enum declaration for cgen_insn attrs. */
+typedef enum cgen_insn_attr {
+ CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
+ , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_ILLSLOT, CGEN_INSN_FP_INSN
+ , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
+ , CGEN_INSN_END_NBOOLS
+} CGEN_INSN_ATTR;
+
+/* Number of non-boolean elements in cgen_insn_attr. */
+#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
+
+/* cgen.h uses things we just defined. */
+#include "opcode/cgen.h"
+
+/* Attributes. */
+extern const CGEN_ATTR_TABLE sh_cgen_hardware_attr_table[];
+extern const CGEN_ATTR_TABLE sh_cgen_ifield_attr_table[];
+extern const CGEN_ATTR_TABLE sh_cgen_operand_attr_table[];
+extern const CGEN_ATTR_TABLE sh_cgen_insn_attr_table[];
+
+/* Hardware decls. */
+
+extern CGEN_KEYWORD sh_cgen_opval_h_gr;
+extern CGEN_KEYWORD sh_cgen_opval_h_grc;
+extern CGEN_KEYWORD sh_cgen_opval_h_cr;
+extern CGEN_KEYWORD sh_cgen_opval_h_fr;
+extern CGEN_KEYWORD sh_cgen_opval_h_fp;
+extern CGEN_KEYWORD sh_cgen_opval_h_fv;
+extern CGEN_KEYWORD sh_cgen_opval_h_fmtx;
+extern CGEN_KEYWORD sh_cgen_opval_h_dr;
+extern CGEN_KEYWORD sh_cgen_opval_h_tr;
+extern CGEN_KEYWORD sh_cgen_opval_frc_names;
+extern CGEN_KEYWORD sh_cgen_opval_drc_names;
+extern CGEN_KEYWORD sh_cgen_opval_xf_names;
+extern CGEN_KEYWORD sh_cgen_opval_frc_names;
+extern CGEN_KEYWORD sh_cgen_opval_h_fvc;
+
+
+
+
+#endif /* SH_CPU_H */
--- /dev/null
+/* Instruction opcode header for sh.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef SH_OPC_H
+#define SH_OPC_H
+
+/* -- opc.h */
+
+/* Allows reason codes to be output when assembler errors occur. */
+#define CGEN_VERBOSE_ASSEMBLER_ERRORS
+
+/* Override disassembly hashing - there are variable bits in the top
+ byte of these instructions. */
+#define CGEN_DIS_HASH_SIZE 8
+#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 6) % CGEN_DIS_HASH_SIZE)
+
+/* -- asm.c */
+/* Enum declaration for sh instruction types. */
+typedef enum cgen_insn_type {
+ SH_INSN_INVALID, SH_INSN_ADD_COMPACT, SH_INSN_ADDI_COMPACT, SH_INSN_ADDC_COMPACT
+ , SH_INSN_ADDV_COMPACT, SH_INSN_AND_COMPACT, SH_INSN_ANDI_COMPACT, SH_INSN_ANDB_COMPACT
+ , SH_INSN_BF_COMPACT, SH_INSN_BFS_COMPACT, SH_INSN_BRA_COMPACT, SH_INSN_BRAF_COMPACT
+ , SH_INSN_BRK_COMPACT, SH_INSN_BSR_COMPACT, SH_INSN_BSRF_COMPACT, SH_INSN_BT_COMPACT
+ , SH_INSN_BTS_COMPACT, SH_INSN_CLRMAC_COMPACT, SH_INSN_CLRS_COMPACT, SH_INSN_CLRT_COMPACT
+ , SH_INSN_CMPEQ_COMPACT, SH_INSN_CMPEQI_COMPACT, SH_INSN_CMPGE_COMPACT, SH_INSN_CMPGT_COMPACT
+ , SH_INSN_CMPHI_COMPACT, SH_INSN_CMPHS_COMPACT, SH_INSN_CMPPL_COMPACT, SH_INSN_CMPPZ_COMPACT
+ , SH_INSN_CMPSTR_COMPACT, SH_INSN_DIV0S_COMPACT, SH_INSN_DIV0U_COMPACT, SH_INSN_DIV1_COMPACT
+ , SH_INSN_DMULSL_COMPACT, SH_INSN_DMULUL_COMPACT, SH_INSN_DT_COMPACT, SH_INSN_EXTSB_COMPACT
+ , SH_INSN_EXTSW_COMPACT, SH_INSN_EXTUB_COMPACT, SH_INSN_EXTUW_COMPACT, SH_INSN_FABS_COMPACT
+ , SH_INSN_FADD_COMPACT, SH_INSN_FCMPEQ_COMPACT, SH_INSN_FCMPGT_COMPACT, SH_INSN_FCNVDS_COMPACT
+ , SH_INSN_FCNVSD_COMPACT, SH_INSN_FDIV_COMPACT, SH_INSN_FIPR_COMPACT, SH_INSN_FLDS_COMPACT
+ , SH_INSN_FLDI0_COMPACT, SH_INSN_FLDI1_COMPACT, SH_INSN_FLOAT_COMPACT, SH_INSN_FMAC_COMPACT
+ , SH_INSN_FMOV1_COMPACT, SH_INSN_FMOV2_COMPACT, SH_INSN_FMOV3_COMPACT, SH_INSN_FMOV4_COMPACT
+ , SH_INSN_FMOV5_COMPACT, SH_INSN_FMOV6_COMPACT, SH_INSN_FMOV7_COMPACT, SH_INSN_FMUL_COMPACT
+ , SH_INSN_FNEG_COMPACT, SH_INSN_FRCHG_COMPACT, SH_INSN_FSCHG_COMPACT, SH_INSN_FSQRT_COMPACT
+ , SH_INSN_FSTS_COMPACT, SH_INSN_FSUB_COMPACT, SH_INSN_FTRC_COMPACT, SH_INSN_FTRV_COMPACT
+ , SH_INSN_JMP_COMPACT, SH_INSN_JSR_COMPACT, SH_INSN_LDC_COMPACT, SH_INSN_LDCL_COMPACT
+ , SH_INSN_LDS_FPSCR_COMPACT, SH_INSN_LDSL_FPSCR_COMPACT, SH_INSN_LDS_FPUL_COMPACT, SH_INSN_LDSL_FPUL_COMPACT
+ , SH_INSN_LDS_MACH_COMPACT, SH_INSN_LDSL_MACH_COMPACT, SH_INSN_LDS_MACL_COMPACT, SH_INSN_LDSL_MACL_COMPACT
+ , SH_INSN_LDS_PR_COMPACT, SH_INSN_LDSL_PR_COMPACT, SH_INSN_MACL_COMPACT, SH_INSN_MACW_COMPACT
+ , SH_INSN_MOV_COMPACT, SH_INSN_MOVI_COMPACT, SH_INSN_MOVB1_COMPACT, SH_INSN_MOVB2_COMPACT
+ , SH_INSN_MOVB3_COMPACT, SH_INSN_MOVB4_COMPACT, SH_INSN_MOVB5_COMPACT, SH_INSN_MOVB6_COMPACT
+ , SH_INSN_MOVB7_COMPACT, SH_INSN_MOVB8_COMPACT, SH_INSN_MOVB9_COMPACT, SH_INSN_MOVB10_COMPACT
+ , SH_INSN_MOVL1_COMPACT, SH_INSN_MOVL2_COMPACT, SH_INSN_MOVL3_COMPACT, SH_INSN_MOVL4_COMPACT
+ , SH_INSN_MOVL5_COMPACT, SH_INSN_MOVL6_COMPACT, SH_INSN_MOVL7_COMPACT, SH_INSN_MOVL8_COMPACT
+ , SH_INSN_MOVL9_COMPACT, SH_INSN_MOVL10_COMPACT, SH_INSN_MOVL11_COMPACT, SH_INSN_MOVW1_COMPACT
+ , SH_INSN_MOVW2_COMPACT, SH_INSN_MOVW3_COMPACT, SH_INSN_MOVW4_COMPACT, SH_INSN_MOVW5_COMPACT
+ , SH_INSN_MOVW6_COMPACT, SH_INSN_MOVW7_COMPACT, SH_INSN_MOVW8_COMPACT, SH_INSN_MOVW9_COMPACT
+ , SH_INSN_MOVW10_COMPACT, SH_INSN_MOVW11_COMPACT, SH_INSN_MOVA_COMPACT, SH_INSN_MOVCAL_COMPACT
+ , SH_INSN_MOVT_COMPACT, SH_INSN_MULL_COMPACT, SH_INSN_MULSW_COMPACT, SH_INSN_MULUW_COMPACT
+ , SH_INSN_NEG_COMPACT, SH_INSN_NEGC_COMPACT, SH_INSN_NOP_COMPACT, SH_INSN_NOT_COMPACT
+ , SH_INSN_OCBI_COMPACT, SH_INSN_OCBP_COMPACT, SH_INSN_OCBWB_COMPACT, SH_INSN_OR_COMPACT
+ , SH_INSN_ORI_COMPACT, SH_INSN_ORB_COMPACT, SH_INSN_PREF_COMPACT, SH_INSN_ROTCL_COMPACT
+ , SH_INSN_ROTCR_COMPACT, SH_INSN_ROTL_COMPACT, SH_INSN_ROTR_COMPACT, SH_INSN_RTS_COMPACT
+ , SH_INSN_SETS_COMPACT, SH_INSN_SETT_COMPACT, SH_INSN_SHAD_COMPACT, SH_INSN_SHAL_COMPACT
+ , SH_INSN_SHAR_COMPACT, SH_INSN_SHLD_COMPACT, SH_INSN_SHLL_COMPACT, SH_INSN_SHLL2_COMPACT
+ , SH_INSN_SHLL8_COMPACT, SH_INSN_SHLL16_COMPACT, SH_INSN_SHLR_COMPACT, SH_INSN_SHLR2_COMPACT
+ , SH_INSN_SHLR8_COMPACT, SH_INSN_SHLR16_COMPACT, SH_INSN_STC_GBR_COMPACT, SH_INSN_STCL_GBR_COMPACT
+ , SH_INSN_STS_FPSCR_COMPACT, SH_INSN_STSL_FPSCR_COMPACT, SH_INSN_STS_FPUL_COMPACT, SH_INSN_STSL_FPUL_COMPACT
+ , SH_INSN_STS_MACH_COMPACT, SH_INSN_STSL_MACH_COMPACT, SH_INSN_STS_MACL_COMPACT, SH_INSN_STSL_MACL_COMPACT
+ , SH_INSN_STS_PR_COMPACT, SH_INSN_STSL_PR_COMPACT, SH_INSN_SUB_COMPACT, SH_INSN_SUBC_COMPACT
+ , SH_INSN_SUBV_COMPACT, SH_INSN_SWAPB_COMPACT, SH_INSN_SWAPW_COMPACT, SH_INSN_TASB_COMPACT
+ , SH_INSN_TRAPA_COMPACT, SH_INSN_TST_COMPACT, SH_INSN_TSTI_COMPACT, SH_INSN_TSTB_COMPACT
+ , SH_INSN_XOR_COMPACT, SH_INSN_XORI_COMPACT, SH_INSN_XORB_COMPACT, SH_INSN_XTRCT_COMPACT
+ , SH_INSN_ADD, SH_INSN_ADDL, SH_INSN_ADDI, SH_INSN_ADDIL
+ , SH_INSN_ADDZL, SH_INSN_ALLOCO, SH_INSN_AND, SH_INSN_ANDC
+ , SH_INSN_ANDI, SH_INSN_BEQ, SH_INSN_BEQI, SH_INSN_BGE
+ , SH_INSN_BGEU, SH_INSN_BGT, SH_INSN_BGTU, SH_INSN_BLINK
+ , SH_INSN_BNE, SH_INSN_BNEI, SH_INSN_BRK, SH_INSN_BYTEREV
+ , SH_INSN_CMPEQ, SH_INSN_CMPGT, SH_INSN_CMPGTU, SH_INSN_CMVEQ
+ , SH_INSN_CMVNE, SH_INSN_FABSD, SH_INSN_FABSS, SH_INSN_FADDD
+ , SH_INSN_FADDS, SH_INSN_FCMPEQD, SH_INSN_FCMPEQS, SH_INSN_FCMPGED
+ , SH_INSN_FCMPGES, SH_INSN_FCMPGTD, SH_INSN_FCMPGTS, SH_INSN_FCMPUND
+ , SH_INSN_FCMPUNS, SH_INSN_FCNVDS, SH_INSN_FCNVSD, SH_INSN_FDIVD
+ , SH_INSN_FDIVS, SH_INSN_FGETSCR, SH_INSN_FIPRS, SH_INSN_FLDD
+ , SH_INSN_FLDP, SH_INSN_FLDS, SH_INSN_FLDXD, SH_INSN_FLDXP
+ , SH_INSN_FLDXS, SH_INSN_FLOATLD, SH_INSN_FLOATLS, SH_INSN_FLOATQD
+ , SH_INSN_FLOATQS, SH_INSN_FMACS, SH_INSN_FMOVD, SH_INSN_FMOVDQ
+ , SH_INSN_FMOVLS, SH_INSN_FMOVQD, SH_INSN_FMOVS, SH_INSN_FMOVSL
+ , SH_INSN_FMULD, SH_INSN_FMULS, SH_INSN_FNEGD, SH_INSN_FNEGS
+ , SH_INSN_FPUTSCR, SH_INSN_FSQRTD, SH_INSN_FSQRTS, SH_INSN_FSTD
+ , SH_INSN_FSTP, SH_INSN_FSTS, SH_INSN_FSTXD, SH_INSN_FSTXP
+ , SH_INSN_FSTXS, SH_INSN_FSUBD, SH_INSN_FSUBS, SH_INSN_FTRCDL
+ , SH_INSN_FTRCSL, SH_INSN_FTRCDQ, SH_INSN_FTRCSQ, SH_INSN_FTRVS
+ , SH_INSN_GETCFG, SH_INSN_GETCON, SH_INSN_GETTR, SH_INSN_ICBI
+ , SH_INSN_LDB, SH_INSN_LDL, SH_INSN_LDQ, SH_INSN_LDUB
+ , SH_INSN_LDUW, SH_INSN_LDW, SH_INSN_LDHIL, SH_INSN_LDHIQ
+ , SH_INSN_LDLOL, SH_INSN_LDLOQ, SH_INSN_LDXB, SH_INSN_LDXL
+ , SH_INSN_LDXQ, SH_INSN_LDXUB, SH_INSN_LDXUW, SH_INSN_LDXW
+ , SH_INSN_MABSL, SH_INSN_MABSW, SH_INSN_MADDL, SH_INSN_MADDW
+ , SH_INSN_MADDSL, SH_INSN_MADDSUB, SH_INSN_MADDSW, SH_INSN_MCMPEQB
+ , SH_INSN_MCMPEQL, SH_INSN_MCMPEQW, SH_INSN_MCMPGTL, SH_INSN_MCMPGTUB
+ , SH_INSN_MCMPGTW, SH_INSN_MCMV, SH_INSN_MCNVSLW, SH_INSN_MCNVSWB
+ , SH_INSN_MCNVSWUB, SH_INSN_MEXTR1, SH_INSN_MEXTR2, SH_INSN_MEXTR3
+ , SH_INSN_MEXTR4, SH_INSN_MEXTR5, SH_INSN_MEXTR6, SH_INSN_MEXTR7
+ , SH_INSN_MMACFXWL, SH_INSN_MMACNFX_WL, SH_INSN_MMULL, SH_INSN_MMULW
+ , SH_INSN_MMULFXL, SH_INSN_MMULFXW, SH_INSN_MMULFXRPW, SH_INSN_MMULHIWL
+ , SH_INSN_MMULLOWL, SH_INSN_MMULSUMWQ, SH_INSN_MOVI, SH_INSN_MPERMW
+ , SH_INSN_MSADUBQ, SH_INSN_MSHALDSL, SH_INSN_MSHALDSW, SH_INSN_MSHARDL
+ , SH_INSN_MSHARDW, SH_INSN_MSHARDSQ, SH_INSN_MSHFHIB, SH_INSN_MSHFHIL
+ , SH_INSN_MSHFHIW, SH_INSN_MSHFLOB, SH_INSN_MSHFLOL, SH_INSN_MSHFLOW
+ , SH_INSN_MSHLLDL, SH_INSN_MSHLLDW, SH_INSN_MSHLRDL, SH_INSN_MSHLRDW
+ , SH_INSN_MSUBL, SH_INSN_MSUBW, SH_INSN_MSUBSL, SH_INSN_MSUBSUB
+ , SH_INSN_MSUBSW, SH_INSN_MULSL, SH_INSN_MULUL, SH_INSN_NOP
+ , SH_INSN_NSB, SH_INSN_OCBI, SH_INSN_OCBP, SH_INSN_OCBWB
+ , SH_INSN_OR, SH_INSN_ORI, SH_INSN_PREFI, SH_INSN_PTA
+ , SH_INSN_PTABS, SH_INSN_PTB, SH_INSN_PTREL, SH_INSN_PUTCFG
+ , SH_INSN_PUTCON, SH_INSN_RTE, SH_INSN_SHARD, SH_INSN_SHARDL
+ , SH_INSN_SHARI, SH_INSN_SHARIL, SH_INSN_SHLLD, SH_INSN_SHLLDL
+ , SH_INSN_SHLLI, SH_INSN_SHLLIL, SH_INSN_SHLRD, SH_INSN_SHLRDL
+ , SH_INSN_SHLRI, SH_INSN_SHLRIL, SH_INSN_SHORI, SH_INSN_SLEEP
+ , SH_INSN_STB, SH_INSN_STL, SH_INSN_STQ, SH_INSN_STW
+ , SH_INSN_STHIL, SH_INSN_STHIQ, SH_INSN_STLOL, SH_INSN_STLOQ
+ , SH_INSN_STXB, SH_INSN_STXL, SH_INSN_STXQ, SH_INSN_STXW
+ , SH_INSN_SUB, SH_INSN_SUBL, SH_INSN_SWAPQ, SH_INSN_SYNCI
+ , SH_INSN_SYNCO, SH_INSN_TRAPA, SH_INSN_XOR, SH_INSN_XORI
+ , SH_INSN_MAX
+} CGEN_INSN_TYPE;
+
+/* Index of `invalid' insn place holder. */
+#define CGEN_INSN_INVALID SH_INSN_INVALID
+
+/* Total number of insns in table. */
+#define MAX_INSNS ((int) SH_INSN_MAX)
+
+/* This struct records data prior to insertion or after extraction. */
+struct cgen_fields
+{
+ int length;
+ long f_nil;
+ long f_anyof;
+ long f_op4;
+ long f_op8;
+ long f_op16;
+ long f_sub4;
+ long f_sub8;
+ long f_sub10;
+ long f_rn;
+ long f_rm;
+ long f_8_1;
+ long f_disp8;
+ long f_disp12;
+ long f_imm8;
+ long f_imm4;
+ long f_imm4x2;
+ long f_imm4x4;
+ long f_imm8x2;
+ long f_imm8x4;
+ long f_dn;
+ long f_dm;
+ long f_vn;
+ long f_vm;
+ long f_xn;
+ long f_xm;
+ long f_op;
+ long f_ext;
+ long f_rsvd;
+ long f_left;
+ long f_right;
+ long f_dest;
+ long f_left_right;
+ long f_tra;
+ long f_trb;
+ long f_likely;
+ long f_25;
+ long f_8_2;
+ long f_imm6;
+ long f_imm10;
+ long f_imm16;
+ long f_uimm6;
+ long f_uimm16;
+ long f_disp6;
+ long f_disp6x32;
+ long f_disp10;
+ long f_disp10x8;
+ long f_disp10x4;
+ long f_disp10x2;
+ long f_disp16;
+};
+
+#define CGEN_INIT_PARSE(od) \
+{\
+}
+#define CGEN_INIT_INSERT(od) \
+{\
+}
+#define CGEN_INIT_EXTRACT(od) \
+{\
+}
+#define CGEN_INIT_PRINT(od) \
+{\
+}
+
+
+#endif /* SH_OPC_H */
--- /dev/null
+/* collection of junk waiting time to sort out
+ Copyright (C) 2000 Free Software Foundation, Inc.
+ Contributed by Red Hat, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#ifndef SH64_SIM_H
+#define SH64_SIM_H
+
+#define GETTWI GETTSI
+#define SETTWI SETTSI
+\f
+
+enum {
+ ISM_COMPACT, ISM_MEDIA
+};
+
+/* Hardware/device support. */
+extern device sh5_devices;
+
+/* FIXME: Temporary, until device support ready. */
+struct _device { int foo; };
+
+extern IDESC * sh64_idesc_media;
+extern IDESC * sh64_idesc_compact;
+
+/* Function prototypes from sh64.c. */
+
+BI sh64_endian (SIM_CPU *);
+VOID sh64_break (SIM_CPU *, PCADDR);
+VOID sh64_trapa (SIM_CPU *, DI, PCADDR);
+VOID sh64_compact_trapa (SIM_CPU *, UQI, PCADDR);
+
+SF sh64_fldi0 (SIM_CPU *);
+SF sh64_fldi1 (SIM_CPU *);
+DF sh64_fcnvsd (SIM_CPU *, SF);
+SF sh64_fcnvds (SIM_CPU *, DF);
+
+DF sh64_fabsd (SIM_CPU *, DF);
+SF sh64_fabss (SIM_CPU *, SF);
+DF sh64_faddd (SIM_CPU *, DF, DF);
+SF sh64_fadds (SIM_CPU *, SF, SF);
+DF sh64_fdivd (SIM_CPU *, DF, DF);
+SF sh64_fdivs (SIM_CPU *, SF, SF);
+DF sh64_floatld (SIM_CPU *, SF);
+SF sh64_floatls (SIM_CPU *, SF);
+DF sh64_floatqd (SIM_CPU *, DF);
+SF sh64_floatqs (SIM_CPU *, DF);
+SF sh64_fmacs(SIM_CPU *, SF, SF, SF);
+DF sh64_fmuld (SIM_CPU *, DF, DF);
+SF sh64_fmuls (SIM_CPU *, SF, SF);
+DF sh64_fnegd (SIM_CPU *, DF);
+SF sh64_fnegs (SIM_CPU *, SF);
+DF sh64_fsqrtd (SIM_CPU *, DF);
+SF sh64_fsqrts (SIM_CPU *, SF);
+DF sh64_fsubd (SIM_CPU *, DF, DF);
+SF sh64_fsubs (SIM_CPU *, SF, SF);
+SF sh64_ftrcdl (SIM_CPU *, DF);
+DF sh64_ftrcdq (SIM_CPU *, DF);
+SF sh64_ftrcsl (SIM_CPU *, SF);
+DF sh64_ftrcsq (SIM_CPU *, SF);
+VOID sh64_ftrvs (SIM_CPU *, unsigned, unsigned, unsigned);
+
+BI sh64_fcmpeqs (SIM_CPU *, SF, SF);
+BI sh64_fcmpeqd (SIM_CPU *, DF, DF);
+BI sh64_fcmpges (SIM_CPU *, SF, SF);
+BI sh64_fcmpged (SIM_CPU *, DF, DF);
+BI sh64_fcmpgts (SIM_CPU *, SF, SF);
+BI sh64_fcmpgtd (SIM_CPU *, DF, DF);
+BI sh64_fcmpund (SIM_CPU *, DF, DF);
+BI sh64_fcmpuns (SIM_CPU *, SF, SF);
+
+DI sh64_nsb (SIM_CPU *, DI);
+
+#endif /* SH64_SIM_H */
--- /dev/null
+/* SH5 simulator support code
+ Copyright (C) 2000, 2001 Free Software Foundation, Inc.
+ Contributed by Red Hat, Inc.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#define WANT_CPU
+#define WANT_CPU_SH64
+
+#include "sim-main.h"
+#include "sim-fpu.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+#include "callback.h"
+#include "defs-compact.h"
+
+#include "bfd.h"
+/* From include/. */
+#include "sim-sh64.h"
+
+#define SYS_exit 1
+#define SYS_read 3
+#define SYS_write 4
+#define SYS_open 5
+#define SYS_close 6
+#define SYS_lseek 19
+#define SYS_time 23
+#define SYS_argc 172
+#define SYS_argnlen 173
+#define SYS_argn 174
+
+IDESC * sh64_idesc_media;
+IDESC * sh64_idesc_compact;
+
+BI
+sh64_endian (SIM_CPU *current_cpu)
+{
+ return (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN);
+}
+
+SF
+sh64_fldi0 (SIM_CPU *current_cpu)
+{
+ SF result;
+ sim_fpu_to32 (&result, &sim_fpu_zero);
+ return result;
+}
+
+SF
+sh64_fldi1 (SIM_CPU *current_cpu)
+{
+ SF result;
+ sim_fpu_to32 (&result, &sim_fpu_one);
+ return result;
+}
+
+DF
+sh64_fabsd(SIM_CPU *current_cpu, DF drgh)
+{
+ DF result;
+ sim_fpu f, fres;
+
+ sim_fpu_64to (&f, drgh);
+ sim_fpu_abs (&fres, &f);
+ sim_fpu_to64 (&result, &fres);
+ return result;
+}
+
+SF
+sh64_fabss(SIM_CPU *current_cpu, SF frgh)
+{
+ SF result;
+ sim_fpu f, fres;
+
+ sim_fpu_32to (&f, frgh);
+ sim_fpu_abs (&fres, &f);
+ sim_fpu_to32 (&result, &fres);
+ return result;
+}
+
+DF
+sh64_faddd(SIM_CPU *current_cpu, DF drg, DF drh)
+{
+ DF result;
+ sim_fpu f1, f2, fres;
+
+ sim_fpu_64to (&f1, drg);
+ sim_fpu_64to (&f2, drh);
+ sim_fpu_add (&fres, &f1, &f2);
+ sim_fpu_to64 (&result, &fres);
+ return result;
+}
+
+SF
+sh64_fadds(SIM_CPU *current_cpu, SF frg, SF frh)
+{
+ SF result;
+ sim_fpu f1, f2, fres;
+
+ sim_fpu_32to (&f1, frg);
+ sim_fpu_32to (&f2, frh);
+ sim_fpu_add (&fres, &f1, &f2);
+ sim_fpu_to32 (&result, &fres);
+ return result;
+}
+
+BI
+sh64_fcmpeqd(SIM_CPU *current_cpu, DF drg, DF drh)
+{
+ sim_fpu f1, f2;
+
+ sim_fpu_64to (&f1, drg);
+ sim_fpu_64to (&f2, drh);
+ return sim_fpu_is_eq (&f1, &f2);
+}
+
+BI
+sh64_fcmpeqs(SIM_CPU *current_cpu, SF frg, SF frh)
+{
+ sim_fpu f1, f2;
+
+ sim_fpu_32to (&f1, frg);
+ sim_fpu_32to (&f2, frh);
+ return sim_fpu_is_eq (&f1, &f2);
+}
+
+BI
+sh64_fcmpged(SIM_CPU *current_cpu, DF drg, DF drh)
+{
+ sim_fpu f1, f2;
+
+ sim_fpu_64to (&f1, drg);
+ sim_fpu_64to (&f2, drh);
+ return sim_fpu_is_ge (&f1, &f2);
+}
+
+BI
+sh64_fcmpges(SIM_CPU *current_cpu, SF frg, SF frh)
+{
+ sim_fpu f1, f2;
+
+ sim_fpu_32to (&f1, frg);
+ sim_fpu_32to (&f2, frh);
+ return sim_fpu_is_ge (&f1, &f2);
+}
+
+BI
+sh64_fcmpgtd(SIM_CPU *current_cpu, DF drg, DF drh)
+{
+ sim_fpu f1, f2;
+
+ sim_fpu_64to (&f1, drg);
+ sim_fpu_64to (&f2, drh);
+ return sim_fpu_is_gt (&f1, &f2);
+}
+
+BI
+sh64_fcmpgts(SIM_CPU *current_cpu, SF frg, SF frh)
+{
+ sim_fpu f1, f2;
+
+ sim_fpu_32to (&f1, frg);
+ sim_fpu_32to (&f2, frh);
+ return sim_fpu_is_gt (&f1, &f2);
+}
+
+BI
+sh64_fcmpund(SIM_CPU *current_cpu, DF drg, DF drh)
+{
+ sim_fpu f1, f2;
+
+ sim_fpu_64to (&f1, drg);
+ sim_fpu_64to (&f2, drh);
+ return (sim_fpu_is_nan (&f1) || sim_fpu_is_nan (&f2));
+}
+
+BI
+sh64_fcmpuns(SIM_CPU *current_cpu, SF frg, SF frh)
+{
+ sim_fpu f1, f2;
+
+ sim_fpu_32to (&f1, frg);
+ sim_fpu_32to (&f2, frh);
+ return (sim_fpu_is_nan (&f1) || sim_fpu_is_nan (&f2));
+}
+
+SF
+sh64_fcnvds(SIM_CPU *current_cpu, DF drgh)
+{
+ union {
+ unsigned long long ll;
+ double d;
+ } f1;
+
+ union {
+ unsigned long l;
+ float f;
+ } f2;
+
+ f1.ll = drgh;
+ f2.f = (float) f1.d;
+
+ return (SF) f2.l;
+}
+
+DF
+sh64_fcnvsd(SIM_CPU *current_cpu, SF frgh)
+{
+ DF result;
+ sim_fpu f;
+
+ sim_fpu_32to (&f, frgh);
+ sim_fpu_to64 (&result, &f);
+ return result;
+}
+
+DF
+sh64_fdivd(SIM_CPU *current_cpu, DF drg, DF drh)
+{
+ DF result;
+ sim_fpu f1, f2, fres;
+
+ sim_fpu_64to (&f1, drg);
+ sim_fpu_64to (&f2, drh);
+ sim_fpu_div (&fres, &f1, &f2);
+ sim_fpu_to64 (&result, &fres);
+ return result;
+}
+
+SF
+sh64_fdivs(SIM_CPU *current_cpu, SF frg, SF frh)
+{
+ SF result;
+ sim_fpu f1, f2, fres;
+
+ sim_fpu_32to (&f1, frg);
+ sim_fpu_32to (&f2, frh);
+ sim_fpu_div (&fres, &f1, &f2);
+ sim_fpu_to32 (&result, &fres);
+ return result;
+}
+
+DF
+sh64_floatld(SIM_CPU *current_cpu, SF frgh)
+{
+ DF result;
+ sim_fpu f;
+
+ sim_fpu_i32to (&f, frgh, sim_fpu_round_default);
+ sim_fpu_to64 (&result, &f);
+ return result;
+}
+
+SF
+sh64_floatls(SIM_CPU *current_cpu, SF frgh)
+{
+ SF result;
+ sim_fpu f;
+
+ sim_fpu_i32to (&f, frgh, sim_fpu_round_default);
+ sim_fpu_to32 (&result, &f);
+ return result;
+}
+
+DF
+sh64_floatqd(SIM_CPU *current_cpu, DF drgh)
+{
+ DF result;
+ sim_fpu f;
+
+ sim_fpu_i64to (&f, drgh, sim_fpu_round_default);
+ sim_fpu_to64 (&result, &f);
+ return result;
+}
+
+SF
+sh64_floatqs(SIM_CPU *current_cpu, DF drgh)
+{
+ SF result;
+ sim_fpu f;
+
+ sim_fpu_i64to (&f, drgh, sim_fpu_round_default);
+ sim_fpu_to32 (&result, &f);
+ return result;
+}
+
+SF
+sh64_fmacs(SIM_CPU *current_cpu, SF fr0, SF frm, SF frn)
+{
+ SF result;
+ sim_fpu m1, m2, a1, fres;
+
+ sim_fpu_32to (&m1, fr0);
+ sim_fpu_32to (&m2, frm);
+ sim_fpu_32to (&a1, frn);
+
+ sim_fpu_mul (&fres, &m1, &m2);
+ sim_fpu_add (&fres, &fres, &a1);
+
+ sim_fpu_to32 (&result, &fres);
+ return result;
+}
+
+DF
+sh64_fmuld(SIM_CPU *current_cpu, DF drg, DF drh)
+{
+ DF result;
+ sim_fpu f1, f2, fres;
+
+ sim_fpu_64to (&f1, drg);
+ sim_fpu_64to (&f2, drh);
+ sim_fpu_mul (&fres, &f1, &f2);
+ sim_fpu_to64 (&result, &fres);
+ return result;
+}
+
+SF
+sh64_fmuls(SIM_CPU *current_cpu, SF frg, SF frh)
+{
+ SF result;
+ sim_fpu f1, f2, fres;
+
+ sim_fpu_32to (&f1, frg);
+ sim_fpu_32to (&f2, frh);
+ sim_fpu_mul (&fres, &f1, &f2);
+ sim_fpu_to32 (&result, &fres);
+ return result;
+}
+
+DF
+sh64_fnegd(SIM_CPU *current_cpu, DF drgh)
+{
+ DF result;
+ sim_fpu f1, f2;
+
+ sim_fpu_64to (&f1, drgh);
+ sim_fpu_neg (&f2, &f1);
+ sim_fpu_to64 (&result, &f2);
+ return result;
+}
+
+SF
+sh64_fnegs(SIM_CPU *current_cpu, SF frgh)
+{
+ SF result;
+ sim_fpu f, fres;
+
+ sim_fpu_32to (&f, frgh);
+ sim_fpu_neg (&fres, &f);
+ sim_fpu_to32 (&result, &fres);
+ return result;
+}
+
+DF
+sh64_fsqrtd(SIM_CPU *current_cpu, DF drgh)
+{
+ DF result;
+ sim_fpu f, fres;
+
+ sim_fpu_64to (&f, drgh);
+ sim_fpu_sqrt (&fres, &f);
+ sim_fpu_to64 (&result, &fres);
+ return result;
+}
+
+SF
+sh64_fsqrts(SIM_CPU *current_cpu, SF frgh)
+{
+ SF result;
+ sim_fpu f, fres;
+
+ sim_fpu_32to (&f, frgh);
+ sim_fpu_sqrt (&fres, &f);
+ sim_fpu_to32 (&result, &fres);
+ return result;
+}
+
+DF
+sh64_fsubd(SIM_CPU *current_cpu, DF drg, DF drh)
+{
+ DF result;
+ sim_fpu f1, f2, fres;
+
+ sim_fpu_64to (&f1, drg);
+ sim_fpu_64to (&f2, drh);
+ sim_fpu_sub (&fres, &f1, &f2);
+ sim_fpu_to64 (&result, &fres);
+ return result;
+}
+
+SF
+sh64_fsubs(SIM_CPU *current_cpu, SF frg, SF frh)
+{
+ SF result;
+ sim_fpu f1, f2, fres;
+
+ sim_fpu_32to (&f1, frg);
+ sim_fpu_32to (&f2, frh);
+ sim_fpu_sub (&fres, &f1, &f2);
+ sim_fpu_to32 (&result, &fres);
+ return result;
+}
+
+SF
+sh64_ftrcdl(SIM_CPU *current_cpu, DF drgh)
+{
+ SI result;
+ sim_fpu f;
+
+ sim_fpu_64to (&f, drgh);
+ sim_fpu_to32i (&result, &f, sim_fpu_round_zero);
+ return (SF) result;
+}
+
+SF
+sh64_ftrcsl(SIM_CPU *current_cpu, SF frgh)
+{
+ SI result;
+ sim_fpu f;
+
+ sim_fpu_32to (&f, frgh);
+ sim_fpu_to32i (&result, &f, sim_fpu_round_zero);
+ return (SF) result;
+}
+
+DF
+sh64_ftrcdq(SIM_CPU *current_cpu, DF drgh)
+{
+ DI result;
+ sim_fpu f;
+
+ sim_fpu_64to (&f, drgh);
+ sim_fpu_to64i (&result, &f, sim_fpu_round_zero);
+ return (DF) result;
+}
+
+DF
+sh64_ftrcsq(SIM_CPU *current_cpu, SF frgh)
+{
+ DI result;
+ sim_fpu f;
+
+ sim_fpu_32to (&f, frgh);
+ sim_fpu_to64i (&result, &f, sim_fpu_round_zero);
+ return (DF) result;
+}
+
+void
+sh64_ftrvs(SIM_CPU *cpu, unsigned g, unsigned h, unsigned f)
+{
+ int i, j;
+
+ for (i = 0; i < 4; i++)
+ {
+ SF result;
+ sim_fpu sum;
+ sim_fpu_32to (&sum, 0);
+
+ for (j = 0; j < 4; j++)
+ {
+ sim_fpu f1, f2, temp;
+ sim_fpu_32to (&f1, sh64_h_fr_get (cpu, (g + i) + (j * 4)));
+ sim_fpu_32to (&f2, sh64_h_fr_get (cpu, h + j));
+ sim_fpu_mul (&temp, &f1, &f2);
+ sim_fpu_add (&sum, &sum, &temp);
+ }
+ sim_fpu_to32 (&result, &sum);
+ sh64_h_fr_set (cpu, f + i, result);
+ }
+}
+
+/* Count the number of arguments. */
+static int
+count_argc (cpu)
+ SIM_CPU *cpu;
+{
+ int i = 0;
+
+ if (! STATE_PROG_ARGV (CPU_STATE (cpu)))
+ return -1;
+
+ while (STATE_PROG_ARGV (CPU_STATE (cpu)) [i] != NULL)
+ ++i;
+
+ return i;
+}
+
+/* Read a null terminated string from memory, return in a buffer */
+static char *
+fetch_str (current_cpu, pc, addr)
+ SIM_CPU *current_cpu;
+ PCADDR pc;
+ DI addr;
+{
+ char *buf;
+ int nr = 0;
+ while (sim_core_read_1 (current_cpu,
+ pc, read_map, addr + nr) != 0)
+ nr++;
+ buf = NZALLOC (char, nr + 1);
+ sim_read (CPU_STATE (current_cpu), addr, buf, nr);
+ return buf;
+}
+
+static void
+trap_handler (SIM_CPU *current_cpu, int shmedia_abi_p, UQI trapnum, PCADDR pc)
+{
+ char ch;
+ switch (trapnum)
+ {
+ case 1:
+ ch = GET_H_GRC (0);
+ sim_io_write_stdout (CPU_STATE (current_cpu), &ch, 1);
+ fflush (stdout);
+ break;
+ case 2:
+ sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
+ break;
+ case 34:
+ {
+ int i;
+ int ret_reg = (shmedia_abi_p) ? 2 : 0;
+ char *buf;
+ DI PARM1 = GET_H_GR ((shmedia_abi_p) ? 3 : 5);
+ DI PARM2 = GET_H_GR ((shmedia_abi_p) ? 4 : 6);
+ DI PARM3 = GET_H_GR ((shmedia_abi_p) ? 5 : 7);
+
+ switch (GET_H_GR ((shmedia_abi_p) ? 2 : 4))
+ {
+ case SYS_write:
+ buf = zalloc (PARM3);
+ sim_read (CPU_STATE (current_cpu), PARM2, buf, PARM3);
+ SET_H_GR (ret_reg,
+ sim_io_write (CPU_STATE (current_cpu),
+ PARM1, buf, PARM3));
+ zfree (buf);
+ break;
+
+ case SYS_lseek:
+ SET_H_GR (ret_reg,
+ sim_io_lseek (CPU_STATE (current_cpu),
+ PARM1, PARM2, PARM3));
+ break;
+
+ case SYS_exit:
+ sim_engine_halt (CPU_STATE (current_cpu), current_cpu,
+ NULL, pc, sim_exited, PARM1);
+ break;
+
+ case SYS_read:
+ buf = zalloc (PARM3);
+ SET_H_GR (ret_reg,
+ sim_io_read (CPU_STATE (current_cpu),
+ PARM1, buf, PARM3));
+ sim_write (CPU_STATE (current_cpu), PARM2, buf, PARM3);
+ zfree (buf);
+ break;
+
+ case SYS_open:
+ buf = fetch_str (current_cpu, pc, PARM1);
+ SET_H_GR (ret_reg,
+ sim_io_open (CPU_STATE (current_cpu),
+ buf, PARM2));
+ zfree (buf);
+ break;
+
+ case SYS_close:
+ SET_H_GR (ret_reg,
+ sim_io_close (CPU_STATE (current_cpu), PARM1));
+ break;
+
+ case SYS_time:
+ SET_H_GR (ret_reg, time (0));
+ break;
+
+ case SYS_argc:
+ SET_H_GR (ret_reg, count_argc (current_cpu));
+ break;
+
+ case SYS_argnlen:
+ if (PARM1 < count_argc (current_cpu))
+ SET_H_GR (ret_reg,
+ strlen (STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1]));
+ else
+ SET_H_GR (ret_reg, -1);
+ break;
+
+ case SYS_argn:
+ if (PARM1 < count_argc (current_cpu))
+ {
+ /* Include the NULL byte. */
+ i = strlen (STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1]) + 1;
+ sim_write (CPU_STATE (current_cpu),
+ PARM2,
+ STATE_PROG_ARGV (CPU_STATE (current_cpu)) [PARM1],
+ i);
+
+ /* Just for good measure. */
+ SET_H_GR (ret_reg, i);
+ break;
+ }
+ else
+ SET_H_GR (ret_reg, -1);
+ break;
+
+ default:
+ SET_H_GR (ret_reg, -1);
+ }
+ }
+ break;
+ case 253:
+ puts ("pass");
+ exit (0);
+ case 254:
+ puts ("fail");
+ exit (1);
+ case 0xc3:
+ /* fall through. */
+ case 255:
+ sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
+ break;
+ }
+}
+
+void
+sh64_trapa (SIM_CPU *current_cpu, DI rm, PCADDR pc)
+{
+ trap_handler (current_cpu, 1, (UQI) rm & 0xff, pc);
+}
+
+void
+sh64_compact_trapa (SIM_CPU *current_cpu, UQI trapnum, PCADDR pc)
+{
+ int mach_sh5_p;
+
+ /* If this is an SH5 executable, this is SHcompact code running in
+ the SHmedia ABI. */
+
+ mach_sh5_p =
+ (bfd_get_mach (STATE_PROG_BFD (CPU_STATE (current_cpu))) == bfd_mach_sh5);
+
+ trap_handler (current_cpu, mach_sh5_p, trapnum, pc);
+}
+
+DI
+sh64_nsb (SIM_CPU *current_cpu, DI rm)
+{
+ int result = 0, count;
+ UDI source = (UDI) rm;
+
+ if ((source >> 63))
+ source = ~source;
+ source <<= 1;
+
+ for (count = 32; count; count >>= 1)
+ {
+ UDI newval = source << count;
+
+ if ((newval >> count) == source)
+ {
+ result |= count;
+ source = newval;
+ }
+ }
+
+ return result;
+}
+
+void
+sh64_break (SIM_CPU *current_cpu, PCADDR pc)
+{
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
+}
+
+void
+set_isa (SIM_CPU *current_cpu, int mode)
+{
+ /* Do nothing. */
+}
+
+/* The semantic code invokes this for invalid (unrecognized) instructions. */
+
+SEM_PC
+sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
+{
+ SIM_DESC sd = CPU_STATE (current_cpu);
+ sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
+
+ return vpc;
+}
+
+
+/* Process an address exception. */
+
+void
+sh64_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
+ unsigned int map, int nr_bytes, address_word addr,
+ transfer_type transfer, sim_core_signals sig)
+{
+ sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
+ transfer, sig);
+}
+
+
+/* Initialize cycle counting for an insn.
+ FIRST_P is non-zero if this is the first insn in a set of parallel
+ insns. */
+
+void
+sh64_compact_model_insn_before (SIM_CPU *cpu, int first_p)
+{
+ /* Do nothing. */
+}
+
+void
+sh64_media_model_insn_before (SIM_CPU *cpu, int first_p)
+{
+ /* Do nothing. */
+}
+
+/* Record the cycles computed for an insn.
+ LAST_P is non-zero if this is the last insn in a set of parallel insns,
+ and we update the total cycle count.
+ CYCLES is the cycle count of the insn. */
+
+void
+sh64_compact_model_insn_after(SIM_CPU *cpu, int last_p, int cycles)
+{
+ /* Do nothing. */
+}
+
+void
+sh64_media_model_insn_after(SIM_CPU *cpu, int last_p, int cycles)
+{
+ /* Do nothing. */
+}
+
+int
+sh64_fetch_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
+{
+ /* Fetch general purpose registers. */
+ if (nr >= SIM_SH64_R0_REGNUM
+ && nr < (SIM_SH64_R0_REGNUM + SIM_SH64_NR_R_REGS)
+ && len == 8)
+ {
+ *((unsigned64*) buf) =
+ H2T_8 (sh64_h_gr_get (cpu, nr - SIM_SH64_R0_REGNUM));
+ return len;
+ }
+
+ /* Fetch PC. */
+ if (nr == SIM_SH64_PC_REGNUM && len == 8)
+ {
+ *((unsigned64*) buf) = H2T_8 (sh64_h_pc_get (cpu) | sh64_h_ism_get (cpu));
+ return len;
+ }
+
+ /* Fetch status register (SR). */
+ if (nr == SIM_SH64_SR_REGNUM && len == 8)
+ {
+ *((unsigned64*) buf) = H2T_8 (sh64_h_sr_get (cpu));
+ return len;
+ }
+
+ /* Fetch saved status register (SSR) and PC (SPC). */
+ if ((nr == SIM_SH64_SSR_REGNUM || nr == SIM_SH64_SPC_REGNUM)
+ && len == 8)
+ {
+ *((unsigned64*) buf) = 0;
+ return len;
+ }
+
+ /* Fetch target registers. */
+ if (nr >= SIM_SH64_TR0_REGNUM
+ && nr < (SIM_SH64_TR0_REGNUM + SIM_SH64_NR_TR_REGS)
+ && len == 8)
+ {
+ *((unsigned64*) buf) =
+ H2T_8 (sh64_h_tr_get (cpu, nr - SIM_SH64_TR0_REGNUM));
+ return len;
+ }
+
+ /* Fetch floating point registers. */
+ if (nr >= SIM_SH64_FR0_REGNUM
+ && nr < (SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS)
+ && len == 4)
+ {
+ *((unsigned32*) buf) =
+ H2T_4 (sh64_h_fr_get (cpu, nr - SIM_SH64_FR0_REGNUM));
+ return len;
+ }
+
+ /* We should never get here. */
+ return 0;
+}
+
+int
+sh64_store_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len)
+{
+ /* Store general purpose registers. */
+ if (nr >= SIM_SH64_R0_REGNUM
+ && nr < (SIM_SH64_R0_REGNUM + SIM_SH64_NR_R_REGS)
+ && len == 8)
+ {
+ sh64_h_gr_set (cpu, nr - SIM_SH64_R0_REGNUM, T2H_8 (*((unsigned64*)buf)));
+ return len;
+ }
+
+ /* Store PC. */
+ if (nr == SIM_SH64_PC_REGNUM && len == 8)
+ {
+ unsigned64 new_pc = T2H_8 (*((unsigned64*)buf));
+ sh64_h_pc_set (cpu, new_pc);
+ return len;
+ }
+
+ /* Store status register (SR). */
+ if (nr == SIM_SH64_SR_REGNUM && len == 8)
+ {
+ sh64_h_sr_set (cpu, T2H_8 (*((unsigned64*)buf)));
+ return len;
+ }
+
+ /* Store saved status register (SSR) and PC (SPC). */
+ if (nr == SIM_SH64_SSR_REGNUM || nr == SIM_SH64_SPC_REGNUM)
+ {
+ /* Do nothing. */
+ return len;
+ }
+
+ /* Store target registers. */
+ if (nr >= SIM_SH64_TR0_REGNUM
+ && nr < (SIM_SH64_TR0_REGNUM + SIM_SH64_NR_TR_REGS)
+ && len == 8)
+ {
+ sh64_h_tr_set (cpu, nr - SIM_SH64_TR0_REGNUM, T2H_8 (*((unsigned64*)buf)));
+ return len;
+ }
+
+ /* Store floating point registers. */
+ if (nr >= SIM_SH64_FR0_REGNUM
+ && nr < (SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS)
+ && len == 4)
+ {
+ sh64_h_fr_set (cpu, nr - SIM_SH64_FR0_REGNUM, T2H_4 (*((unsigned32*)buf)));
+ return len;
+ }
+
+ /* We should never get here. */
+ return 0;
+}
+
+void
+sh64_engine_run_full(SIM_CPU *cpu)
+{
+ if (sh64_h_ism_get (cpu) == ISM_MEDIA)
+ {
+ if (!sh64_idesc_media)
+ {
+ sh64_media_init_idesc_table (cpu);
+ sh64_idesc_media = CPU_IDESC (cpu);
+ }
+ else
+ CPU_IDESC (cpu) = sh64_idesc_media;
+ sh64_media_engine_run_full (cpu);
+ }
+ else
+ {
+ if (!sh64_idesc_compact)
+ {
+ sh64_compact_init_idesc_table (cpu);
+ sh64_idesc_compact = CPU_IDESC (cpu);
+ }
+ else
+ CPU_IDESC (cpu) = sh64_idesc_compact;
+ sh64_compact_engine_run_full (cpu);
+ }
+}
+
+void
+sh64_engine_run_fast (SIM_CPU *cpu)
+{
+ if (sh64_h_ism_get (cpu) == ISM_MEDIA)
+ {
+ if (!sh64_idesc_media)
+ {
+ sh64_media_init_idesc_table (cpu);
+ sh64_idesc_media = CPU_IDESC (cpu);
+ }
+ else
+ CPU_IDESC (cpu) = sh64_idesc_media;
+ sh64_media_engine_run_fast (cpu);
+ }
+ else
+ {
+ if (!sh64_idesc_compact)
+ {
+ sh64_compact_init_idesc_table (cpu);
+ sh64_idesc_compact = CPU_IDESC (cpu);
+ }
+ else
+ CPU_IDESC (cpu) = sh64_idesc_compact;
+ sh64_compact_engine_run_fast (cpu);
+ }
+}
+
+static void
+sh64_prepare_run (SIM_CPU *cpu)
+{
+ /* Nothing. */
+}
+
+static const CGEN_INSN *
+sh64_get_idata (SIM_CPU *cpu, int inum)
+{
+ return CPU_IDESC (cpu) [inum].idata;
+}
+
+static void
+sh64_init_cpu (SIM_CPU *cpu)
+{
+ CPU_REG_FETCH (cpu) = sh64_fetch_register;
+ CPU_REG_STORE (cpu) = sh64_store_register;
+ CPU_PC_FETCH (cpu) = sh64_h_pc_get;
+ CPU_PC_STORE (cpu) = sh64_h_pc_set;
+ CPU_GET_IDATA (cpu) = sh64_get_idata;
+ /* Only used by profiling. 0 disables it. */
+ CPU_MAX_INSNS (cpu) = 0;
+ CPU_INSN_NAME (cpu) = cgen_insn_name;
+ CPU_FULL_ENGINE_FN (cpu) = sh64_engine_run_full;
+#if WITH_FAST
+ CPU_FAST_ENGINE_FN (cpu) = sh64_engine_run_fast;
+#else
+ CPU_FAST_ENGINE_FN (cpu) = sh64_engine_run_full;
+#endif
+}
+
+static void
+shmedia_init_cpu (SIM_CPU *cpu)
+{
+ sh64_init_cpu (cpu);
+}
+
+static void
+shcompact_init_cpu (SIM_CPU *cpu)
+{
+ sh64_init_cpu (cpu);
+}
+
+static void
+sh64_model_init()
+{
+ /* Do nothing. */
+}
+
+static const MODEL sh_models [] =
+{
+ { "sh2", & sh2_mach, MODEL_SH5, NULL, sh64_model_init },
+ { "sh3", & sh3_mach, MODEL_SH5, NULL, sh64_model_init },
+ { "sh3e", & sh3_mach, MODEL_SH5, NULL, sh64_model_init },
+ { "sh4", & sh4_mach, MODEL_SH5, NULL, sh64_model_init },
+ { "sh5", & sh5_mach, MODEL_SH5, NULL, sh64_model_init },
+ { 0 }
+};
+
+static const MACH_IMP_PROPERTIES sh5_imp_properties =
+{
+ sizeof (SIM_CPU),
+#if WITH_SCACHE
+ sizeof (SCACHE)
+#else
+ 0
+#endif
+};
+
+const MACH sh2_mach =
+{
+ "sh2", "sh2", MACH_SH5,
+ 16, 16, &sh_models[0], &sh5_imp_properties,
+ shcompact_init_cpu,
+ sh64_prepare_run
+};
+
+const MACH sh3_mach =
+{
+ "sh3", "sh3", MACH_SH5,
+ 16, 16, &sh_models[1], &sh5_imp_properties,
+ shcompact_init_cpu,
+ sh64_prepare_run
+};
+
+const MACH sh3e_mach =
+{
+ "sh3e", "sh3e", MACH_SH5,
+ 16, 16, &sh_models[2], &sh5_imp_properties,
+ shcompact_init_cpu,
+ sh64_prepare_run
+};
+
+const MACH sh4_mach =
+{
+ "sh4", "sh4", MACH_SH5,
+ 16, 16, &sh_models[3], &sh5_imp_properties,
+ shcompact_init_cpu,
+ sh64_prepare_run
+};
+
+const MACH sh5_mach =
+{
+ "sh5", "sh5", MACH_SH5,
+ 32, 32, &sh_models[4], &sh5_imp_properties,
+ shmedia_init_cpu,
+ sh64_prepare_run
+};
--- /dev/null
+/* Main simulator entry points specific to the SH5.
+ Copyright (C) 2000 Free Software Foundation, Inc.
+ Contributed by Cygnus Solutions.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#include "libiberty.h"
+#include "bfd.h"
+#include "sim-main.h"
+#ifdef HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+#include "sim-options.h"
+#include "dis-asm.h"
+
+static void free_state (SIM_DESC);
+
+/* Since we don't build the cgen-opcode table, we use a wrapper around
+ the existing disassembler from libopcodes. */
+static CGEN_DISASSEMBLER sh64_disassemble_insn;
+
+/* Records simulator descriptor so utilities like sh5_dump_regs can be
+ called from gdb. */
+SIM_DESC current_state;
+\f
+/* Cover function of sim_state_free to free the cpu buffers as well. */
+
+static void
+free_state (SIM_DESC sd)
+{
+ if (STATE_MODULES (sd) != NULL)
+ sim_module_uninstall (sd);
+ sim_cpu_free_all (sd);
+ sim_state_free (sd);
+}
+
+/* Create an instance of the simulator. */
+
+SIM_DESC
+sim_open (kind, callback, abfd, argv)
+ SIM_OPEN_KIND kind;
+ host_callback *callback;
+ struct _bfd *abfd;
+ char **argv;
+{
+ char c;
+ int i;
+ SIM_DESC sd = sim_state_alloc (kind, callback);
+
+ /* The cpu data is kept in a separately allocated chunk of memory. */
+ if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+#if 0 /* FIXME: pc is in mach-specific struct */
+ /* FIXME: watchpoints code shouldn't need this */
+ {
+ SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+ STATE_WATCHPOINTS (sd)->pc = &(PC);
+ STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
+ }
+#endif
+
+ if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+#if 0 /* FIXME: 'twould be nice if we could do this */
+ /* These options override any module options.
+ Obviously ambiguity should be avoided, however the caller may wish to
+ augment the meaning of an option. */
+ if (extra_options != NULL)
+ sim_add_option_table (sd, extra_options);
+#endif
+
+ /* getopt will print the error message so we just have to exit if this fails.
+ FIXME: Hmmm... in the case of gdb we need getopt to call
+ print_filtered. */
+ if (sim_parse_args (sd, argv) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ /* Allocate core managed memory if none specified by user.
+ Use address 4 here in case the user wanted address 0 unmapped. */
+ if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
+ sim_do_commandf (sd, "memory region 0,0x%x", SH64_DEFAULT_MEM_SIZE);
+
+ /* Add a small memory region way up in the address space to handle
+ writes to invalidate an instruction cache line. This is used for
+ trampolines. Since we don't simulate the cache, this memory just
+ avoids bus errors. 64K ought to do. */
+ sim_do_command (sd," memory region 0xf0000000,0x10000");
+
+ /* check for/establish the reference program image */
+ if (sim_analyze_program (sd,
+ (STATE_PROG_ARGV (sd) != NULL
+ ? *STATE_PROG_ARGV (sd)
+ : NULL),
+ abfd) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ /* Establish any remaining configuration options. */
+ if (sim_config (sd) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ if (sim_post_argv_init (sd) != SIM_RC_OK)
+ {
+ free_state (sd);
+ return 0;
+ }
+
+ /* Open a copy of the cpu descriptor table. */
+ {
+ CGEN_CPU_DESC cd = sh_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
+ CGEN_ENDIAN_BIG);
+
+ for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+ {
+ SIM_CPU *cpu = STATE_CPU (sd, i);
+ CPU_CPU_DESC (cpu) = cd;
+ CPU_DISASSEMBLER (cpu) = sh64_disassemble_insn;
+ }
+ }
+
+ /* Clear idesc table pointers for good measure. */
+ sh64_idesc_media = sh64_idesc_compact = NULL;
+
+ /* Initialize various cgen things not done by common framework.
+ Must be done after sh_cgen_cpu_open. */
+ cgen_init (sd);
+
+ /* Store in a global so things like sparc32_dump_regs can be invoked
+ from the gdb command line. */
+ current_state = sd;
+
+ return sd;
+}
+
+void
+sim_close (sd, quitting)
+ SIM_DESC sd;
+ int quitting;
+{
+ sh_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0)));
+ sim_module_uninstall (sd);
+}
+\f
+SIM_RC
+sim_create_inferior (sd, abfd, argv, envp)
+ SIM_DESC sd;
+ struct _bfd *abfd;
+ char **argv;
+ char **envp;
+{
+ SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+ SIM_ADDR addr;
+
+ if (abfd != NULL)
+ addr = bfd_get_start_address (abfd);
+ else
+ addr = 0;
+ sim_pc_set (current_cpu, addr);
+
+#if 0
+ STATE_ARGV (sd) = sim_copy_argv (argv);
+ STATE_ENVP (sd) = sim_copy_argv (envp);
+#endif
+
+ return SIM_RC_OK;
+}
+
+void
+sim_do_command (sd, cmd)
+ SIM_DESC sd;
+ char *cmd;
+{
+ if (sim_args_command (sd, cmd) != SIM_RC_OK)
+ sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
+}
+
+\f
+/* Disassemble an instruction. */
+
+static void
+sh64_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
+ const ARGBUF *abuf, IADDR pc, char *buf)
+{
+ struct disassemble_info disasm_info;
+ SFILE sfile;
+ SIM_DESC sd = CPU_STATE (cpu);
+
+ sfile.buffer = sfile.current = buf;
+ INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
+ (fprintf_ftype) sim_disasm_sprintf);
+
+ disasm_info.arch = bfd_get_arch (STATE_PROG_BFD (sd));
+ disasm_info.mach = bfd_get_mach (STATE_PROG_BFD (sd));
+ disasm_info.endian =
+ (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
+ : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
+ : BFD_ENDIAN_UNKNOWN);
+ disasm_info.read_memory_func = sim_disasm_read_memory;
+ disasm_info.memory_error_func = sim_disasm_perror_memory;
+ disasm_info.application_data = (PTR) cpu;
+
+ if (sh64_h_ism_get (cpu) == ISM_MEDIA)
+ print_insn_sh64x_media (pc, &disasm_info);
+ else
+ switch (disasm_info.endian)
+ {
+ case BFD_ENDIAN_BIG:
+ print_insn_sh (pc, &disasm_info);
+ break;
+ case BFD_ENDIAN_LITTLE:
+ print_insn_shl (pc, &disasm_info);
+ break;
+ default:
+ abort();
+ }
+}
--- /dev/null
+/* Main header for the Hitachi SH64 architecture. */
+
+#ifndef SIM_MAIN_H
+#define SIM_MAIN_H
+
+#define USING_SIM_BASE_H /* FIXME: quick hack */
+
+struct _sim_cpu; /* FIXME: should be in sim-basics.h */
+typedef struct _sim_cpu SIM_CPU;
+
+/* sim-basics.h includes config.h but cgen-types.h must be included before
+ sim-basics.h and cgen-types.h needs config.h. */
+#include "config.h"
+
+#include "symcat.h"
+#include "sim-basics.h"
+#include "cgen-types.h"
+#include "sh-desc.h"
+#include "sh-opc.h"
+#include "arch.h"
+
+/* These must be defined before sim-base.h. */
+typedef UDI sim_cia;
+
+#define CIA_GET(cpu) CPU_PC_GET (cpu)
+#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val) | (sh64_h_ism_get (cpu)))
+
+#include "sim-base.h"
+#include "cgen-sim.h"
+#include "sh64-sim.h"
+\f
+/* The _sim_cpu struct. */
+
+struct _sim_cpu {
+ /* sim/common cpu base. */
+ sim_cpu_base base;
+
+ /* Static parts of cgen. */
+ CGEN_CPU cgen_cpu;
+
+ /* CPU specific parts go here.
+ Note that in files that don't need to access these pieces WANT_CPU_FOO
+ won't be defined and thus these parts won't appear. This is ok in the
+ sense that things work. It is a source of bugs though.
+ One has to of course be careful to not take the size of this
+ struct and no structure members accessed in non-cpu specific files can
+ go after here. Oh for a better language. */
+#if defined (WANT_CPU_SH64)
+ SH64_CPU_DATA cpu_data;
+#endif
+};
+\f
+/* The sim_state struct. */
+
+struct sim_state {
+ sim_cpu *cpu;
+#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
+
+ CGEN_STATE cgen_state;
+
+ sim_state_base base;
+};
+\f
+/* Misc. */
+
+/* Catch address exceptions. */
+extern SIM_CORE_SIGNAL_FN sh64_core_signal;
+#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
+sh64_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
+ (TRANSFER), (ERROR))
+
+/* Default memory size. */
+#define SH64_DEFAULT_MEM_SIZE 0x800000 /* 8M */
+
+#endif /* SIM_MAIN_H */
--- /dev/null
+/* SH64 target configuration file. -*- C -*- */
+
+/* Define this if the simulator can vary the size of memory.
+ See the xxx simulator for an example.
+ This enables the `-m size' option.
+ The memory size is stored in STATE_MEM_SIZE. */
+/* Not used for SH64 since we use the memory module. TODO -- check this */
+/* #define SIM_HAVE_MEM_SIZE */
+
+/* See sim-hload.c. We properly handle LMA. -- TODO: check this */
+#define SIM_HANDLES_LMA 1
+
+/* For MSPR support. FIXME: revisit. */
+#define WITH_DEVICES 0
+
+/* FIXME: Revisit. */
+#ifdef HAVE_DV_SOCKSER
+MODULE_INSTALL_FN dv_sockser_install;
+#define MODULE_LIST dv_sockser_install,
+#endif
+
+#if 0
+/* Enable watchpoints. */
+#define WITH_WATCHPOINTS 1
+#endif
+
+/* ??? Temporary hack until model support unified. */
+#define SIM_HAVE_MODEL
+
+/* Define this to enable the intrinsic breakpoint mechanism. */
+/* FIXME: may be able to remove SIM_HAVE_BREAKPOINTS since it essentially
+ duplicates ifdef SIM_BREAKPOINT (right?) */
+#if 1
+#define SIM_HAVE_BREAKPOINTS
+#define SIM_BREAKPOINT { 0, 0, 0, 0xD }
+#define SIM_BREAKPOINT_SIZE 4
+#endif
+
+/* This is a global setting. Different cpu families can't mix-n-match -scache
+ and -pbb. However some cpu families may use -simple while others use
+ one of -scache/-pbb. ???? */
+#define WITH_SCACHE_PBB 1
+
+/* Define this if the target cpu is bi-endian and the simulator supports it. */
+#define SIM_HAVE_BIENDIAN
--- /dev/null
+2001-01-06 Ben Elliston <bje@redhat.com>
+
+ * misc/fr-dr.s: New test.
+
+2001-01-03 Ben Elliston <bje@redhat.com>
+
+ * interwork.exp: Match .s files only.
+
+2000-12-06 Ben Elliston <bje@redhat.com>
+
+ * interwork.exp: New test case.
+
+2000-11-16 Ben Elliston <bje@redhat.com>
+
+ * allinsn.exp: Rename from this ..
+ * compact.exp: .. to this.
+ * media.exp: New test case.
+
+2000-11-13 Ben Elliston <bje@redhat.com>
+
+ * allinsn.exp: New test case.
--- /dev/null
+# SHcompact testsuite.
+
+if [istarget sh64-*-*] {
+ # load support procs (none yet)
+ # load_lib cgen.exp
+
+ # all machines
+ set all_machs "sh5"
+
+ # The .cgs suffix is for "cgen .s".
+ foreach src [lsort [glob -nocomplain $srcdir/$subdir/compact/*.cgs]] {
+ # If we're only testing specific files and this isn't one of them,
+ # skip it.
+ if ![runtest_file_p $runtests $src] {
+ continue
+ }
+ run_sim_test $src $all_machs
+ }
+}
--- /dev/null
+2002-01-09 Ben Elliston <bje@redhat.com>
+
+ * macl.cgs: For good measure, clear the S bit at startup.
+
+2001-01-11 Ben Elliston <bje@redhat.com>
+
+ * fmov.cgs (f13b): Compare R0 with R1, not R2, when testing that
+ the source register was correctly post-incremented.
+
+2000-12-01 Ben Elliston <bje@redhat.com>
+
+ * *.cgs (ld): Link tests with -m shelf32.
+
+2000-11-24 Ben Elliston <bje@redhat.com>
+
+ * fmov.cgs: New test case.
+ * ftrv.cgs: Populate the matrix with meaningful values.
+
+2000-11-22 Ben Elliston <bje@redhat.com>
+
+ * *.cgs (as): Assemble tests with -isa=shcompact.
+
+2000-11-16 Ben Elliston <bje@redhat.com>
+
+ * *.cgs: New test cases.
+
--- /dev/null
+# sh testcase for add $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+init:
+ # Initialise some registers with values which help us to verify
+ # that the correct source registers are used by the ADD instruction.
+ mov #0, r0
+ mov #1, r1
+ mov #2, r2
+ mov #3, r3
+ mov #5, r5
+ mov #15, r15
+
+add:
+ # 0 + 0 = 0.
+ add r0, r0
+ assert r0, #0
+
+ # 0 + 1 = 1.
+ add r0, r1
+ assert r1, #1
+
+ # 1 + 2 = 3.
+ add r1, r2
+ assert r2, #3
+
+ # 3 + 5 = 8.
+ add r3, r5
+ assert r5, #8
+
+ # 8 + 8 = 16.
+ add r5, r5
+ assert r5, #16
+
+ # 15 + 1 = 16.
+ add r15, r1
+ assert r1, #16
+
+neg:
+ mov #1, r0
+ neg r0, r0
+ mov #2, r1
+ add r0, r1
+ assert r1, #1
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for addc $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ # Initialise some registers with values which help us to verify
+ # that the correct source registers are used by the ADDC instruction.
+
+ .macro init
+ mov #0, r0
+ mov #1, r1
+ mov #2, r2
+ mov #3, r3
+ mov #5, r5
+ mov #15, r15
+ .endm
+
+ start
+
+ init
+add:
+ clrt
+ addc r0, r0
+ assert r0, #0
+ clrt
+ addc r0, r1
+ assert r1, #1
+ clrt
+ addc r1, r2
+ assert r2, #3
+ clrt
+ addc r3, r5
+ assert r5, #8
+ clrt
+ addc r5, r5
+ assert r5, #16
+ clrt
+ addc r15, r1
+ assert r1, #16
+
+ init
+addt:
+ sett
+ addc r0, r0
+ assert r0, #1
+ sett
+ addc r0, r1
+ assert r1, #3
+ sett
+ addc r1, r2
+ assert r2, #6
+ sett
+ addc r3, r5
+ assert r5, #9
+ sett
+ addc r5, r5
+ assert r5, #19
+ sett
+ addc r15, r1
+ assert r1, #19
+
+ bra next
+ nop
+
+wrong:
+ fail
+
+next:
+ init
+large:
+ clrt
+ mov #1, r0
+ neg r0, r0
+ mov #2, r1
+ addc r0, r1
+ assert r1, #1
+
+ init
+larget:
+ sett
+ mov #1, r0
+ neg r0, r0
+ mov #2, r1
+ addc r0, r1
+ assert r1, #2
+
+okay:
+ pass
--- /dev/null
+# sh testcase for add #$imm8, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+init:
+ # Initialise some registers with values which help us to verify
+ # that the correct source registers are used by the ADD instruction.
+ mov #0, r0
+ mov #1, r1
+ mov #2, r2
+ mov #3, r3
+ mov #5, r5
+ mov #15, r15
+
+addi:
+ # 0 + 0 = 0.
+ add #0, r0
+ assert r0, #0
+
+ # 0 + 1 = 1.
+ add #0, r1
+ assert r1, #1
+
+ # 2 + 2 = 4.
+ add #2, r2
+ assert r2, #4
+
+ # 120 + 5 = 125.
+ add #120, r5
+ assert r5, #125
+
+large:
+ mov #1, r0
+ neg r0, r0
+ add #2, r0
+ assert r0, #1
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for addv $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+zero:
+ mov #0, r0
+ mov #0, r1
+ addv r0, r1
+ # Assert !T and #0.
+ bt wrong
+ assert r1, #0
+
+one:
+ mov #0, r0
+ mov #1, r1
+ addv r0, r1
+ # Assert !T and #1.
+ bt wrong
+ assert r1, #1
+
+large:
+ # Produce MAXINT in R0.
+ mov #0, r0
+ not r0, r0
+ shlr r0
+
+ # Put #3 into R1.
+ mov #3, r1
+
+ # Add them and overflow.
+ addv r0, r1
+
+ # Assert T and overflowed value.
+ bf wrong
+ mov #1, r7
+ rotr r7
+ add #2, r7
+ cmp/eq r1, r7
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for and $rm64, $rn64 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global and
+and:
+ mov #1, r1
+ mov #7, r2
+ rotr r2
+ rotr r2
+ and r1, r2
+
+ # R1 & R2 = 1.
+ assert r2, #1
+
+another:
+ mov #192, r1
+ mov #0, r2
+ and r1, r2
+
+ # R1 & R2 = 0.
+ assert r2, #0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for and.b #$imm8, @(r0, gbr) -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global orb
+init:
+ # Init GBR and R0.
+ mov #30, r0
+ ldc r0, gbr
+ mov #40, r0
+
+orb:
+ and.b #255, @(r0, gbr)
+ and.b #170, @(r0, gbr)
+ and.b #255, @(r0, gbr)
+ and.b #0, @(r0, gbr)
+
+okay:
+ pass
--- /dev/null
+# sh testcase for and #$imm8, r0 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global andi
+andi:
+ mov #0, r0
+ or #255, r0
+ and #0, r0
+ assert r0, #0
+
+large:
+ mov #0, r0
+ or #255, r0
+ shll8 r0
+ or #255, r0
+ shll8 r0
+ or #255, r0
+ shll8 r0
+ or #255, r0
+
+mask:
+ and #255, r0
+ mov r0, r1
+ mov #0, r0
+ or #255, r0
+ cmp/eq r0, r1
+ bf wrong
+
+mask0:
+ and #0, r0
+ assert r0, #0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for bf $disp8 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global taken
+taken:
+ clrt
+ bf ntaken
+ fail
+ .global ntaken
+ntaken:
+ sett
+ bf bad
+ pass
+bad:
+ fail
+ fail
+ fail
+ fail
--- /dev/null
+# sh testcase for bf/s $disp8 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global taken
+taken:
+ clrt
+ bf/s ntaken
+slot1:
+ nop
+ fail
+ .global ntaken
+ntaken:
+ sett
+ bf/s bad
+slot2:
+ nop
+ pass
+bad:
+ fail
+ fail
+ fail
+ fail
--- /dev/null
+# sh testcase for bra $disp12 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global bra
+bra:
+ bra okay
+slot:
+ nop
+bad:
+ fail
+ fail
+ fail
+ .global okay
+okay:
+ pass
+ fail
+
--- /dev/null
+# sh testcase for braf $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global braf
+braf:
+ mov #4, r0
+ braf r0
+slot:
+ nop
+bad:
+ fail
+ fail
+okay:
+ pass
+alsobad:
+ fail
+ fail
+ fail
--- /dev/null
+# sh testcase for brk -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ .global brk
+brk:
+ # If we hit the breakpoint, the sim will stop.
+ pass
+
+ # FIXME: breakpoint instruction.
+ # The SH4 assembler doesn't know about "brk".
+ .word 0x003b
+bad:
+ fail
--- /dev/null
+# sh testcase for bsr $disp12 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global bsr
+bsr:
+ bsr okay
+slot:
+ nop
+bad:
+ fail
+ fail
+okay:
+ pass
+alsobad:
+ fail
--- /dev/null
+# sh testcase for bsrf $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+bsrf:
+ mov #4, r0
+ bsrf r0
+slot:
+ nop
+bad:
+ fail
+ fail
+okay:
+ pass
+alsobad:
+ fail
+ fail
--- /dev/null
+# sh testcase for bt $disp8
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global taken
+taken:
+ sett
+ bt ntaken
+ fail
+ .global ntaken
+ntaken:
+ clrt
+ bt bad
+ pass
+bad:
+ fail
+ fail
+ fail
+ fail
--- /dev/null
+# sh testcase for bt/s $disp8 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global taken
+taken:
+ sett
+ bt/s ntaken
+slot1:
+ nop
+ fail
+ .global ntaken
+ntaken:
+ clrt
+ bt/s bad
+slot2:
+ nop
+ pass
+bad:
+ fail
+ fail
+ fail
+ fail
--- /dev/null
+# sh testcase for clrmac -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global clrmac
+clrmac:
+ clrmac
+ pass
--- /dev/null
+# sh testcase for clrs -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global clrs
+clrs:
+ clrs
+ # Somehow ensure that S is set.
+ pass
--- /dev/null
+# sh testcase for clrt -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global clrt
+clrt:
+ clrt
+ bt wrong
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for cmp/eq $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+zeroes:
+ mov #0, r1
+ mov #0, r2
+ cmp/eq r1, r2
+ bf wrong
+
+zero1:
+ mov #0, r1
+ mov #1, r2
+ cmp/eq r1, r2
+ bt wrong
+
+zero2:
+ mov #0, r2
+ mov #1, r1
+ cmp/eq r2, r1
+ bt wrong
+
+equal:
+ mov #192, r1
+ mov #192, r2
+ cmp/eq r1, r2
+ bf wrong
+
+noteq:
+ mov #192, r1
+ mov #193, r2
+ cmp/eq r1, r2
+ bt wrong
+
+large:
+ mov #1, r1
+ rotr r1
+ mov #1, r2
+ rotr r2
+ cmp/eq r1, r2
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for cmp/eq #$imm8, r0 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+zeroes:
+ mov #0, r0
+ cmp/eq #0, r0
+ bf wrong
+
+zero1:
+ mov #0, r0
+ cmp/eq #1, r0
+ bt wrong
+
+zero2:
+ mov #1, r0
+ cmp/eq #0, r0
+ bt wrong
+
+equal:
+ mov #192, r0
+ cmp/eq #192, r0
+ bf wrong
+
+sign:
+ mov #255, r0
+ cmp/eq #255, r0
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for cmp/ge $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+zero:
+ mov #0, r0
+ mov #0, r1
+ cmp/ge r0, r1
+ bf wrong
+
+onezero:
+ mov #1, r0
+ mov #0, r1
+ cmp/ge r0, r1
+ bt wrong
+
+zeroone:
+ mov #0, r0
+ mov #1, r1
+ cmp/ge r0, r1
+ bf wrong
+
+equal:
+ mov #192, r0
+ mov #192, r1
+ cmp/ge r0, r1
+ bf wrong
+
+eqlarge:
+ mov #1, r0
+ rotr r0
+ add #85, r0
+ mov #1, r1
+ rotr r1
+ add #85, r1
+ cmp/ge r0, r1
+ bf wrong
+
+large2:
+ mov #1, r0
+ rotr r0
+ add #85, r0
+ mov #1, r1
+ rotr r1
+ add #84, r1
+ cmp/ge r0, r1
+ bt wrong
+
+large3:
+ mov #1, r0
+ rotr r0
+ add #84, r0
+ mov #1, r1
+ rotr r1
+ add #85, r1
+ cmp/ge r0, r1
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for cmp/gt $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+zero:
+ mov #0, r0
+ mov #0, r1
+ cmp/gt r0, r1
+ bt wrong
+
+onezero:
+ mov #1, r0
+ mov #0, r1
+ cmp/gt r0, r1
+ bt wrong
+
+zeroone:
+ mov #0, r0
+ mov #1, r1
+ cmp/gt r0, r1
+ bf wrong
+
+equal:
+ mov #192, r0
+ mov #192, r1
+ cmp/gt r0, r1
+ bt wrong
+
+eqlarge:
+ mov #1, r0
+ rotr r0
+ add #85, r0
+ mov #1, r1
+ rotr r1
+ add #85, r1
+ cmp/gt r0, r1
+ bt wrong
+
+large2:
+ mov #1, r0
+ rotr r0
+ add #85, r0
+ mov #1, r1
+ rotr r1
+ add #84, r1
+ cmp/gt r0, r1
+ bt wrong
+
+large3:
+ mov #1, r0
+ rotr r0
+ add #84, r0
+ mov #1, r1
+ rotr r1
+ add #85, r1
+ cmp/gt r0, r1
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for cmp/hi $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+zero:
+ mov #0, r0
+ mov #0, r0
+ cmp/hi r0, r1
+ bt wrong
+
+equal:
+ mov #1, r0
+ rotr r0
+ add #3, r0
+
+ mov #1, r1
+ rotr r1
+ add #3, r1
+
+ cmp/hi r0, r1
+ bt wrong
+
+gt:
+ mov #10, r0
+ mov #12, r1
+ cmp/hi r0, r1
+ bf wrong
+
+lt:
+ mov #12, r0
+ mov #10, r1
+ cmp/hi r0, r1
+ bt wrong
+
+gtneg:
+ mov #1, r0
+ rotr r0
+ add #1, r0
+
+ mov #1, r1
+ rotr r1
+ add #3, r1
+
+ cmp/hi r0, r1
+ bf wrong
+
+ltneg:
+ mov #1, r0
+ rotr r0
+ add #3, r0
+
+ mov #1, r1
+ rotr r1
+ add #1, r1
+
+ cmp/hi r0, r1
+ bt wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for cmp/hs $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+zero:
+ mov #0, r0
+ mov #0, r0
+ cmp/hs r0, r1
+
+equal:
+ mov #1, r0
+ rotr r0
+ add #3, r0
+
+ mov #1, r1
+ rotr r1
+ add #3, r1
+
+ cmp/hs r0, r1
+
+gt:
+ mov #10, r0
+ mov #12, r1
+ cmp/hs r0, r1
+
+lt:
+ mov #12, r0
+ mov #10, r1
+ cmp/hs r0, r1
+
+gtneg:
+ mov #1, r0
+ rotr r0
+ add #1, r0
+
+ mov #1, r1
+ rotr r1
+ add #3, r1
+
+ cmp/hs r0, r1
+
+ltneg:
+ mov #1, r0
+ rotr r0
+ add #3, r0
+
+ mov #1, r1
+ rotr r1
+ add #1, r1
+
+ cmp/hs r0, r1
+
+okay:
+ pass
--- /dev/null
+# sh testcase for cmp/pl $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+zero:
+ mov #0, r0
+ cmp/pl r0
+ bt wrong
+
+plus:
+ mov #10, r0
+ cmp/pl r0
+ bf wrong
+
+minus:
+ mov #10, r0
+ neg r0, r0
+ cmp/pl r0
+ bt wrong
+
+large:
+ mov #10, r0
+ shll8 r0
+ add #123, r0
+ cmp/pl r0
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for cmp/pz $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+zero:
+ mov #0, r0
+ cmp/pz r0
+ bf wrong
+
+plus:
+ mov #10, r0
+ cmp/pz r0
+ bf wrong
+
+minus:
+ mov #10, r0
+ neg r0, r0
+ cmp/pz r0
+ bt wrong
+
+large:
+ mov #10, r0
+ shll8 r0
+ add #123, r0
+ cmp/pz r0
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for cmp/str $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+.macro rot8
+ rotr r0
+ rotr r0
+ rotr r0
+ rotr r0
+ rotr r0
+ rotr r0
+ rotr r0
+ rotr r0
+.endm
+
+ start
+
+# Use multiple "wrong" labels because this program is quite long. It's
+# likely that some instructions will be too far away from the branch
+# target to use PC-relative branches.
+
+match0:
+ # No bytes matching.
+ mov #1, r0
+ neg r0, r0
+ xor #170, r0
+ rot8
+ xor #170, r0
+ rot8
+ xor #170, r0
+ rot8
+ xor #170, r0
+ rot8
+ mov r0, r1
+ mov #1, r0
+ neg r0, r0
+ xor #85, r0
+ rot8
+ xor #85, r0
+ rot8
+ xor #85, r0
+ rot8
+ xor #85, r0
+ rot8
+ cmp/str r0, r1
+ bt wrong0
+
+ bra match1
+ nop
+wrong0:
+ fail
+
+match1:
+ # One byte matching.
+ mov #1, r0
+ neg r0, r0
+ xor #170, r0
+ rot8
+ xor #170, r0
+ rot8
+ xor #170, r0
+ rot8
+ mov r0, r1
+ mov #1, r0
+ neg r0, r0
+ xor #85, r0
+ rot8
+ xor #85, r0
+ rot8
+ xor #85, r0
+ rot8
+ cmp/str r0, r1
+ bf wrong1
+
+ bra match2
+ nop
+wrong1:
+ fail
+
+match2:
+ # Two bytes matching.
+ mov #1, r0
+ neg r0, r0
+ xor #170, r0
+ rot8
+ xor #170, r0
+ rot8
+ mov r0, r1
+ mov #1, r0
+ neg r0, r0
+ xor #85, r0
+ rot8
+ xor #85, r0
+ rot8
+ cmp/str r0, r1
+ bf wrong2
+
+ bra match3
+ nop
+wrong2:
+ fail
+
+byte0:
+match3:
+ # One byte matching.
+ # This is also the test for byte 0.
+ mov #85, r0
+ mov #85, r1
+ cmp/str r0, r1
+ bf wrong3
+
+byte1:
+ # Match in byte position 1.
+ mov #85, r0
+ shll8 r0
+ mov #85, r1
+ shll8 r1
+ cmp/str r0, r1
+ bf wrong3
+
+byte2:
+ # Match in byte position 2.
+ mov #85, r0
+ shll16 r0
+ mov #85, r1
+ shll16 r1
+ cmp/str r0, r1
+ bf wrong3
+
+byte3:
+ # Match in byte position 3.
+ mov #85, r0
+ shll16 r0
+ shll8 r0
+ mov #85, r1
+ shll16 r1
+ shll8 r1
+ cmp/str r0, r1
+ bf wrong3
+
+okay:
+ pass
+wrong3:
+ fail
+
--- /dev/null
+# sh testcase for div0s $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+init:
+ mov #0, r0
+ mov #3, r1
+ mov #4, r2
+ neg r1, r3
+ neg r2, r4
+
+perm1:
+ div0s r0, r0
+ bt wrong
+ div0s r0, r1
+ bt wrong
+ div0s r1, r0
+ bt wrong
+
+perm2:
+ div0s r0, r4
+ bf wrong
+ div0s r4, r0
+ bf wrong
+
+perm3:
+ div0s r1, r2
+ bt wrong
+ div0s r2, r1
+ bt wrong
+
+perm4:
+ div0s r3, r4
+ bt wrong
+ div0s r4, r3
+ bt wrong
+
+perm5:
+ div0s r1, r1
+ bt wrong
+ div0s r3, r3
+ bt wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for div0u -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global div0u
+div0u:
+ div0u
+ # Can't easily test Q and M (other than visually inspecting
+ # the simulator's trace output).
+ bt wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for div1 $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #10, r0
+ mov #2, r1
+ div0s r0,r1
+
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+ div1 r0, r1
+
+ pass
--- /dev/null
+# sh testcase for dmuls.l $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ mov #0, r0
+ mov #0, r1
+ dmuls.l r0, r1
+ # check result
+ sts mach, r3
+ sts macl, r4
+ assert r3, #0
+ assert r4, #0
+
+test2:
+ mov #0, r0
+ mov #5, r1
+ dmuls.l r0, r1
+ # check result
+ sts mach, r3
+ sts macl, r4
+ assert r3, #0
+ assert r4, #0
+
+test3:
+ mov #5, r0
+ mov #0, r1
+ dmuls.l r0, r1
+ # check result
+ sts mach, r3
+ sts macl, r4
+ assert r3, #0
+ assert r4, #0
+
+test4:
+ mov #1, r0
+ mov #5, r1
+ dmuls.l r0, r1
+ # check result
+ sts mach, r3
+ sts macl, r4
+ assert r3, #0
+ assert r4, #5
+
+test5:
+ mov #5, r0
+ mov #1, r1
+ dmuls.l r0, r1
+ # check result
+ sts mach, r3
+ sts macl, r4
+ assert r3, #0
+ assert r4, #5
+
+ bra test6
+ nop
+
+wrong:
+ fail
+
+test6:
+ mov #2, r0
+ mov #2, r1
+ dmuls.l r0, r1
+ # check result
+ sts mach, r3
+ sts macl, r4
+ assert r3, #0
+ assert r4, #4
+
+test7:
+ mov #1, r0
+ neg r0, r0
+ mov #2, r1
+ dmuls.l r0, r1
+ # check result
+ sts mach, r3
+ sts macl, r4
+
+ mov #0, r8
+ not r8, r9
+ not r8, r10
+ shll r10
+ cmp/eq r3, r9
+ bf wrong
+ cmp/eq r4, r10
+ bf wrong
+
+test8:
+ mov #1, r0
+ neg r0, r0
+ mov #1, r1
+ neg r1, r1
+ dmuls.l r0, r1
+ # check result
+ sts mach, r3
+ sts macl, r4
+ assert r3, #0
+ assert r4, #1
+
+test9:
+ mov #1, r0
+ neg r0, r0
+ shlr r0
+ mov #1, r1
+ neg r1, r1
+ shlr r1
+ dmuls.l r0, r1
+
+okay:
+ pass
--- /dev/null
+# sh testcase for dmulu.l $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ mov #0, r0
+ mov #0, r1
+ dmulu.l r0, r1
+
+ mov #0, r0
+ mov #5, r1
+ dmulu.l r0, r1
+
+ mov #5, r0
+ mov #0, r1
+ dmulu.l r0, r1
+
+ mov #1, r0
+ mov #5, r1
+ dmulu.l r0, r1
+
+ mov #5, r0
+ mov #1, r1
+ dmulu.l r0, r1
+
+ mov #2, r0
+ mov #2, r1
+ dmulu.l r0, r1
+
+ mov #1, r0
+ neg r0, r0
+ mov #2, r1
+ dmulu.l r0, r1
+
+ mov #1, r0
+ neg r0, r0
+ mov #1, r1
+ neg r1, r1
+ dmulu.l r0, r1
+
+ mov #1, r0
+ neg r0, r0
+ shlr r0
+ mov #1, r1
+ neg r1, r1
+ shlr r1
+ dmulu.l r0, r1
+
+ pass
--- /dev/null
+# sh testcase for dt $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global dt
+dt:
+ mov #3, r0
+ dt r0
+ bt wrong
+ assert r0, #2
+
+ mov #1, r0
+ dt r0
+ bf wrong
+ assert r0, #0
+
+ mov #0, r0
+ dt r0
+ bt wrong
+ mov #0, r7
+ not r7, r7
+ cmp/eq r7, r0
+ bf wrong
+
+ mov #1, r0
+ neg r0, r0
+ dt r0
+ mov #1, r7
+ not r7, r7
+ cmp/eq r7, r0
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for exts.b $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global extsb
+extsb:
+ mov #42, r1
+ exts.b r1, r2
+ assert r2, #42
+signed:
+ mov #0, r0
+ or #255, r0
+ exts.b r0, r1
+ mov #0, r7
+ not r7, r7
+ cmp/eq r1, r7
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for exts.w $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global extsw
+extsw:
+ mov #42, r1
+ exts.w r1, r2
+ assert r2, #42
+
+another:
+ mov #0, r0
+ or #255, r0
+ shll8 r0
+ exts.w r0, r1
+
+ mov #-1, r7
+ shll8 r7
+ cmp/eq r1, r7
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for extu.b $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global extub
+extub:
+ mov #42, r1
+ extu.b r1, r2
+ assert r2, #42
+
+another:
+ mov #0, r0
+ or #255, r0
+ extu.b r0, r1
+
+ mov #0, r0
+ or #255, r0
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for extu.w $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global extuw
+extuw:
+ mov #42, r1
+ extu.w r1, r2
+ assert r2, #42
+
+another:
+ mov #0, r0
+ or #255, r0
+ shll8 r0
+ extu.w r0, r1
+ mov #0, r0
+ or #255, r0
+ shll8 r0
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fabs -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ _clrpr
+ # fabs(0.0) = 0.0.
+ fldi0 fr0
+ fabs fr0
+ fldi0 fr1
+ fcmp/eq fr0, fr1
+ bf wrong
+
+ # fabs(1.0) = 1.0.
+ fldi1 fr0
+ fabs fr0
+ fldi1 fr1
+ fcmp/eq fr0, fr1
+ bf wrong
+
+ # fabs(-1.0) = 1.0.
+ fldi1 fr0
+ fneg fr0
+ fabs fr0
+ fldi1 fr1
+ fcmp/eq fr0, fr1
+ bf wrong
+
+ bra double
+ nop
+
+wrong:
+ fail
+
+double:
+ # double precision tests.
+ # fabs(0.0) = 0.0.
+ fldi0 fr0
+ _s2d fr0, dr0
+ _setpr
+ fabs dr0
+ _clrpr
+ # check.
+ fldi0 fr2
+ _s2d fr2, dr2
+ _setpr
+ fcmp/eq dr0, dr2
+ bf wrong
+ _clrpr
+
+one:
+ # fabs(1.0) = 1.0.
+ fldi1 fr0
+ _s2d fr0, dr0
+ _setpr
+ fabs dr0
+ _clrpr
+ # check.
+ fldi1 fr2
+ _s2d fr2, dr2
+ _setpr
+ fcmp/eq dr0, dr2
+ bf wrong2
+ _clrpr
+
+minusone:
+ # fabs(-1.0) = 1.0.
+ fldi1 fr0
+ fneg fr0
+ _s2d fr0, dr0
+ _setpr
+ fabs dr0
+ _clrpr
+ # check.
+ fldi1 fr2
+ _s2d fr2, dr2
+ _setpr
+ fcmp/eq dr0, dr2
+ bf wrong2
+ _clrpr
+
+okay:
+ pass
+wrong2:
+ fail
--- /dev/null
+# sh testcase for fadd
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ _clrpr
+
+ fldi1 fr0
+ fldi1 fr1
+ fadd fr0, fr1
+
+ fldi0 fr0
+ fldi1 fr1
+ fadd fr0, fr1
+
+ fldi1 fr0
+ fldi0 fr1
+ fadd fr0, fr1
+
+ _setpr
+double:
+ fldi1 fr0
+ fldi1 fr1
+ _s2d fr0, dr4
+ _s2d fr1, dr6
+ fadd dr4, dr6
+
+ pass
--- /dev/null
+# sh testcase for fcmpeq -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ # 1.0 == 1.0.
+ fldi1 fr0
+ fldi1 fr1
+ fcmp/eq fr0, fr1
+ bf wrong
+
+ # 0.0 != 1.0.
+ fldi0 fr0
+ fldi1 fr1
+ fcmp/eq fr0, fr1
+ bt wrong
+
+ # 1.0 != 0.0.
+ fldi1 fr0
+ fldi0 fr1
+ fcmp/eq fr0, fr1
+ bt wrong
+
+ # 2.0 != 1.0
+ fldi1 fr0
+ fadd fr0, fr0
+ fldi1 fr1
+ fcmp/eq fr0, fr1
+ bt wrong
+
+ bra double
+ # delay slot
+ nop
+
+wrong:
+ fail
+
+double:
+ # 1.0 == 1.0
+ fldi1 fr0
+ fldi1 fr2
+ _s2d fr0, dr0
+ _s2d fr2, dr2
+ _setpr
+ fcmp/eq dr0, dr2
+ bf wrong
+ _clrpr
+
+ # 0.0 != 1.0
+ fldi0 fr0
+ fldi1 fr2
+ _s2d fr0, dr0
+ _s2d fr2, dr2
+ _setpr
+ fcmp/eq dr0, dr2
+ bt wrong
+ _clrpr
+
+ # 1.0 != 0.0
+ fldi1 fr0
+ fldi0 fr2
+ _s2d fr0, dr0
+ _s2d fr2, dr2
+ _setpr
+ fcmp/eq dr0, dr2
+ bt wrong2
+ _clrpr
+
+ # 2.0 != 1.0
+ fldi1 fr0
+ fadd fr0, fr0
+ fldi1 fr2
+ _s2d fr0, dr0
+ _s2d fr2, dr2
+ _setpr
+ fcmp/eq dr0, dr2
+ bt wrong2
+ _clrpr
+
+okay:
+ pass
+
+wrong2:
+ fail
--- /dev/null
+# sh testcase for fcmpgt -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ # 1.0 !> 1.0.
+ fldi1 fr0
+ fldi1 fr1
+ fcmp/gt fr0, fr1
+ bt wrong
+
+ # 0.0 !> 1.0.
+ fldi0 fr0
+ fldi1 fr1
+ fcmp/gt fr0, fr1
+ bf wrong
+
+ # 1.0 > 0.0.
+ fldi1 fr0
+ fldi0 fr1
+ fcmp/gt fr0, fr1
+ bt wrong
+
+ # 2.0 > 1.0
+ fldi1 fr0
+ fadd fr0, fr0
+ fldi1 fr1
+ fcmp/gt fr0, fr1
+ bt wrong
+
+ bra double
+ nop
+
+wrong:
+ fail
+
+double:
+ # double precision tests.
+ # 1.0 !> 1.0.
+ fldi1 fr0
+ fldi1 fr2
+ _s2d fr0, dr0
+ _s2d fr2, dr2
+ _setpr
+ fcmp/gt dr0, dr2
+ bt wrong2
+ _clrpr
+
+ # 0.0 !> 1.0.
+ fldi0 fr0
+ fldi1 fr2
+ _s2d fr0, dr0
+ _s2d fr2, dr2
+ _setpr
+ fcmp/gt dr0, dr2
+ bf wrong2
+ _clrpr
+
+ bra next
+ nop
+
+wrong2:
+ fail
+
+next:
+ # 1.0 > 0.0.
+ fldi1 fr0
+ fldi0 fr2
+ _s2d fr0, dr0
+ _s2d fr2, dr2
+ _setpr
+ fcmp/gt dr0, dr2
+ bt wrong2
+ _clrpr
+
+ # 2.0 > 1.0.
+ fldi1 fr0
+ fadd fr0, fr0
+ fldi1 fr2
+ _s2d fr0, dr0
+ _s2d fr2, dr2
+ _setpr
+ fcmp/gt dr0, dr2
+ bt wrong2
+ _clrpr
+
+okay:
+ pass
+
+wrong3:
+ fail
--- /dev/null
+# sh testcase for fcnvds -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ _setpr
+ fcnvds dr0, fpul
+ _clrpr
+okay:
+ pass
--- /dev/null
+# sh testcase for fcnvsd -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ fldi1 fr0
+ flds fr0, fpul
+ _setpr
+ fcnvsd fpul, dr2
+ _clrpr
+
+ # Convert back.
+ _setpr
+ fcnvds dr2, fpul
+ _clrpr
+ fsts fpul, fr1
+ fcmp/eq fr0, fr1
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fdiv -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ _clrpr
+
+ # 1.0 / 0.0 should be INF
+ # (and not crash the sim).
+ fldi0 fr0
+ fldi1 fr1
+ fdiv fr0, fr1
+
+ # 0.0 / 1.0 == 0.0.
+ fldi0 fr0
+ fldi1 fr1
+ fdiv fr1, fr0
+ fldi0 fr2
+ fcmp/eq fr0, fr2
+ bf wrong
+
+ # 2.0 / 1.0 == 2.0.
+ fldi1 fr1
+ fldi1 fr2
+ fadd fr2, fr2
+ fdiv fr1, fr2
+ # Load 2.0 into fr3.
+ fldi1 fr3
+ fadd fr3, fr3
+ fcmp/eq fr2, fr3
+ bf wrong
+
+ # (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
+ fldi1 fr1
+ fldi1 fr2
+ fadd fr2, fr2
+ fdiv fr2, fr1
+ # fr1 should contain 0.5.
+ fadd fr1, fr1
+ # Load 1.0 into fr3.
+ fldi1 fr3
+ # Compare fr1 with fr3.
+ fcmp/eq fr1, fr3
+ bf wrong
+
+ bra double
+ nop
+
+wrong:
+ fail
+
+double:
+ # double test
+ # (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
+ fldi1 fr1
+ _s2d fr1, dr6
+ fldi1 fr2
+ fadd fr2, fr2
+ _s2d fr2, dr8
+ _setpr
+ fdiv dr8, dr6
+ # dr0 should contain 0.5.
+ # double it, expect 1.0.
+ fadd dr6, dr6
+ _clrpr
+foo:
+ # Load 1.0 into dr4.
+ fldi1 fr1
+ _s2d fr1, dr10
+ # Compare dr0 with dr10.
+ _setpr
+ fcmp/eq dr6, dr10
+ bf wrong2
+ _clrpr
+
+okay:
+ pass
+
+wrong2:
+ fail
--- /dev/null
+# sh testcase for fipr $fvm, $fvn
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+initv1:
+ fldi1 fr0
+ # Load 2 into fr2.
+ fldi1 fr1
+ fadd fr1, fr1
+ # Load 4 into fr2.
+ fldi1 fr2
+ fadd fr2, fr2
+ fadd fr2, fr2
+ fldi0 fr3
+
+initv2:
+ fldi1 fr8
+ fldi0 fr9
+ fldi1 fr10
+ fldi0 fr11
+
+ fipr fv0, fv8
+
+ # Result will be in fr11.
+ fldi1 fr0
+ fldi1 fr1
+ # Two.
+ fadd fr1, fr0
+ # Four.
+ fadd fr0, fr0
+ # Five.
+ fadd fr1, fr0
+ fcmp/eq fr0, fr11
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fldi0 $frn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ fldi0 fr0
+ fldi0 fr2
+ fldi0 fr4
+ fldi0 fr6
+ fldi0 fr8
+ fldi0 fr10
+ fldi0 fr12
+ fldi0 fr14
+ pass
--- /dev/null
+# sh testcase for fldi1 $frn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ fldi1 fr1
+ fldi1 fr3
+ fldi1 fr5
+ fldi1 fr7
+ fldi1 fr9
+ fldi1 fr11
+ fldi1 fr13
+ fldi1 fr15
+ pass
--- /dev/null
+# sh testcase for flds -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ fldi0 fr0
+ flds fr0, fpul
+ fsts fpul, fr1
+ fcmp/eq fr0, fr1
+ bf wrong
+
+ fldi1 fr0
+ flds fr0, fpul
+ fsts fpul, fr1
+ fcmp/eq fr0, fr1
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for float -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+pos:
+ mov #3, r0
+ lds r0, fpul
+ float fpul, fr7
+
+ # Check the result.
+ fldi1 fr0
+ fldi1 fr1
+ fadd fr0, fr1
+ fadd fr0, fr1
+ fcmp/eq fr1, fr7
+ bf wrong
+
+neg:
+ mov #3, r0
+ neg r0, r0
+ lds r0, fpul
+ float fpul, fr7
+
+ # Check the result.
+ fldi1 fr0
+ fldi1 fr1
+ fadd fr0, fr1
+ fadd fr0, fr1
+ fneg fr1
+ fcmp/eq fr1, fr7
+ bf wrong
+
+ bra double
+ nop
+
+wrong:
+ fail
+
+double:
+ mov #3, r0
+ lds r0, fpul
+ _setpr
+ float fpul, dr8
+ _clrpr
+ # check the result.
+ fldi1 fr0
+ fldi1 fr1
+ fadd fr0, fr1
+ fadd fr0, fr1
+ _s2d fr1, dr2
+ fcmp/eq dr2, dr8
+ bf wrong
+
+dneg:
+ mov #3, r0
+ neg r0, r0
+ lds r0, fpul
+ _setpr
+ float fpul, dr8
+ _clrpr
+ # check the result.
+ fldi1 fr0
+ fldi1 fr1
+ fadd fr0, fr1
+ fadd fr0, fr1
+ fneg fr1
+ _s2d fr1, dr2
+ fcmp/eq dr2, dr8
+ bf wrong
+
+okay:
+ pass
+
+wrong2:
+ fail
--- /dev/null
+# sh testcase for fmac -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ # 0.0 * x + y = y.
+
+ fldi0 fr0
+ fldi1 fr1
+ fldi1 fr2
+ fmac fr0, fr1, fr2
+ # check result.
+ fldi1 fr0
+ fcmp/eq fr0, fr2
+ bf wrong
+
+ # x * y + 0.0 = x * y.
+
+ fldi1 fr0
+ fldi1 fr1
+ fldi0 fr2
+ # double it.
+ fadd fr1, fr2
+ fmac fr0, fr1, fr2
+ # check result.
+ fldi1 fr0
+ fadd fr0, fr0
+ fcmp/eq fr0, fr2
+ bf wrong
+
+ # x * 0.0 + y = y.
+
+ fldi1 fr0
+ fldi0 fr1
+ fldi1 fr2
+ fadd fr2, fr2
+ fmac fr0, fr1, fr2
+ # check result.
+ fldi1 fr0
+ # double fr0.
+ fadd fr0, fr0
+ fcmp/eq fr0, fr2
+ bf wrong
+
+ # x * 0.0 + 0.0 = 0.0
+
+ fldi1 fr0
+ fadd fr0, fr0
+ fldi0 fr1
+ fldi0 fr2
+ fmac fr0, fr1, fr2
+ # check result.
+ fldi0 fr0
+ fcmp/eq fr0, fr2
+ bf wrong
+
+ # 0.0 * x + 0.0 = 0.0.
+
+ fldi0 fr0
+ fldi1 fr1
+ # double it.
+ fadd fr1, fr1
+ fldi0 fr2
+ fmac fr0, fr1, fr2
+ # check result.
+ fldi0 fr0
+ fcmp/eq fr0, fr2
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for all fmov instructions
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ .macro init
+ fldi0 fr0
+ fldi1 fr2
+ .endm
+
+ # Set the SZ (SiZe) bit in the fpscr.
+ .macro _setsz
+ sts fpscr, r7
+ mov #16, r8
+ shll16 r8
+ or r8, r7
+ lds r7, fpscr
+ .endm
+
+ # Clear the SZ bit.
+ .macro _clrsz
+ sts fpscr, r7
+ mov #16, r8
+ shll16 r8
+ not r8, r8
+ and r8, r7
+ lds r7, fpscr
+ .endm
+ start
+
+fmov1: # Test fr -> fr.
+ init
+ _clrpr
+ _clrsz
+ fmov fr0, fr10
+ # Ensure fr0 and fr10 are now equal.
+ fcmp/eq fr0, fr10
+ bt fmov2
+ fail
+
+fmov2: # Test dr -> dr.
+ init
+ _setpr
+ _setsz
+ fmov dr0, dr2
+ # Ensure dr0 and dr2 are now equal.
+ fcmp/eq dr0, dr2
+ bt fmov3
+ fail
+
+fmov3: # Test dr -> xd and xd -> dr.
+ init
+ _setsz
+ fmov dr0, xd0
+ # Ensure dr0 and xd0 are now equal.
+ fmov xd0, dr2
+ fcmp/eq dr0, dr2
+ bt fmov4
+ fail
+
+fmov4: # Test xd -> xd.
+ init
+ _setsz
+ _setpr
+ fmov dr0, xd0
+ fmov xd0, xd2
+ fmov xd2, dr2
+ # Ensure dr0 and dr2 are now equal.
+ fcmp/eq dr0, dr2
+ bt fmov5
+ fail
+
+fmov5: # Test fr -> @rn and @rn -> fr.
+ init
+ _clrsz
+ _clrpr
+ mov #40, r0
+ shll8 r0
+ fmov fr0, @r0
+ fmov @r0, fr1
+ fcmp/eq fr0, fr1
+ bt fmov6
+ fail
+
+fmov6: # Test dr -> @rn and @rn -> dr.
+ init
+ _setsz
+ _setpr
+ mov #40, r0
+ shll8 r0
+ fmov dr0, @r0
+ fmov @r0, dr2
+ fcmp/eq dr0, dr2
+ bt fmov7
+ fail
+
+fmov7: # Test xd -> @rn and @rn -> xd.
+ init
+ _setsz
+ _setpr
+ mov #40, r0
+ shll8 r0
+ fmov dr0, xd0
+ fmov xd0, @r0
+ fmov @r0, xd2
+ fmov xd2, dr2
+ fcmp/eq dr0, dr2
+ bt fmov8
+ fail
+
+fmov8: # Test fr -> @-rn.
+ init
+ _clrsz
+ _clrpr
+ mov #40, r0
+ shll8 r0
+ # Preserve.
+ mov r0, r1
+ fmov fr0, @-r0
+ fmov @r0, fr2
+ fcmp/eq fr0, fr2
+ bt f8b
+ fail
+f8b: # check pre-dec.
+ add #4, r0
+ cmp/eq r0, r1
+ bt fmov9
+ fail
+
+fmov9: # Test dr -> @-rn.
+ init
+ _setsz
+ _setpr
+ mov #40, r0
+ shll8 r0
+ # Preserve r0.
+ mov r0, r1
+ fmov dr0, @-r0
+ fmov @r0, dr2
+ fcmp/eq dr0, dr2
+ bt f9b
+ fail
+f9b: # check pre-dec.
+ add #8, r0
+ cmp/eq r0, r1
+ bt fmov10
+ fail
+
+fmov10: # Test xd -> @-rn.
+ init
+ _setsz
+ _setpr
+ mov #40, r0
+ shll8 r0
+ # Preserve r0.
+ mov r0, r1
+ fmov dr0, xd0
+ fmov xd0, @-r0
+ fmov @r0, xd2
+ fmov xd2, dr2
+ fcmp/eq dr0, dr2
+ bt f10b
+ fail
+f10b: # check pre-dec.
+ add #8, r0
+ cmp/eq r0, r1
+ bt fmov11
+ fail
+
+fmov11: # Test @rn+ -> fr.
+ init
+ _clrsz
+ _clrpr
+ mov #40, r0
+ shll8 r0
+ # Preserve r0.
+ mov r0, r1
+ fmov fr0, @r0
+ fmov @r0+, fr2
+ fcmp/eq fr0, fr2
+ bt f11b
+ fail
+f11b: # check post-inc.
+ add #4, r1
+ cmp/eq r0, r1
+ bt fmov12
+ fail
+
+fmov12: # Test @rn+ -> dr.
+ init
+ _setsz
+ _setpr
+ mov #40, r0
+ shll8 r0
+ # preserve r0.
+ mov r0, r1
+ fmov dr0, @r0
+ fmov @r0+, dr2
+ fcmp/eq dr0, dr2
+ bt f12b
+ fail
+f12b: # check post-inc.
+ add #8, r1
+ cmp/eq r0, r1
+ bt fmov13
+ fail
+
+fmov13: # Test @rn -> xd.
+ init
+ _setsz
+ _setpr
+ mov #40, r0
+ shll8 r0
+ # Preserve r0.
+ mov r0, r1
+ fmov dr0, xd0
+ fmov xd0, @r0
+ fmov @r0+, xd2
+ fmov xd2, dr2
+ fcmp/eq dr0, dr2
+ bt f13b
+ fail
+f13b:
+ add #8, r1
+ cmp/eq r0, r1
+ bt fmov14
+ fail
+
+fmov14: # Test fr -> @(r0,rn), @(r0, rn) -> fr.
+ init
+ _clrsz
+ _clrpr
+ mov #40, r0
+ shll8 r0
+ mov #0, r1
+ fmov fr0, @(r0, r1)
+ fmov @(r0, r1), fr1
+ fcmp/eq fr0, fr1
+ bt fmov15
+ fail
+
+fmov15: # Test dr -> @(r0, rn), @(r0, rn) -> dr.
+ init
+ _setsz
+ _setpr
+ mov #40, r0
+ shll8 r0
+ mov #0, r1
+ fmov dr0, @(r0, r1)
+ fmov @(r0, r1), dr2
+ fcmp/eq dr0, dr2
+ bt fmov16
+ fail
+
+fmov16: # Test xd -> @(r0, rn), @(r0, rn) -> xd.
+ init
+ _setsz
+ _setpr
+ mov #40, r0
+ shll8 r0
+ mov #0, r1
+ fmov dr0, xd0
+ fmov xd0, @(r0, r1)
+ fmov @(r0, r1), xd2
+ fmov xd2, dr2
+ fcmp/eq dr0, dr2
+ bt okay
+ fail
+
+okay:
+ pass
--- /dev/null
+# sh testcase for fmul -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ .macro init
+ fldi0 fr0
+ fldi1 fr1
+ fldi1 fr2
+ fadd fr2, fr2
+ fldi0 fr7
+ fldi1 fr8
+ .endm
+
+ start
+
+ # 0.0 * 0.0 = 0.0.
+ init
+ fmul fr0, fr0
+ fcmp/eq fr7, fr0
+ bf wrong
+
+ # 0.0 * 1.0 = 0.0.
+ init
+ fmul fr1, fr0
+ fcmp/eq fr7, fr0
+ bf wrong
+
+ # 1.0 * 0.0 = 0.0.
+ init
+ fmul fr0, fr1
+ fcmp/eq fr7, fr1
+ bf wrong
+
+ # 1.0 * 1.0 = 1.0.
+ init
+ fmul fr1, fr1
+ fcmp/eq fr8, fr1
+ bf wrong
+
+ # 2.0 * 1.0 = 2.0.
+ init
+ fmul fr2, fr1
+ fcmp/eq fr2, fr1
+ bf wrong
+
+ bra double
+ nop
+
+wrong:
+ fail
+
+ .macro dinit
+ fldi0 fr0
+ fldi1 fr2
+ fldi1 fr4
+ fadd fr4, fr4
+ fldi0 fr8
+ fldi1 fr10
+ _s2d fr0, dr0
+ _s2d fr2, dr2
+ _s2d fr4, dr4
+ _s2d fr8, dr8
+ _s2d fr10, dr10
+ .endm
+
+double:
+ # 0.0 * 0.0 = 0.0.
+ dinit
+ _setpr
+ fmul dr0, dr0
+ fcmp/eq dr8, dr0
+ bf wrong
+ _clrpr
+
+ # 0.0 * 1.0 = 0.0.
+ dinit
+ _setpr
+ fmul dr2, dr0
+ fcmp/eq dr8, dr0
+ bf wrong2
+ _clrpr
+
+ # 1.0 * 0.0 = 0.0.
+ dinit
+ _setpr
+ fmul dr0, dr2
+ fcmp/eq dr8, dr2
+ bf wrong2
+ _clrpr
+
+ bra next
+ nop
+
+wrong2:
+ fail
+
+next:
+ # 1.0 * 1.0 = 1.0.
+ dinit
+ _setpr
+ fmul dr2, dr2
+ fcmp/eq dr10, dr2
+ bf wrong3
+ _clrpr
+
+ # 2.0 * 1.0 = 2.0.
+ dinit
+ _setpr
+ fmul dr4, dr2
+ fcmp/eq dr4, dr2
+ bf wrong3
+ _clrpr
+
+okay:
+ pass
+
+wrong3:
+ fail
--- /dev/null
+# sh testcase for fneg -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ # neg(0.0) = 0.0.
+ fldi0 fr0
+ fldi0 fr1
+ fneg fr0
+ fcmp/eq fr0, fr1
+ bf wrong
+
+ # neg(1.0) = fsub(0,1)
+ fldi1 fr0
+ fneg fr0
+ fldi0 fr1
+ fldi1 fr2
+ fsub fr2, fr1
+ fcmp/eq fr0, fr1
+ bf wrong
+
+ # neg(neg(1.0)) = 1.0.
+ fldi1 fr0
+ fldi1 fr1
+ fneg fr0
+ fneg fr0
+ fcmp/eq fr0, fr1
+ bf wrong
+
+ bra double
+ nop
+
+wrong:
+ fail
+
+double:
+ # neg(0.0) = 0.0.
+ fldi0 fr0
+ fldi0 fr2
+ _s2d fr0, dr0
+ _s2d fr2, dr2
+ _setpr
+ fneg dr0
+ fcmp/eq dr0, dr2
+ bf wrong2
+ _clrpr
+
+ # neg(1.0) = fsub(0,1)
+ fldi1 fr0
+ _s2d fr0, dr0
+ _setpr
+ fneg dr0
+ _clrpr
+ fldi0 fr2
+ fldi1 fr3
+ fsub fr3, fr2
+ _s2d fr2, dr2
+ _setpr
+ fcmp/eq fr0, fr2
+ bf wrong2
+ _clrpr
+
+ # neg(neg(1.0)) = 1.0.
+ fldi1 fr0
+ _s2d fr0, dr0
+ fldi1 fr2
+ _s2d fr2, dr2
+ _setpr
+ fneg dr0
+ fneg dr2
+ fcmp/eq dr0, dr2
+ bf wrong2
+ _clrpr
+
+okay:
+ pass
+
+wrong2:
+ fail
--- /dev/null
+# sh testcase for frchg
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ frchg
+ frchg
+ frchg
+ frchg
+ pass
--- /dev/null
+# sh testcase for fschg
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ fschg
+ fschg
+ fschg
+ fschg
+ pass
--- /dev/null
+# sh testcase for fsqrt -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ # sqrt(0.0) = 0.0.
+ fldi0 fr0
+ fsqrt fr0
+ fldi0 fr1
+ fcmp/eq fr0, fr1
+ bf wrong
+
+ # sqrt(1.0) = 1.0.
+ fldi1 fr0
+ fsqrt fr0
+ fldi1 fr1
+ fcmp/eq fr0, fr1
+ bf wrong
+
+ # sqrt(4.0) = 2.0
+ fldi1 fr0
+ # Double it.
+ fadd fr0, fr0
+ # Double it again.
+ fadd fr0, fr0
+ fsqrt fr0
+ fldi1 fr1
+ # Double it.
+ fadd fr1, fr1
+ fcmp/eq fr0, fr1
+ bf wrong
+
+ bra double
+ nop
+
+wrong:
+ fail
+
+double:
+ # sqrt(0.0) = 0.0.
+ fldi0 fr0
+ _s2d fr0, dr0
+ _setpr
+ fsqrt dr0
+ _clrpr
+ fldi0 fr2
+ _s2d fr2, dr2
+ _setpr
+ fcmp/eq dr0, dr2
+ bf wrong2
+ _clrpr
+
+ # sqrt(1.0) = 1.0.
+ fldi1 fr0
+ _s2d fr0, dr0
+ _setpr
+ fsqrt dr0
+ _clrpr
+ fldi1 fr2
+ _s2d fr2, dr2
+ _setpr
+ fcmp/eq fr0, fr2
+ bf wrong2
+ _clrpr
+
+ # sqrt(4.0) = 2.0.
+ fldi1 fr0
+ # Double it.
+ fadd fr0, fr0
+ # Double it again.
+ fadd fr0, fr0
+ _s2d fr0, dr0
+ _setpr
+ fsqrt dr0
+ _clrpr
+ fldi1 fr2
+ # Double it.
+ fadd fr2, fr2
+ _s2d fr2, dr2
+ _setpr
+ fcmp/eq fr0, fr2
+ bf wrong2
+ _clrpr
+
+okay:
+ pass
+
+wrong2:
+ fail
--- /dev/null
+# sh testcase for fsts fpul, $frn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ fsts fpul, fr0
+ fsts fpul, fr1
+ pass
--- /dev/null
+# sh testcase for fmul -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ # 0.0 - 0.0 = 0.0.
+ fldi0 fr0
+ fldi0 fr1
+ fsub fr0, fr1
+ fldi0 fr2
+ fcmp/eq fr1, fr2
+ bf wrong
+
+ # 1.0 - 0.0 = 1.0.
+ fldi0 fr0
+ fldi1 fr1
+ fsub fr0, fr1
+ fldi1 fr2
+ fcmp/eq fr1, fr2
+ bf wrong
+
+ # 1.0 - 1.0 = 0.0.
+ fldi1 fr0
+ fldi1 fr1
+ fsub fr0, fr1
+ fldi0 fr2
+ fcmp/eq fr1, fr2
+ bf wrong
+
+ # 0.0 - 1.0 = -1.0.
+ fldi1 fr0
+ fldi0 fr1
+ fsub fr0, fr1
+ fldi1 fr2
+ fneg fr2
+ fcmp/eq fr1, fr2
+ bf wrong
+
+ bra double
+ nop
+
+wrong:
+ fail
+
+double:
+ # 0.0 - 0.0 = 0.0.
+ fldi0 fr0
+ fldi0 fr2
+ _s2d fr0, dr0
+ _s2d fr2, dr2
+ _setpr
+ fsub dr0, dr2
+ _clrpr
+ fldi0 fr4
+ _s2d fr4, dr4
+ _setpr
+ fcmp/eq dr2, dr4
+ bf wrong
+ _clrpr
+
+onezero:
+ # 1.0 - 0.0 = 1.0.
+ fldi0 fr0
+ fldi1 fr2
+ _s2d fr0, dr0
+ _s2d fr2, dr2
+ _setpr
+ fsub dr0, dr2
+ _clrpr
+ fldi1 fr4
+ _s2d fr4, dr4
+ _setpr
+ fcmp/eq dr2, dr4
+ bf wrong2
+ _clrpr
+
+oneone:
+ # 1.0 - 1.0 = 0.0.
+ fldi1 fr0
+ fldi1 fr2
+ _s2d fr0, dr0
+ _s2d fr2, dr2
+ _setpr
+ fsub dr0, dr2
+ _clrpr
+ fldi0 fr4
+ _s2d fr4, dr4
+ _setpr
+ fcmp/eq dr2, dr4
+ bf wrong2
+ _clrpr
+
+ bra zeroone
+ nop
+
+wrong2:
+ fail
+
+zeroone:
+ # 0.0 - 1.0 = -1.0.
+ fldi1 fr0
+ fldi0 fr2
+ _s2d fr0, dr0
+ _s2d fr2, dr2
+ _setpr
+ fsub dr0, dr2
+ _clrpr
+ fldi1 fr4
+ fneg fr4
+ _s2d fr4, dr4
+ _setpr
+ fcmp/eq dr2, dr4
+ bf wrong2
+ _clrpr
+
+okay:
+ pass
--- /dev/null
+# sh testcase for ftrc -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ # ftrc(0.0) = 0.
+ fldi0 fr0
+ ftrc fr0, fpul
+ # check results.
+ mov #0, r0
+ sts fpul, r1
+ cmp/eq r0, r1
+ bf wrong
+
+ # ftrc(1.5) = 1.
+ fldi1 fr0
+ fldi1 fr1
+ fldi1 fr2
+ # double it.
+ fadd fr2, fr2
+ # form the fraction.
+ fdiv fr2, fr1
+ fadd fr1, fr0
+ # now we've got 1.5 in fr0.
+ ftrc fr0, fpul
+ # check results.
+ mov #1, r0
+ sts fpul, r1
+ cmp/eq r0, r1
+ bf wrong
+
+ # ftrc(-1.5) = -1.
+ fldi1 fr0
+ fneg fr0
+ fldi1 fr1
+ fldi1 fr2
+ # double it.
+ fadd fr2, fr2
+ # form the fraction.
+ fdiv fr2, fr1
+ fneg fr1
+ # -1 + -0.5 = -1.5.
+ fadd fr1, fr0
+ # now we've got 1.5 in fr0.
+ ftrc fr0, fpul
+ # check results.
+ mov #1, r0
+ neg r0, r0
+ sts fpul, r1
+ cmp/eq r0, r1
+ bf wrong
+
+ bra double
+ nop
+
+wrong:
+ fail
+
+double:
+ # ftrc(0.0) = 0.
+ fldi0 fr0
+ _s2d fr0, dr0
+ _setpr
+ ftrc dr0, fpul
+ _clrpr
+ # check results.
+ mov #0, r0
+ sts fpul, r1
+ cmp/eq r0, r1
+foo:
+ bf wrong2
+
+ # ftrc(1.5) = 1.
+ fldi1 fr0
+ fldi1 fr2
+ fldi1 fr4
+ # double it.
+ fadd fr4, fr4
+ # form 0.5.
+ fdiv fr4, fr2
+ fadd fr2, fr0
+ # now we've got 1.5 in fr0, so do some single->double
+ # conversions and perform the ftrc.
+ _s2d fr0, dr0
+ _s2d fr2, dr2
+ _s2d fr4, dr4
+ _setpr
+ ftrc dr0, fpul
+ _clrpr
+
+ # check results.
+ mov #1, r0
+ sts fpul, r1
+ cmp/eq r0, r1
+ bf wrong2
+
+ # ftrc(-1.5) = -1.
+ fldi1 fr0
+ fneg fr0
+ fldi1 fr2
+ fldi1 fr4
+ # double it.
+ fadd fr4, fr4
+ # form the fraction.
+ fdiv fr4, fr2
+ fneg fr2
+ # -1 + -0.5 = -1.5.
+ fadd fr2, fr0
+ # now we've got 1.5 in fr0, so do some single->double
+ # conversions and perform the ftrc.
+ _s2d fr0, dr0
+ _s2d fr2, dr2
+ _s2d fr4, dr4
+ _setpr
+ ftrc dr0, fpul
+ _clrpr
+
+ # check results.
+ mov #1, r0
+ neg r0, r0
+ sts fpul, r1
+ cmp/eq r0, r1
+ bf wrong2
+
+okay:
+ pass
+wrong2:
+ fail
--- /dev/null
+# sh testcase for ftrv xmtrx, $fvn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ # set the fr bit in the fpscr
+ .macro _setfr
+ sts fpscr, r7
+ mov #32, r8
+ shll16 r8
+ or r8, r7
+ lds r7, fpscr
+ .endm
+
+ # clear the fr bit
+ .macro _clrfr
+ sts fpscr, r7
+ mov #32, r8
+ shll16 r8
+ not r8, r8
+ and r8, r7
+ lds r7, fpscr
+ .endm
+
+ .macro incr old new
+ fldi1 \new
+ fadd \old, \new
+ .endm
+
+ start
+ _setfr
+popmtrx:
+ # 1.0.
+ fldi1 fr0
+ # 2.0.
+ fldi1 fr1
+ fadd fr1, fr1
+
+ incr fr1, fr2
+ incr fr2, fr3
+ incr fr3, fr4
+ incr fr4, fr5
+ incr fr5, fr6
+ incr fr6, fr7
+ incr fr7, fr8
+ incr fr8, fr9
+ incr fr9, fr10
+ incr fr10, fr11
+ incr fr11, fr12
+ incr fr12, fr13
+ incr fr13, fr14
+ incr fr14, fr15
+
+popvect:
+ # Swtich fp banks.
+ _clrfr
+ fldi1 fr4
+ fldi1 fr5
+ fadd fr5, fr5
+ fldi1 fr6
+ fadd fr5, fr6
+ fldi1 fr7
+ fadd fr6, fr7
+
+ftrv:
+ # fr[4,7] should contain the results:
+ # { 30, 70, 110, 150 }.
+ ftrv xmtrx, fv4
+
+okay:
+ pass
+
--- /dev/null
+# sh testcase for jmp @$rn
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global jmp
+jmp:
+ # Load 0x1010 into r0.
+ mov #1, r0
+ shll8 r0
+ shll2 r0
+ shll2 r0
+ add #16, r0
+ jmp @r0
+slot:
+ nop
+bad:
+ fail
+okay:
+ pass
+alsobad:
+ fail
+ fail
+ fail
+
--- /dev/null
+# sh testcase for jsr @$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global jsr
+jsr:
+ # Load 0x1010 into r0.
+ mov #1, r0
+ shll8 r0
+ shll2 r0
+ shll2 r0
+ add #16, r0
+ jsr @r0
+slot:
+ nop
+bad:
+ fail
+okay:
+ pass
+alsobad:
+ fail
+ fail
+ fail
+
--- /dev/null
+# sh testcase for ldc $rn, gbr -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global ldc
+ldc:
+ mov #40, r0
+ shll8 r0
+ ldc r0, gbr
+ stc gbr, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for ldc.l @${rn}+, gbr -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global ldcl
+ldcl:
+ mov #40, r0
+ shll8 r0
+ # Preserve address.
+ mov r0, r1
+ ldc.l @r0+, gbr
+
+ # Add 4 to saved address (r1).
+ # Then compare with r0.
+ add #4, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for lds $rn, fpscr -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global lds_fpscr
+lds_fpscr:
+ mov #0, r0
+ lds r0, fpscr
+readback:
+ sts fpscr, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for lds $rn, fpul -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global lds_fpul
+lds_fpul:
+ mov #63, r0
+ shll8 r0
+ add #128, r0
+ shll16 r0
+ lds r0, fpul
+ pass
--- /dev/null
+# sh testcase for lds $rn, mach
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global lds_mach
+lds_mach:
+ mov #41, r0
+ shll8 r0
+ lds r0, mach
+readback:
+ sts mach, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for lds $rn, macl
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global lds_macl
+lds_macl:
+ mov #42, r0
+ shll8 r0
+ lds r0, macl
+readback:
+ sts macl, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for lds $rn, pr
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global lds_pr
+lds_pr:
+ mov #40, r0
+ shll8 r0
+ lds r0, pr
+readback:
+ sts pr, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for lds.l @${rn}+, fpscr -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ mov #40, r0
+ shll8 r0
+ # save address for later examination.
+ mov r0, r1
+
+ # Build up a distinctive bit pattern.
+ mov #1, r2
+ shll8 r2
+ add #12, r2
+ shll8 r2
+ add #85, r2
+ shll8 r2
+ add #170, r2
+ # Store it in memory.
+ mov.l r2, @r0
+
+ lds.l @r0+, fpscr
+
+check:
+ # Read it back.
+ sts fpscr, r3
+ cmp/eq r2, r3
+ bf wrong
+
+inc:
+ # Test for proper post-increment.
+ add #4, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for lds.l @${rn}+, fpul -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global ldsl_fpul
+ldsl_fpul:
+ mov #40, r0
+ shll8 r0
+ # remember the address.
+ mov r0, r1
+ lds.l @r0+, fpul
+
+ # ensure post increment occurred.
+ add #4, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for lds.l @${rn}+, mach -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global ldsl_mach
+ldsl_mach:
+ mov #40, r0
+ shll8 r0
+ # save address for later examination.
+ mov r0, r1
+
+ lds.l @r0+, mach
+
+ add #4, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for lds.l @${rn}+, macl -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global ldsl_macl
+ldsl_macl:
+ mov #40, r0
+ shll8 r0
+ # save address for later examination.
+ mov r0, r1
+
+ lds.l @r0+, macl
+
+ add #4, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for lds.l @${rn}+, pr -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global ldsl_pr
+ldsl_pr:
+ mov #40, r0
+ shll8 r0
+ # Preserve address.
+ mov r0, r1
+ lds.l @r0+, pr
+
+ # Add 4 to saved address (r1).
+ # Then compare with r0.
+ add #4, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mac.l @${rm}+, @${rn}+
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ # force S-bit clear
+ clrs
+
+ # Store some magic numbers in memory.
+ mov #40, r1
+ shll8 r1
+ mov #85, r0
+ mov.l r0, @r1
+ # Keep for later.
+ mov r1, r10
+store2:
+ mov #40, r1
+ shll8 r1
+ add #12, r1
+ mov #17, r0
+ mov.l r0, @r1
+ # Keep for later.
+ mov r1, r11
+
+init:
+ # Set up addresses.
+ mov #40, r1
+ shll8 r1
+ mov #40, r2
+ shll8 r2
+ add #12, r2
+
+ # Prime {MACL, MACH} to #1.
+ mov #1, r3
+ dmulu.l r3, r3
+
+test:
+ mac.l @r1+, @r2+
+
+check:
+ # Check result.
+ sts mach, r5
+ assert r5, #0
+
+ mov #5, r0
+ shll8 r0
+ or #166, r0
+ sts macl, r6
+ cmp/eq r6, r0
+ bf wrong
+
+ # Ensure post-increment occurred.
+ add #4, r10
+ cmp/eq r10, r1
+ bf wrong
+
+ add #4, r11
+ cmp/eq r11, r2
+ bf wrong
+
+doubleinc:
+ mov #40, r0
+ shll8 r0
+ mov r0, r1
+ mac.l @r0+, @r0+
+ add #16, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mac.w @${rm}+, @${rn}+
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ # Store some magic numbers in memory.
+ mov #40, r1
+ shll8 r1
+ mov #85, r0
+ mov.l r0, @r1
+ # Keep for later.
+ mov r1, r10
+store2:
+ mov #40, r1
+ shll8 r1
+ add #12, r1
+ mov #17, r0
+ mov.l r0, @r1
+ # Keep for later.
+ mov r1, r11
+
+init:
+ # Set up addresses.
+ mov #40, r1
+ shll8 r1
+ mov #40, r2
+ shll8 r2
+ add #12, r2
+
+ # Prime {MACL, MACH} to #1.
+ mov #1, r3
+ dmulu.l r3, r3
+
+test:
+ mac.w @r1+, @r2+
+
+check:
+ # Check result.
+ sts mach, r5
+ assert r5, #0
+
+ sts macl, r6
+ assert r6, #1
+
+ # Ensure post-increment occurred.
+ add #2, r10
+ cmp/eq r10, r1
+ bf wrong
+
+ add #2, r11
+ cmp/eq r11, r2
+ bf wrong
+
+doubleinc:
+ mov #40, r0
+ shll8 r0
+ mov r0, r1
+ mac.w @r0+, @r0+
+ add #8, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov $rm64, $rn64
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global mov
+mov:
+ mov #1, r0
+ rotr r0
+ mov #0, r15
+ mov #10, r0
+
+ mov r0, r1
+ mov r1, r2
+ mov r2, r3
+ mov r3, r4
+ mov r4, r5
+ mov r5, r6
+ mov r6, r7
+ mov r7, r8
+ mov r8, r9
+ mov r9, r10
+ mov r10, r11
+ mov r11, r12
+ mov r12, r13
+ mov r13, r14
+ mov r14, r15
+
+ cmp/eq r0, r15
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mova @($imm8x4, pc), r0 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global mova
+mova:
+ mova @(40, pc), r0
+ mov #16, r1
+ shll8 r1
+ add #40, r1
+ cmp/eq r0, r1
+ bf wrong
+ mova @(12, pc), r0
+ mov #16, r1
+ shll8 r1
+ add #24, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.b $rm, @$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #55, r1
+ mov #40, r2
+ shll8 r2
+ mov.b r1, @r2
+
+ # Load it back into r3.
+ mov #40, r2
+ shll8 r2
+ mov.b @r2, r3
+
+ # Make sure r1 and r3 match.
+ cmp/eq r1, r3
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.b @($imm4, $rm), r0 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #30, r1
+ shll8 r1
+ # Store something there first.
+ mov #0, r0
+ or #170, r0
+ mov r0, r7
+ mov.b r0, @(3, r1)
+ # Load it back.
+ mov.b @(3, r1), r0
+ and #255, r0
+ cmp/eq r0, r7
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.b $rm, @-$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #40, r1
+ shll8 r1
+ mov #55, r2
+
+ # Save ADDR, DATA.
+ mov r1, r7
+ mov r2, r8
+
+ # Do the move.
+ mov.b r2, @-r1
+
+ # Load the value back into r3.
+ mov.b @r1, r3
+ cmp/eq r2, r3
+ bf wrong
+
+ # Ensure that r1 has been decremented.
+ mov #1, r0
+ sub r0, r7
+ cmp/eq r7, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.b $rm, @(r0,$rn) -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #40, r2
+ shll8 r2
+ mov #3, r1
+ mov #0, r0
+ or #170, r0
+ mov r0, r3
+ mov r2, r0
+ mov.b r3, @(r0, r1)
+
+ # Load the value back into a different register.
+ mov.b @(r0, r1), r4
+ # Check the lowest order byte matches the stored value.
+ mov r4, r0
+ and #255, r0
+ cmp/eq r0, r3
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.b r0, @($imm8, gbr) -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #0, r0
+ or #170, r0
+ mov r0, r3
+ mov #30, r2
+ ldc r2, gbr
+ mov.b r0, @(40, gbr)
+
+ # Load the value back into a different register.
+ mov.b @(40, gbr), r0
+ # Check the lowest order byte matches the stored value.
+ and #255, r0
+ cmp/eq r0, r3
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for mov.b r0, @($imm4, rm) -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #0, r0
+ or #170, r0
+ mov r0, r3
+ mov #30, r2
+ mov.b r0, @(3, r2)
+
+ # Load the value back into a different register.
+ mov.b @(3, r2), r0
+ and #255, r0
+ cmp/eq r3, r0
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for mov.b @$rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #30, r2
+ shll8 r2
+ # Store something first.
+ mov #0, r0
+ or #170, r0
+ mov r0, r7
+ mov.b r7, @r2
+ # Load it back.
+ mov.b @r2, r1
+ mov r1, r0
+ and #255, r0
+ cmp/eq r7, r0
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.b @${rm}+, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #30, r1
+ shll8 r1
+ # Store addr.
+ mov r1, r8
+
+ # Store something there first.
+ mov #0, r0
+ or #170, r0
+ mov r0, r7
+ mov.b r7, @r1
+ # Load it back.
+ mov.b @r1+, r2
+ mov r2, r0
+ and #255, r0
+ cmp/eq r7, r0
+ bf wrong
+
+ # Test address for post-incrementing.
+ add #1, r8
+ cmp/eq r8, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for mov.b @(r0, $rm), $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #30, r0
+ shll8 r0
+ mov #14, r1
+ # Store something there first.
+ mov #0, r0
+ or #170, r0
+ mov r0, r7
+ mov.b r7, @(r0, r1)
+ # Load it back.
+ mov.b @(r0, r1), r2
+ mov r2, r0
+ and #255, r0
+ cmp/eq r0, r7
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.b @($imm8, gbr), r0 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #30, r0
+ shll8 r0
+ ldc r0, gbr
+ # Store something there first.
+ mov #0, r0
+ or #170, r0
+ mov r0, r7
+ mov.b r0, @(3, gbr)
+ # Load it back.
+ mov.b @(3, gbr), r0
+ and #255, r0
+ cmp/eq r7, r0
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for movca.l r0, @$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global movcal
+movcal:
+ mov #1, r0
+ rotr r0
+ add #128, r0
+ mov #40, r1
+ shll8 r1
+ movca.l r0, @r1
+
+ # Load the word back in.
+ mov.l @r1, r3
+ cmp/eq r0, r3
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for mov #$imm8, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global movi
+movi:
+ mov #0, r0
+ cmp/eq #0, r0
+ bf wrong
+
+ mov #1, r0
+ cmp/eq #1, r0
+ bf wrong
+
+ mov #255, r0
+ cmp/eq #255, r0
+ bf wrong
+
+ mov #1, r15
+ mov #1, r0
+ cmp/eq r0, r15
+ bf wrong
+
+ mov #255, r15
+ mov r15, r0
+ cmp/eq r0, r15
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for mov.l $rm, @$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #30, r1
+ shll8 r1
+init:
+ # Build up a distinctive bit pattern.
+ mov #1, r2
+ shll8 r2
+ add #12, r2
+ shll8 r2
+ add #85, r2
+ shll8 r2
+ add #170, r2
+
+ mov.l r2, @r1
+
+ # Load it back.
+ mov.l @r1, r3
+ cmp/eq r2, r3
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.l @($imm8x4, pc), $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+init:
+ # Build up a distinctive bit pattern.
+ mov #1, r2
+ shll8 r2
+ add #12, r2
+ shll8 r2
+ add #85, r2
+ shll8 r2
+ add #170, r2
+
+ # Store to memory.
+ mov #16, r1
+ shll8 r1
+ add #32, r1
+ mov.l r2, @r1
+check:
+ # Read it back.
+ mov.l @(12, pc), r0
+ cmp/eq r2, r0
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.l @($imm4x4, $rm), $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #30, r0
+ shll8 r0
+ # Build up a distinctive bit pattern.
+ mov #1, r2
+ shll8 r2
+ add #12, r2
+ shll8 r2
+ add #85, r2
+ shll8 r2
+ add #170, r2
+ # Store something first.
+ mov.l r2, @(12, r0)
+
+check:
+ # Read it back.
+ mov.l @(12, r0), r1
+ cmp/eq r2, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for mov.l $rm, @-$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ mov #30, r1
+ shll8 r1
+ # Save address.
+ mov r1, r7
+
+init:
+ # Build up a distinctive bit pattern.
+ mov #1, r2
+ shll8 r2
+ add #12, r2
+ shll8 r2
+ add #85, r2
+ shll8 r2
+ add #170, r2
+ mov.l r2, @-r1
+
+check:
+ # Compare the value loaded into another reg.
+ mov.l @r1, r3
+ cmp/eq r2, r3
+ bf wrong
+
+dec:
+ # Ensure address is decremented.
+ mov #4, r6
+ sub r6, r7
+ cmp/eq r1, r7
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.l $rm, @(r0, $rn)
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+setaddr:
+ mov #0, r0
+ mov #30, r1
+ shll8 r1
+
+init:
+ # Build up a distinctive bit pattern.
+ mov #1, r2
+ shll8 r2
+ add #12, r2
+ shll8 r2
+ add #85, r2
+ shll8 r2
+ add #170, r2
+
+ mov.l r2, @(r0, r1)
+
+check:
+ # Load it back.
+ mov.l @(r0, r1), r3
+ cmp/eq r2, r3
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.l r0, @($imm8x4, gbr) -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+setaddr:
+ mov #30, r1
+ shll8 r1
+ ldc r1, gbr
+
+init:
+ # Build up a distinctive bit pattern.
+ mov #1, r0
+ shll8 r0
+ add #12, r0
+ shll8 r0
+ add #85, r0
+ shll8 r0
+ add #170, r0
+ # Preserve.
+ mov r0, r7
+
+ mov.l r0, @(4, gbr)
+check:
+ # Load it back.
+ mov.l @(4, gbr), r0
+ cmp/eq r0, r7
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for mov.l $rm, @($imm4x4, $rn) -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+setaddr:
+ mov #30, r1
+ shll8 r1
+
+init:
+ # Build up a distinctive bit pattern.
+ mov #1, r0
+ shll8 r0
+ add #12, r0
+ shll8 r0
+ add #85, r0
+ shll8 r0
+ add #170, r0
+ # Preserve.
+ mov r0, r7
+
+ mov.l r0, @(4, r1)
+check:
+ # Load it back.
+ mov.l @(4, r1), r0
+ cmp/eq r7, r0
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.l @$rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ mov #30, r0
+ shll8 r0
+ # Store something there first.
+ mov #170, r1
+ mov.l r1, @r0
+check:
+ # Load it back.
+ mov.l @r0, r3
+ cmp/eq r1, r3
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for mov.l @$rm+, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ mov #30, r0
+ shll8 r0
+ # Preserve address.
+ mov r0, r7
+ # Store something first.
+ mov #170, r3
+ mov.l r3, @r0
+
+ mov.l @r0+, r1
+check:
+ cmp/eq r1, r3
+ bf wrong
+
+ # Ensure address is post-incremented.
+ add #4, r7
+ cmp/eq r7, r0
+ bf wrong
+
+equal:
+ # Test rm = rn.
+ mov #30, r0
+ shll8 r0
+ mov.l @r0+, r0
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.l @(r0, $rm), $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #0, r0
+ mov #30, r1
+ shll8 r1
+ # Store something there first.
+ mov #170, r3
+ mov.l r3, @(r0, r1)
+check:
+ # Load it back.
+ mov.l @(r0, r1), r2
+ cmp/eq r2, r3
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.l @($imm8x4, gbr), r0 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #30, r1
+ shll8 r1
+ ldc r1, gbr
+ # Store something there first.
+ mov #170, r0
+ mov r0, r7
+ mov.l r0, @(12, gbr)
+check:
+ # Load it back.
+ mov.l @(12, gbr), r0
+ cmp/eq r0, r7
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for movt $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global movt
+init:
+ sett
+ movt r1
+ assert r1, #1
+clear:
+ clrt
+ movt r1
+ assert r1, #0
+set:
+ sett
+ movt r1
+ assert r1, #1
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for mov.w $rm, @$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ mov #30, r1
+ shll8 r1
+init:
+ # Build up a distinctive bit pattern.
+ mov #1, r2
+ shll8 r2
+ add #12, r2
+ mov.w r2, @r1
+check:
+ # Read it back.
+ mov.w @r1, r3
+ shll16 r2
+ shll16 r3
+ cmp/eq r2, r3
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.w @($imm8x2, pc), $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ # Build up a distinctive bit pattern.
+ mov #1, r2
+ shll8 r2
+ add #12, r2
+
+ # Store to memory.
+ mov #16, r1
+ shll8 r1
+ add #32, r1
+ mov.w r2, @r1
+
+check:
+ # Read it back.
+ mov.w @(18, pc), r0
+ shll16 r0
+ shll16 r2
+ cmp/eq r0, r2
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.w @($imm4x2, $rm), r0 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #30, r1
+ shll8 r1
+
+ # Build up a distinctive bit pattern.
+ mov #1, r0
+ shll8 r0
+ add #12, r0
+
+ # Preserve r0.
+ mov r0, r3
+
+ # Store something first.
+ mov.w r0, @(12, r1)
+
+check:
+ # Read it back.
+ mov.w @(12, r1), r0
+ shll16 r0
+ shll16 r3
+ cmp/eq r0, r3
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for mov.w $rm, @-$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ mov #30, r1
+ shll8 r1
+ # Preserve.
+ mov r1, r7
+init:
+ # Build up a distinctive bit pattern.
+ mov #1, r2
+ shll8 r2
+ add #12, r2
+store:
+ mov.w r2, @-r1
+check:
+ # Read it back.
+ mov.w @r1, r3
+ shll16 r2
+ shll16 r3
+ cmp/eq r2, r3
+ bf wrong
+dec:
+ add #2, r1
+ cmp/eq r7, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.w $rm, @(r0, $rn) -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ mov #0, r0
+ mov #30, r1
+ shll8 r1
+init:
+ # Build up a distinctive bit pattern.
+ mov #1, r2
+ shll8 r2
+ add #12, r2
+ mov.w r2, @(r0, r1)
+check:
+ # Read it back.
+ mov.w @(r0, r1), r3
+ shll16 r2
+ shll16 r3
+ cmp/eq r2, r3
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for mov.w r0, @($imm8x2, gbr) -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ mov #30, r0
+ shll8 r0
+ ldc r0, gbr
+
+init:
+ # Build up a distinctive bit pattern.
+ mov #1, r0
+ shll8 r0
+ add #12, r0
+ # Preserve r0.
+ mov r0, r7
+ mov.w r0, @(12, gbr)
+check:
+ mov.w @(12, gbr), r0
+ cmp/eq r0, r7
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for mov.w r0, @($imm4x2, $rn) -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #30, r1
+ shll8 r1
+
+init:
+ # Build up a distinctive bit pattern.
+ mov #1, r0
+ shll8 r0
+ add #12, r0
+ # Preserve.
+ mov r0, r7
+move:
+ mov.w r0, @(12, r1)
+check:
+ mov.w @(12, r1), r0
+ shll16 r0
+ shll16 r7
+ cmp/eq r0, r7
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for mov.w @$rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ mov #30, r0
+ shll8 r0
+
+ # Store something first.
+ # Build up a distinctive bit pattern.
+ mov #1, r2
+ shll8 r2
+ add #12, r2
+ mov.w r2, @r0
+
+check:
+ # Read it back.
+ mov.w @r0, r1
+ cmp/eq r1, r2
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for mov.w @${rm}+, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #30, r0
+ shll8 r0
+ # Preserve address.
+ mov r0, r7
+
+ # Store something first.
+ # Build up a distinctive bit pattern.
+ mov #1, r2
+ shll8 r2
+ add #12, r2
+ mov.w r2, @r0
+check:
+ # Read it back.
+ mov.w @r0+, r3
+ cmp/eq r2, r3
+ bf wrong
+
+inc:
+ # Ensure address is post-incremented.
+ add #2, r7
+ cmp/eq r0, r7
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for mov.w @(r0, $rm), $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #30, r0
+ shll8 r0
+ mov #10, r1
+
+ # Store something first.
+ # Build up a distinctive bit pattern.
+ mov #1, r2
+ shll8 r2
+ add #12, r2
+
+ mov.w r2, @(r0, r1)
+check:
+ # Read it back.
+ mov.w @(r0, r1), r3
+ shll16 r2
+ shll16 r3
+ cmp/eq r2, r3
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mov.w @($imm8x2, gbr), r0 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ mov #30, r0
+ shll8 r0
+ ldc r0, gbr
+
+ # Store something first.
+ # Build up a distinctive bit pattern.
+ mov #1, r0
+ shll8 r0
+ add #12, r0
+ # Preserve r0.
+ mov r0, r7
+ mov.w r0, @(12, gbr)
+
+check:
+ # Load it back.
+ mov.w @(12, gbr), r0
+ shll16 r0
+ shll16 r7
+ cmp/eq r0, r7
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mul.l $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global mull
+mull:
+ mov #3, r0
+ mov #5, r1
+ mul.l r0, r1
+
+ # Check the result.
+ sts macl, r3
+ mov #15, r4
+ cmp/eq r3, r4
+ bf wrong
+
+lxs:
+ # Large * small.
+ mov #255, r0
+ mov #0, r1
+ mul.l r0, r1
+
+ # Check the result.
+ sts macl, r3
+ mov #0, r4
+ cmp/eq r3, r4
+ bf wrong
+
+sxl:
+ # Small * large.
+ mov #0, r0
+ mov #255, r1
+ mul.l r0, r1
+
+ # Check the result.
+ sts macl, r3
+ mov #0, r4
+ cmp/eq r3, r4
+ bf wrong
+
+lxl:
+ # Large * large.
+ mov #1, r0
+ neg r0, r0
+ mov #2, r1
+ mul.l r0, r1
+
+ # Check the result.
+ sts macl, r3
+ mov #2, r4
+ neg r4, r4
+ cmp/eq r3, r4
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for muls.w $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ sts mach, r7
+
+ .global mulsw
+zero:
+ mov #0, r0
+ mov #1, r1
+ muls.w r0, r1
+
+ # Check the result.
+ sts macl, r3
+ mov #0, r4
+ cmp/eq r3, r4
+ bf wrong
+
+sxs:
+ # Small * small.
+ mov #1, r0
+ mov #2, r1
+ muls.w r0, r1
+
+ # Check the result.
+ sts macl, r3
+ mov #2, r4
+ cmp/eq r3, r4
+ bf wrong
+
+sxl:
+ # Small * large.
+ mov #1, r0
+ mov #255, r1
+ shll8 r1
+ muls.w r0, r1
+
+ # Check the result.
+ sts macl, r3
+ mov #0, r4
+ not r4, r4
+ shll8 r4
+ cmp/eq r3, r4
+ bf wrong
+
+lxs:
+ # Large * small.
+ mov #255, r0
+ shll8 r0
+ mov #1, r1
+ muls.w r0, r1
+
+ # Check the result.
+ sts macl, r3
+ mov #0, r4
+ not r4, r4
+ shll8 r4
+ cmp/eq r3, r4
+ bf wrong
+
+lxl:
+ # Large * large.
+ mov #255, r0
+ shll8 r0
+ mov #255, r1
+ shll8 r1
+ muls.w r0, r1
+
+ # Check the result.
+ sts macl, r3
+ mov #1, r4
+ shll16 r4
+ cmp/eq r3, r4
+ bf wrong
+
+invariant:
+ # Ensure MACH is invariant.
+ sts mach, r8
+ cmp/eq r7, r8
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mulu.w $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ sts mach, r7
+
+ .global mulsw
+zero:
+ mov #0, r0
+ mov #1, r1
+ mulu.w r0, r1
+
+ # Check the result.
+ sts macl, r1
+ mov #0, r0
+ cmp/eq r0, r1
+ bf wrong
+
+sxs:
+ # Small * small.
+ mov #1, r0
+ mov #2, r1
+ mulu.w r0, r1
+
+ # Check the result.
+ sts macl, r1
+ mov #2, r0
+ cmp/eq r0, r1
+ bf wrong
+
+sxl:
+ # Small * large.
+ mov #1, r1
+ mov #0, r0
+ or #255, r0
+ shll8 r0
+ mulu.w r1, r0
+
+ # Check the result.
+ sts macl, r1
+ mov #0, r0
+ or #255, r0
+ shll8 r0
+ cmp/eq r0, r1
+ bf wrong
+
+lxs:
+ # Large * small.
+ mov #0, r0
+ or #255, r0
+ shll8 r0
+ mov #1, r1
+ mulu.w r0, r1
+
+ # Check the result.
+ sts macl, r1
+ mov #0, r0
+ or #255, r0
+ shll8 r0
+ cmp/eq r0, r1
+ bf wrong
+
+lxl:
+ # Large * large.
+ mov #0, r0
+ or #255, r0
+ shll8 r0
+ mov r0, r1
+ mulu.w r0, r1
+
+ # Check the result.
+ sts macl, r1
+ mov #0, r0
+ or #254, r0
+ shll8 r0
+ or #1, r0
+ shll16 r0
+ cmp/eq r0, r1
+ bf wrong
+
+invariant:
+ # Ensure MACH is invariant.
+ sts mach, r8
+ cmp/eq r7, r8
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for neg $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ .macro signbit sign
+ shlr16 r1
+ shlr8 r1
+ shlr r1
+ shlr r1
+ shlr r1
+ shlr r1
+ shlr r1
+ shlr r1
+ shlr r1
+ assert r1, \sign
+ .endm
+ start
+
+ .global neg
+neg:
+ mov #0, r0
+ neg r0, r1
+ signbit #0
+
+ mov #42, r0
+ neg r0, r1
+ signbit #1
+
+ mov #0, r0
+ or #25, r0
+ neg r0, r1
+ signbit #1
+
+ # neg(0) is 0.
+ mov #0, r0
+ neg r0, r1
+ signbit #0
+
+ # neg(neg(x)) = x.
+ mov #42, r0
+ neg r0, r1
+ signbit #1
+ mov #42, r0
+ neg r0, r2
+ neg r2, r1
+ signbit #0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for negc $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ .macro signbit sign
+ mov r1, r2
+ shlr16 r2
+ shlr8 r2
+ shlr r2
+ shlr r2
+ shlr r2
+ shlr r2
+ shlr r2
+ shlr r2
+ shlr r2
+ assert r2, \sign
+ .endm
+ start
+
+ .global negc
+negc:
+ clrt
+ mov #1, r0
+ negc r0, r1
+ signbit #1
+
+negc2:
+ sett
+ mov #1, r0
+ negc r0, r1
+ signbit #1
+
+negc3:
+ clrt
+ mov #0, r0
+ negc r0, r1
+ signbit #0
+
+negc4:
+ sett
+ mov #0, r0
+ negc r0, r1
+ signbit #1
+
+negc5:
+ clrt
+ mov #0, r0
+ or #255, r0
+ negc r0, r1
+ signbit #1
+
+negc6:
+ sett
+ mov #0, r0
+ or #255, r0
+ negc r0, r1
+ signbit #1
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for nop
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global nop
+nop:
+ nop
+ pass
--- /dev/null
+# sh testcase for not $rm64, $rn64 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global not
+not:
+ mov #0, r0
+ or #192, r0
+ not r0, r1
+
+ mov #0, r0
+ or #255, r0
+ shll8 r0
+ or #255, r0
+ shll8 r0
+ or #255, r0
+ shll8 r0
+ or #63, r0
+
+ cmp/eq r0, r1
+ bf wrong
+
+ones:
+ mov #0, r1
+ not r1, r2
+
+ mov #0, r0
+ or #255, r0
+ shll8 r0
+ or #255, r0
+ shll8 r0
+ or #255, r0
+ shll8 r0
+ or #255, r0
+ cmp/eq r0, r2
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for ocbi @$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+ .global ocbi
+ocbi:
+ ocbi @r0
+ ocbi @r1
+ ocbi @r15
+ pass
--- /dev/null
+# sh testcase for ocbp @$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global ocbp
+ocbp:
+ ocbp @r0
+ ocbp @r1
+ ocbp @r15
+ pass
--- /dev/null
+# sh testcase for ocbwb @$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global ocbwb
+ocbwb:
+ ocbwb @r0
+ ocbwb @r1
+ ocbwb @r15
+ pass
--- /dev/null
+# sh testcase for or $rm64, $rn64 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global or
+or:
+ mov #1, r0
+ rotr r0
+ mov #1, r1
+ or r0, r1
+
+ mov #1, r7
+ rotr r7
+ add #1, r7
+ cmp/eq r7, r1
+ bf wrong
+
+ .global or2
+or2:
+ mov #85, r0
+ shll16 r0
+ shll8 r0
+ mov #85, r1
+ shll8 r1
+ or r0, r1
+
+ mov #85, r7
+ shll16 r7
+ add #85 ,r7
+ shll8 r7
+ cmp/eq r1, r7
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for or.b #$imm8, @(r0, gbr) -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global orb
+init:
+ # Init GBR and R0.
+ mov #30, r0
+ ldc r0, gbr
+ mov #40, r0
+
+orb:
+ or.b #0, @(r0, gbr)
+ or.b #170, @(r0, gbr)
+ or.b #0, @(r0, gbr)
+ or.b #255, @(r0, gbr)
+
+okay:
+ pass
--- /dev/null
+# sh testcase for or #$imm8, r0 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global ori
+ori:
+ mov #1, r0
+ rotr r0
+ or #1, r0
+
+ mov #1, r7
+ rotr r7
+ add #1, r7
+ cmp/eq r0, r7
+ bf wrong
+
+ .global ori2
+ori2:
+ mov #85, r0
+ shll16 r0
+ shll8 r0
+ or #85, r0
+
+ mov #85, r7
+ shll16 r7
+ shll8 r7
+ add #85, r7
+ cmp/eq r0, r7
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for pref @$rn
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global pref
+pref:
+ pref @r0
+ pref @r1
+ pref @r15
+ pass
--- /dev/null
+# sh testcase for rotcl $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global rotcl
+
+rotcl:
+ clrt
+ mov #1, r1
+ rotcl r1
+ assert r1, #2
+ clrt
+ rotcl r1
+ assert r1, #4
+ clrt
+ rotcl r1
+ assert r1, #8
+ clrt
+ rotcl r1
+ assert r1, #16
+ clrt
+ rotcl r1
+ assert r1, #32
+ clrt
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ bf wrong
+ rotcl r1
+ assert r1, #1
+
+ bra trotcl
+ nop
+
+wrong:
+ fail
+
+trotcl:
+ sett
+ mov #1, r1
+ rotcl r1
+ assert r1, #3
+ clrt
+ rotcl r1
+ assert r1, #6
+ clrt
+ rotcl r1
+ assert r1, #12
+ clrt
+ rotcl r1
+ assert r1, #24
+ clrt
+ rotcl r1
+ assert r1, #48
+ clrt
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ rotcl r1
+ bf wrong2
+ assert r1, #1
+ rotcl r1
+ rotcl r1
+
+okay:
+ pass
+wrong2:
+ fail
--- /dev/null
+# sh testcase for rotcr $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global rotcr
+rotcr:
+ clrt
+ mov #1, r1
+ rotcr r1
+ bf wrong
+ assert r1, #0
+ sett
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ assert r1, #1
+ rotcr r1
+ bf wrong
+
+trotcr:
+ sett
+ mov #1, r1
+ rotcr r1
+ bf wrong
+ sett
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ rotcr r1
+ bf wrong
+ assert r1, #1
+ rotcr r1
+ bf wrong
+ rotcr r1
+
+okay:
+ pass
+wrong:
+ fail
+
+
--- /dev/null
+# sh testcase for rotl $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global rotl
+rotl:
+ mov #1, r1
+ rotl r1
+ assert r1, #2
+ rotl r1
+ assert r1, #4
+ rotl r1
+ assert r1, #8
+ rotl r1
+ assert r1, #16
+ rotl r1
+ assert r1, #32
+ rotl r1
+ assert r1, #64
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ rotl r1
+ bf wrong
+ assert r1, #1
+ rotl r1
+ rotl r1
+ rotl r1
+ assert r1, #8
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for rotr $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global rotr
+rotr:
+ mov #1, r1
+ rotr r1
+ bf wrong
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ rotr r1
+ assert r1, #1
+ rotr r1
+ rotr r1
+ rotr r1
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for rts -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global rts
+rts:
+ bsr subroutine
+slot:
+ nop
+return:
+ pass
+ fail
+
+subroutine:
+ rts
+rts_slot:
+ nop
+bad:
+ fail
--- /dev/null
+# sh testcase for sets -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global sets
+sets:
+ sets
+ pass
--- /dev/null
+# sh testcase for sett -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global sett
+sett:
+ sett
+ bf wrong
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for shad $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global null
+null:
+ mov #1, r0
+ mov #0, r1
+ shad r1, r0
+ # no shift is performed.
+ assert r0, #1
+
+ .global gt0
+gt0:
+ mov #4, r0
+ mov #3, r1
+ shad r1, r0
+ # shift left 3 bits.
+ assert r0, #32
+
+ .global lt0
+lt0:
+ mov #32, r0
+ mov #3, r1
+ neg r1, r1
+ shad r1, r0
+ # shift right 3 bits.
+ assert r0, #4
+
+ .global fillpos
+fillpos:
+ mov #1, r0
+ mov #1, r1
+ rotr r1
+ shad r1, r0
+ # check result.
+ assert r0, #0
+
+ .global fillneg
+fillneg:
+ mov #1, r0
+ neg r0, r0
+ mov #1, r1
+ rotr r1
+ shad r1, r0
+ # check result.
+ not r0, r0
+ assert r0, #0
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for shal $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global shal
+shal:
+ mov #1, r1
+ shal r1
+ assert r1, #2
+ shal r1
+ assert r1, #4
+ shal r1
+ assert r1, #8
+ shal r1
+ assert r1, #16
+ shal r1
+ assert r1, #32
+ shal r1
+ assert r1, #64
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ shal r1
+ assert r1, #0
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for shar $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global shar
+shar:
+ mov #0, r0
+ or #192, r0
+ shar r0
+ bt wrong
+ shar r0
+ bt wrong
+ shar r0
+ bt wrong
+ shar r0
+ bt wrong
+ shar r0
+ bt wrong
+ shar r0
+ bt wrong
+ shar r0
+ bf wrong
+ shar r0
+ bf wrong
+ shar r0
+ bt wrong
+ shar r0
+ bt wrong
+ assert r0, #0
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for shld $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global null
+null:
+ mov #1, r0
+ mov #0, r1
+ shld r1, r0
+ # no shift is performed.
+ assert r0, #1
+
+ .global gt0
+gt0:
+ mov #4, r0
+ mov #3, r1
+ shld r1, r0
+ # shift left 3 bits.
+ assert r0, #32
+
+ .global lt0
+lt0:
+ mov #32, r0
+ mov #3, r1
+ neg r1, r1
+ shld r1, r0
+ # shift right 3 bits.
+ assert r0, #4
+
+ .global fill
+fill:
+ mov #1, r0
+ rotr r0
+ mov #1, r1
+ rotr r1
+ shld r1, r0
+ assert r0, #0
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for shll $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global shll
+shll:
+ mov #1, r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ shll r1
+ assert r1, #0
+another:
+ mov #1, r1
+ shll r1
+ shll r1
+ shll r1
+ assert r1, #8
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for shll16 $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global shll16
+shll16:
+ mov #108, r1
+ shll16 r1
+ shll16 r1
+ assert r1, #0
+
+another:
+ mov #1, r1
+ shll16 r1
+ mov #1, r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ cmp/eq r1, r7
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for shll2 $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global shll2
+shll2:
+ mov #1, r1
+ shll2 r1
+ shll2 r1
+ shll2 r1
+ shll2 r1
+ shll2 r1
+ shll2 r1
+ shll2 r1
+ shll2 r1
+ shll2 r1
+ shll2 r1
+ shll2 r1
+ shll2 r1
+ shll2 r1
+ shll2 r1
+ shll2 r1
+ shll2 r1
+ assert r1, #0
+
+another:
+ mov #1, r1
+ shll2 r1
+ assert r1, #4
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for shll8 $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global shll8
+shll8:
+ mov #1, r1
+ shll8 r1
+ shll8 r1
+ shll8 r1
+ shll8 r1
+ assert r1, #0
+
+another:
+ mov #1, r1
+ shll8 r1
+ mov #1, r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ shll r7
+ cmp/eq r1, r7
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for shlr $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global shlr
+shlr:
+ mov #0, r0
+ or #192, r0
+ shlr r0
+ shlr r0
+ shlr r0
+ shlr r0
+ shlr r0
+ shlr r0
+ # Make sure a bit is shifted into T.
+ shlr r0
+ bf wrong
+ # Ditto.
+ shlr r0
+ bf wrong
+ shlr r0
+ assert r0, #0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for shlr16 $rn
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global shrl16
+shrl16:
+ shlr16 r0
+
+ pass
--- /dev/null
+# sh testcase for shlr2 $rn
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global shrl2
+shrl2:
+ shlr2 r0
+
+ pass
--- /dev/null
+# sh testcase for shlr8 $rn
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global shrl8
+shrl8:
+ shlr8 r0
+
+ pass
--- /dev/null
+# sh testcase for stc gbr, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global stc_gbr
+stc_gbr:
+ stc gbr, r1
+ mov #42, r1
+ ldc r1, gbr
+ stc gbr, r2
+ cmp/eq r1, r2
+ bf wrong
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for stc.l gbr, @-$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global stcl_gbr
+stcl_gbr:
+ mov #42, r0
+ ldc r0, gbr
+ mov #40, r0
+ shll8 r0
+ # save address
+ mov r0, r1
+ stc.l gbr, @-r0
+
+ add #4, r0
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for sts fpscr, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global sts_fpscr
+sts_fpscr:
+ sts fpscr, r0
+ mov #42, r0
+ lds r0, fpscr
+ sts fpscr, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for sts fpul, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global sts_fpul
+sts_fpul:
+ # This is properly exercised by the lds-fpul test case.
+ sts fpul, r1
+ pass
--- /dev/null
+# sh testcase for sts mach, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global sts_mach
+sts_mach:
+ mov #42, r0
+ lds r0, mach
+ sts mach, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for sts macl, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global sts_macl
+sts_macl:
+ mov #42, r0
+ lds r0, macl
+ sts macl, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for sts pr, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global sts_pr
+sts_pr:
+ mov #42, r0
+ lds r0, pr
+ sts pr, r1
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for sts.l fpscr, @-$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global stsl_fpscr
+stsl_fpscr:
+ mov #40, r0
+ shll8 r0
+ # Preserve r0.
+ mov r0, r7
+ sts.l fpscr, @-r0
+
+check:
+ # Ensure r0 is decremented.
+ add #4, r0
+ cmp/eq r0, r7
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for sts.l fpul, @-$rn -*- Asm -*_
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global stsl_fpul
+stsl_fpul:
+ mov #40, r0
+ shll8 r0
+ # Preserve r0.
+ mov r0, r7
+ sts.l fpul, @-r0
+
+dec:
+ # Check for proper pre-decrementing.
+ add #4, r0
+ cmp/eq r0, r7
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for sts.l mach, @-$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global stsl_mach
+stsl_mach:
+ # Build up a distinctive bit pattern.
+ mov #1, r0
+ shll8 r0
+ add #12, r0
+ shll8 r0
+ add #85, r0
+ shll8 r0
+ add #170, r0
+
+ lds r0, mach
+ mov #40, r2
+ shll8 r2
+ # Preserve r2.
+ mov r2, r7
+ sts.l mach, @-r2
+
+ # check results.
+ mov.l @r2, r3
+ cmp/eq r0, r3
+ bf wrong
+
+ # Ensure decrement occurred.
+ add #4, r2
+ cmp/eq r2, r7
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for sts.l macl, @-$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global stsl_macl
+stsl_macl:
+ # Build up a distinctive bit pattern.
+ mov #1, r0
+ shll8 r0
+ add #12, r0
+ shll8 r0
+ add #85, r0
+ shll8 r0
+ add #170, r0
+
+ lds r0, macl
+ mov #40, r2
+ shll8 r2
+ # Preserve r2.
+ mov r2, r7
+ sts.l macl, @-r2
+
+ # check results.
+ mov.l @r2, r3
+ cmp/eq r0, r3
+ bf wrong
+
+ # Ensure decrement occurred.
+ add #4, r2
+ cmp/eq r2, r7
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for sts.l pr, @-$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global stsl_pr
+stsl_pr:
+ # Build up a distinctive bit pattern.
+ mov #1, r0
+ shll8 r0
+ add #12, r0
+ shll8 r0
+ add #85, r0
+ shll8 r0
+ add #170, r0
+
+ lds r0, pr
+ mov #40, r2
+ shll8 r2
+ # Preserve r2.
+ mov r2, r7
+ sts.l pr, @-r2
+
+ # check results.
+ mov.l @r2, r3
+ cmp/eq r0, r3
+ bf wrong
+
+ # Ensure decrement occurred.
+ add #4, r2
+ cmp/eq r2, r7
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for sub $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global sub1
+sub1:
+ # 0 - x.
+ mov #0, r0
+ mov #3, r1
+ sub r1, r0
+
+ mov #2, r7
+ not r7, r7
+ cmp/eq r7, r0
+ bf wrong
+
+ .global sub2
+sub2:
+ # x - 0.
+ mov #0, r0
+ mov #3, r1
+ sub r0, r1
+ assert r1, #3
+
+ .global sub3
+sub3:
+ # x - y.
+ mov #4, r0
+ mov #3, r1
+ sub r0, r1
+
+ mov #0, r7
+ not r7, r7
+ cmp/eq r7, r1
+ bf wrong
+
+ .global sub4
+sub4:
+ # y - x.
+ mov #4, r0
+ mov #3, r1
+ sub r1, r0
+ assert r0, #1
+
+ .global sub5
+sub5:
+ # y - y == 0 (where y are in two distinct registers).
+ mov #4, r0
+ mov #4, r1
+ sub r1, r0
+ assert r0, #0
+
+ .global sub6
+sub6:
+ # y - y = 0 (where y is the same register).
+ mov #4, r1
+ sub r1, r1
+ assert r1, #0
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for subc $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+zero:
+ mov #0, r0
+ mov #0, r1
+ clrt
+ subc r0, r1
+ assert r1, #0
+
+zerot:
+ mov #0, r0
+ mov #0, r1
+ sett
+ subc r0, r1
+ # Invert all 1's to all 0's for ease of comparison.
+ not r1, r1
+ assert r1, #0
+
+null:
+ mov #0, r0
+ mov #10, r1
+ clrt
+ subc r0, r1
+ assert r1, #10
+
+nullt:
+ mov #0, r0
+ mov #10, r1
+ sett
+ subc r0, r1
+ assert r1, #9
+
+subc:
+ mov #10, r0
+ mov #0, r1
+ clrt
+ subc r0, r1
+ # Again, invert ..
+ not r1, r1
+ assert r1, #9
+
+subct:
+ mov #10, r0
+ mov #0, r1
+ sett
+ subc r0, r1
+ # Again, invert ..
+ not r1, r1
+ assert r1, #10
+
+subc2:
+ mov #10, r0
+ mov #20, r1
+ clrt
+ subc r0, r1
+ assert r1, #10
+
+subc2t:
+ mov #20, r0
+ mov #10, r1
+ sett
+ subc r0, r1
+ # Again, invert ..
+ not r1, r1
+ assert r1, #10
+
+subc3:
+ mov #5, r0
+ mov #5, r1
+ clrt
+ subc r0, r1
+ assert r1, #0
+
+subc3t:
+ mov #5, r0
+ mov #5, r1
+ sett
+ subc r0, r1
+ # Again, invert ..
+ not r1, r1
+ assert r1, #0
+
+large:
+ mov #2, r0
+ mov #10, r1
+ clrt
+ subc r1, r0
+ # Again, invert ..
+ not r0, r0
+ assert r0, #7
+
+larget:
+ mov #2, r0
+ mov #10, r1
+ sett
+ subc r0, r1
+ assert r1, #7
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for subv $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+zero:
+ mov #0, r0
+ mov #0, r1
+ subv r0, r1
+ bt wrong
+ assert r1, #0
+
+one:
+ mov #10, r0
+ mov #0, r1
+ subv r0, r1
+ bt wrong
+ not r1, r1
+ assert r1, #9
+
+large:
+ # Produce MAXINT in R0.
+ mov #0, r0
+ not r0, r0
+ shlr r0
+
+ # Put -3 into R1.
+ mov #3, r1
+ neg r1, r1
+
+ # Subtract them and underflow.
+ subv r0, r1
+ bf wrong
+
+another:
+ # Produce MAXINT in R0.
+ mov #0, r0
+ not r0, r0
+ shlr r0
+
+ # Put -3 into R1.
+ mov #3, r1
+ neg r1, r1
+
+ # Subtract them and overflow.
+ subv r1, r0
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for swap.b $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+init:
+ # Build up a distinctive bit pattern.
+ mov #1, r0
+ shll8 r0
+ add #12, r0
+ shll8 r0
+ add #85, r0
+ shll8 r0
+ add #70, r0
+
+test:
+ # Swap the lower two bytes into a different register.
+ swap.b r0, r1
+ mov #1, r7
+ shll8 r7
+ add #12, r7
+ shll8 r7
+ add #70, r7
+ shll8 r7
+ add #85, r7
+ cmp/eq r1, r7
+ bf wrong
+
+swapback:
+ # Swap the lower two bytes into the same registers.
+ # R0 should now equal R1.
+ swap.b r1, r2
+ cmp/eq r0, r2
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for swap.w $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global swapw
+swapw:
+ # Build up a characteristic bit pattern in R0.
+ mov #85, r0
+ shll16 r0
+ add #3, r0
+ rotr r0
+ rotr r0
+ or #170, r0
+ # Preserve for later.
+ mov r0, r8
+
+test:
+ swap.w r0, r1
+ mov #64, r0
+ shll8 r0
+ or #170, r0
+ shll8 r0
+ or #192, r0
+ shll8 r0
+ or #21, r0
+ cmp/eq r1, r0
+ bf wrong
+
+swapback:
+ swap.w r1, r2
+ cmp/eq r2, r8
+ bf wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for tas.b @$rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+tasb1:
+ mov #40, r0
+ shll8 r0
+ tas.b @r0
+ bf wrong
+
+tasb2:
+ mov #40, r0
+ shll8 r0
+ tas.b @r0
+ bt wrong
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# Support macros for the assembly test cases.
+
+ .macro start
+ .text
+ .global start
+start:
+ .endm
+
+ # Perform a single to double precision floating point conversion.
+ .macro _s2d fpr dpr
+ flds \fpr, fpul
+ _setpr
+ fcnvsd fpul, \dpr
+ _clrpr
+ .endm
+
+ # Set the PR (PRecision) bit in the FPSCR.
+ .macro _setpr
+ sts fpscr, r7
+ mov #8, r8
+ shll16 r8
+ or r8, r7
+ lds r7, fpscr
+ .endm
+
+ # Clear the PR bit.
+ .macro _clrpr
+ sts fpscr, r7
+ mov #8, r8
+ shll16 r8
+ not r8, r8
+ and r8, r7
+ lds r7, fpscr
+ .endm
+
+ # nb: this macro clobbers R7.
+ .macro assert reg value
+ mov \value, r7
+ cmp/eq \reg, r7
+ bf wrong
+ .endm
+
+ .macro pass
+ trapa #253
+ .endm
+
+ .macro fail
+ trapa #254
+ .endm
--- /dev/null
+# sh testcase for trapa #$imm8 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global trapa
+trapa:
+ # pass is a macro for "trapa #253".
+ trapa #253
--- /dev/null
+# sh testcase for tst $rm, $rn
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global tst1
+tst1:
+ mov #0, r0
+ mov #0, r1
+ tst r0, r0
+ bf wrong
+
+test2:
+ mov #0, r0
+ mov #1, r1
+ tst r0, r1
+ bf wrong
+
+test3:
+ mov #0, r0
+ mov #1, r1
+ tst r1, r0
+ bf wrong
+
+test4:
+ mov #1, r0
+ mov #1, r1
+ tst r0, r1
+ bt wrong
+
+test5:
+ mov #1, r0
+ rotr r0
+ add #85, r0
+ shll16 r0
+ add #12, r0
+ mov #1, r1
+ rotr r1
+ add #85, r1
+ shll16 r1
+ add #12, r1
+ tst r0, r1
+ bt wrong
+
+test6:
+ mov #1, r0
+ rotr r0
+ add #85, r0
+ shll16 r0
+ add #12, r0
+ mov #1, r1
+ tst r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for tst.b #$imm8, @(r0, gbr) -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global orb
+init:
+ # Init GBR and R0.
+ mov #30, r0
+ ldc r0, gbr
+ mov #40, r0
+
+orb:
+ tst.b #0, @(r0, gbr)
+ bf wrong
+ tst.b #170, @(r0, gbr)
+ bf wrong
+ tst.b #0, @(r0, gbr)
+ bf wrong
+ tst.b #255, @(r0, gbr)
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for tst #$imm8, r0 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global tsti
+tsti:
+ mov #0, r0
+ tst #0, r0
+
+tsti2:
+ mov #0, r0
+ tst #1, r0
+
+tsti3:
+ mov #1, r0
+ tst #0, r0
+
+tsti4:
+ mov #1, r0
+ tst #1, r0
+
+tsti5:
+ mov #255, r0
+ tst #255, r0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for xor $rm64, $rn64 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global xor
+xor:
+ # 0 (+) 1 = 1.
+ mov #0, r0
+ mov #1, r1
+ xor r0, r1
+ assert r1, #1
+
+xor2:
+ # 1 (+) 0 = 0.
+ mov #1, r0
+ mov #0, r1
+ xor r0, r1
+ assert r1, #1
+
+xor3:
+ # 0 (+) 0 = 0.
+ mov #0, r0
+ mov #0, r1
+ xor r0, r1
+ assert r1, #0
+
+xor4:
+ # 0 (+) 0 = 0.
+ mov #0, r0
+ xor r0, r0
+ assert r0, #0
+
+xor5:
+ mov #0, r0
+ or #85, r0
+ shll16 r0
+ or #170, r0
+ mov r0, r1
+ mov #0, r0
+ or #85, r0
+ shll16 r0
+ or #170, r0
+ xor r1, r0
+ assert r0, #0
+
+xor6:
+ mov #0, r0
+ or #85, r0
+ shll16 r0
+ or #170, r0
+ mov r0, r1
+ mov #0, r0
+ or #85, r0
+ shll16 r0
+ or #12, r0
+ xor r0, r1
+ mov #0, r0
+ or #166, r0
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for xor.b #$imm8, @(r0, gbr) -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global orb
+init:
+ # Init GBR and R0.
+ mov #30, r0
+ ldc r0, gbr
+ mov #40, r0
+
+orb:
+ xor.b #0, @(r0, gbr)
+ xor.b #170, @(r0, gbr)
+ xor.b #0, @(r0, gbr)
+ xor.b #255, @(r0, gbr)
+
+okay:
+ pass
--- /dev/null
+# sh testcase for xor #$imm8, r0 -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+ .global xori
+xori:
+ # 0 (+) 1 = 1.
+ mov #0, r0
+ xor #1, r0
+ assert r0, #1
+
+xori2:
+ # 1 (+) 0 = 1.
+ mov #1, r0
+ xor #0, r0
+ assert r0, #1
+
+xori3:
+ # 1 (+) 1 = 0.
+ mov #1, r0
+ xor #1, r0
+ assert r0, #0
+
+xori4:
+ # 255 (+) 255 = 0.
+ mov #0, r0
+ or #255, r0
+ xor #255, r0
+ assert r0, #0
+
+xori5:
+ # 0 (+) 255 = 255.
+ mov #0, r0
+ xor #255, r0
+ mov r0, r1
+
+ mov #0, r0
+ or #255, r0
+ cmp/eq r0, r1
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for xtrct $rm, $rn -*- Asm -*-
+# mach: all
+# as: -isa=shcompact
+# ld: -m shelf32
+
+ .include "compact/testutils.inc"
+
+ start
+
+init:
+ mov #170, r0
+ shll8 r0
+ add #1, r0
+ shll8 r0
+ add #66, r0
+ shll8 r0
+ mov r0, r1
+
+ mov #85, r0
+ shll8 r0
+ add #2, r0
+ shll8 r0
+ add #42, r0
+ shll8 r0
+ add #3, r0
+
+copy:
+ mov r0, r3
+ mov r1, r4
+
+xtrct:
+ xtrct r0, r1
+
+check:
+ # Lower r3, upper r4.
+ shll16 r3
+ shlr16 r4
+ or r3, r4
+ cmp/eq r1, r4
+ bf wrong
+
+okay:
+ pass
+wrong:
+ fail
+
--- /dev/null
+# SH64 interworking testsuite.
+# In particular, test parts of the instruction set that can be used
+# for SHmedia/SHcompact instruction set mode switches.
+
+if [istarget sh64-*-*] {
+ # load support procs (none yet)
+ # load_lib cgen.exp
+
+ # all machines
+ set all_machs "sh5"
+
+ foreach src [lsort [glob -nocomplain $srcdir/$subdir/misc/*.s]] {
+ # If we're only testing specific files and this isn't one of them,
+ # skip it.
+ if ![runtest_file_p $runtests $src] {
+ continue
+ }
+ run_sim_test $src $all_machs
+ }
+}
--- /dev/null
+# SHmedia testsuite.
+
+if [istarget sh64-*-*] {
+ # load support procs (none yet)
+ # load_lib cgen.exp
+
+ # all machines
+ set all_machs "sh5"
+
+ # The .cgs suffix is for "cgen .s".
+ foreach src [lsort [glob -nocomplain $srcdir/$subdir/media/*.cgs]] {
+ # If we're only testing specific files and this isn't one of them,
+ # skip it.
+ if ![runtest_file_p $runtests $src] {
+ continue
+ }
+ run_sim_test $src $all_machs
+ }
+}
--- /dev/null
+2001-01-09 Ben Elliston <bje@redhat.com>
+
+ * nsb.cgs: Test consecutive bits of zeros as well as ones.
+ * ptb.cgs: Clean up.
+
+2001-01-08 Ben Elliston <bje@redhat.com>
+
+ * fcmpund.cgs, fcmpuns.cgs: Complete test cases.
+ * fcnvds.cgs, fcnvsd.cgs, fgetscr.cgs, fiprs.cgs: Ditto.
+ * floatld.cgs, floatls.cgs, floatqd.cgs, floatqs.cgs: Ditto.
+ * fmuld.cgs, fmuls.cgs, fputscr.cgs, fstxp.cgs: Ditto.
+ * fsubd.cgs, fsubs.cgs, ftrcdl.cgs, ftrcdq.cgs: Ditto.
+ * ftrcsl.cgs, ftrcsq.cgs, ftrvs.cgs: Ditto.
+ * ldhil.cgs, ldhiq.cgs, ldlol.cgs, ldloq.cgs: Ditto.
+ * mabsl.cgs, mabsw.cgs, maddl.cgs, maddsl.cgs: Ditto.
+ * maddsub.cgs, maddsw.cgs, maddw.cgs: Ditto.
+ * mcmpeqb.cgs, mcmpeql.cgs, mcmpeqw.cgs: Ditto.
+ * mcmpgtl.cgs, mcmpgtub.cgs, mcmpgtw.cgs: Ditto.
+ * mcmv.cgs, mcnvslw.cgs, mcnvswb.cgs, mcnvswub.cgs: Ditto.
+ * mmacfxwl.cgs, mmacnfx-wl.cgs: Ditto.
+ * mmulfxl.cgs, mmulfxrpw.cgs, mmulfxw.cgs: Ditto.
+ * mmulhiwl.cgs, mmull.cgs, mmullowl.cgs: Ditto.
+ * mmulsumwq.cgs, mmulw.cgs, movi.cgs: Ditto.
+ * mpermw.cgs, msadubq.cgs: Ditto.
+ * mshaldsl.cgs, mshaldsw.cgs: Ditto.
+ * mshardl.cgs, mshardsq.cgs, mshardw.cgs: Ditto.
+ * mshfhib.cgs, mshfhil.cgs, mshfhiw.cgs: Ditto.
+ * mshflob.cgs, mshflol.cgs, mshflow.cgs: Ditto.
+ * mshlldl.cgs, mshlldw.cgs, mshlrdl.cgs: Ditto.
+ * mshlrdw.cgs, msubl.cgs, msubsl.cgs: Ditto.
+ * msubsub.cgs, msubsw.cgs, msubw.cgs: Ditto.
+ * mulsl.cgs, mulul.cgs: Ditto.
+ * ptabs.cgs, ptb.cgs, ptrel.cgs: Ditto.
+ * shard.cgs, shardl.cgs, shari.cgs, sharil.cgs: Ditto.
+ * shlld.cgs, shlldl.cgs, shlli.cgs, shllil.cgs: Ditto.
+ * shlrd.cgs, shlrdl.cgs, shlri.cgs, shlril.cgs: Ditto.
+ * sthil.cgs, sthiq.cgs, swapq.cgs, trapa.cgs: Ditto.
+
+ * testutils.inc (pass): Pass correct "syscall" number.
+ (fail): Ditto.
+
+2000-12-13 Ben Elliston <bje@redhat.com>
+
+ * sub.cgs, subl.cgs: Complete test cases.
+ * ptrel.cgs: Likewise.
+
+ * shori.cgs: Test for zero extension of immediate operand.
+ * fcmpged.cgs, fcmpges.cgs, fldd.cgs: Complete test cases.
+ * fldp.cgs, flds.cgs, fldxd.cgs, fldxp.cgs: Likewise.
+ * fldxs.cgs, fmacs.cgs, fnegd.cgs, fnegs.cgs: Likewise.
+ * fsqrtd.cgs, fsqrts.cgs, fstd.cgs, fstp.cgs: Likewise.
+ * fsts.cgs, fstxd.cgs, fstxs.cgs: Likewise.
+
+2000-12-12 Ben Elliston <bje@redhat.com>
+
+ * testutils.inc (pass): Use simple syscall mechanism.
+ (fail): Likewise.
+ (_packb, _packw, _packl): New macros for packing slices.
+
+ * stb.cgs, stq.cgs, stxb.cgs, stxq.cgs: Complete test cases.
+ * stl.cgs, stw.cgs, stxl.cgs, stxw.cgs: Likewise.
+ * ldl.cgs, ldq.cgs, ldub.cgs, lduw.cgs, ldw.cgs: Likewise.
+ * ldxb.cgs, ldxl.cgs, ldxq.cgs, ldxub.cgs: Likewise.
+ * ldxuw.cgs, ldxw.cgs, nsb.cgs, trapa.cgs: Likewise.
+
+ * fcmpeqd.cgs, fcmpeqs.cgs, fcmpgtd.cgs: Complete test cases.
+ * fcmpgts.cgs, fdivd.cgs, fdivs.cgs, fmovd.cgs: Likewise.
+ * fmovdq.cgs, fmovqd.cgs, fmovls.cgs, fmovs.cgs: Likewise.
+ * fmovsl.cgs: Likewise.
+
+2000-12-11 Ben Elliston <bje@redhat.com>
+
+ * fabss.cgs, fabsd.cgs, fadds.cgs, faddd.cgs: Complete test cases.
+ * getcfg.cgs, getcon.cgs, gettr.cgs, icbi.cgs: Likewise.
+ * prefi.cgs, pta.cgs, ptabs.cgs, ptb.cgs: Likewise.
+ * putcon.cgs, putcfg.cgs, rte.cgs: Likewise.
+
+ * add.cgs, addi.cgs, addl.cgs, addil.cgs: Complete test cases.
+ * addl.cgs, addzl.cgs, alloco.cgs, and.cgs, andc.cgs: Likewise.
+ * andi.cgs, beq.cgs, beqi.cgs, bge.cgs, bgeu.cgs: Likewise.
+ * bgt.cgs, bgtu.cgs, blink.cgs, bne.cgs, bnei.cgs: Likewise.
+ * brk.cgs, byterev.cgs, cmpeq.cgs, cmpgt.cgs: Likewise.
+ * cmpgtu.cgs, cmveq.cgs, cmvne.cgs: Likewise.
+
+2000-12-07 Ben Elliston <bje@redhat.com>
+
+ * mextr1.cgs, mextr2.cgs, mextr3.cgs: Complete test cases.
+ * mextr4.cgs, mextr5.cgs, mextr6.cgs, mextr7.cgs: Likewise.
+
+2000-12-05 Ben Elliston <bje@redhat.com>
+
+ * nop.cgs, ocbi.cgs, ocbp.cgs, ocbwb.cgs: Complete test cases.
+ * or.cgs, ori.cgs, xor.cgs, xori.cgs: Ditto.
+ * sleep.cgs, synci.cgs, synco.cgs: Ditto.
+
+2000-11-22 Ben Elliston <bje@redhat.com>
+
+ * *.cgs: Include "media/testutils.inc", not "testutils.inc" as
+ generated test cases do. Miscellaneous fixes.
+
+ * testutils.inc: New file.
+ * *.cgs: Generate test cases.
--- /dev/null
+# sh testcase for add $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global add
+init:
+ pta wrong, tr0
+add:
+ movi 10, r0
+ movi 0, r1
+ add r0, r1, r3
+ movi 10, r4
+ bne r3, r4, tr0
+
+add0:
+ movi 1, r63
+ add r63, r63, r1
+ bnei r1, 0, tr0
+
+add2:
+ movi 0, r0
+ movi 10, r1
+ add r0, r1, r3
+ movi 10, r4
+ bne r3, r4, tr0
+
+add3:
+ movi 10, r1
+ add r63, r1, r3
+ movi 10, r4
+ bne r3, r4, tr0
+
+add4:
+ movi 10, r1
+ add r1, r63, r3
+ movi 10, r4
+ bne r3, r4, tr0
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for addi $rm, $disp10, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+addi1:
+ movi 1, r0
+ addi r0, 10, r0
+ bnei r0, 11, tr0
+
+addi2:
+ movi 10, r0
+ addi r0, 1, r0
+ bnei r0, 11, tr0
+
+addi3:
+ movi 10, r0
+ addi r0, -1, r0
+ bnei r0, 9, tr0
+
+addi4:
+ movi 20, r0
+ addi r0, -2, r0
+ bnei r0, 18, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for addi.l $rm, $disp10, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+addil0:
+ movi 1, r63
+ addi.l r63, 0, r1
+ bnei r1, 0, tr0
+
+addil1:
+ movi 10, r0
+ addi.l r0, 0, r3
+ bnei r3, 10, tr0
+
+addil2:
+ movi 0, r0
+ addi.l r0, 10, r2
+ bnei r2, 10, tr0
+
+addil3:
+ addi.l r63, 10, r1
+ bnei r1, 10, tr0
+
+addil4:
+ movi 10, r0
+ addi.l r0, 0, r1
+ bnei r1, 10, tr0
+
+addil5:
+ # Ensure top 32-bits are discarded when adding.
+ movi 10, r0
+ shlli r0, 32, r0
+ addi r0, 10, r0
+ addi.l r0, 10, r2
+ bnei r2, 20, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for add.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global addl
+init:
+ pta wrong, tr0
+
+addl0:
+ movi 1, r63
+ add.l r63, r63, r1
+ bnei r1, 0, tr0
+
+addl1:
+ movi 10, r0
+ movi 0, r1
+ add.l r0, r1, r3
+ movi 10, r4
+ bne r3, r4, tr0
+
+addl2:
+ movi 0, r0
+ movi 10, r1
+ add.l r0, r1, r2
+ movi 10, r3
+ bne r2, r3, tr0
+
+addl3:
+ movi 10, r0
+ add.l r63, r0, r1
+ movi 10, r2
+ bne r1, r2, tr0
+
+addl4:
+ movi 10, r0
+ add.l r0, r63, r1
+ movi 10, r2
+ bne r1, r2, tr0
+
+addl5:
+ # Ensure top 32-bits are discarded when adding.
+ movi 10, r0
+ shlli r0, 32, r0
+ addi r0, 10, r0
+ movi 10, r1
+ shlli r1, 32, r1
+ addi r1, 10, r1
+ add.l r0, r1, r2
+ movi 20, r3
+ bne r2, r3, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for addz.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+addzl1:
+ movi 1, r0
+ movi 2, r1
+ addz.l r0, r1, r2
+ bnei r2, 3, tr0
+
+addzl2:
+ movi 1, r0
+ shlli r0, 32, r0
+ addi r0, 2, r0
+ movi 1, r1
+ shlli r1, 32, r1
+ addi r1, 2, r1
+ addz.l r0, r1, r2
+ bnei r2, 4, tr0
+
+addzl3:
+ movi 1, r0
+ shlli r0, 31, r0
+ addi r0, 2, r0
+ movi 2, r1
+ addz.l r0, r1, r2
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for alloco $rm, $disp6x32 -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ alloco r0, 32
+ pass
--- /dev/null
+# sh testcase for and $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+and0:
+ # 0 and 0 is 0.
+ movi 0, r0
+ movi 0, r1
+ and r0, r1, r2
+ bnei r2, 0, tr0
+
+and1:
+ # 0 and 1 is 0.
+ movi 0, r0
+ movi 1, r1
+ and r0, r1, r2
+ bnei r2, 0, tr0
+
+and2:
+ # 1 and 0 is 0.
+ movi 1, r0
+ movi 0, r1
+ and r0, r1, r2
+ bnei r2, 0, tr0
+
+and3:
+ # 1 and 1 is 1.
+ movi 1, r0
+ movi 1, r1
+ and r0, r1, r2
+ bnei r2, 1, tr0
+
+and4:
+ movi 1, r0
+ shlli r0, 63, r0
+ movi 1, r1
+ shlli r1, 63, r1
+ and r0, r1, r2
+ # Check it.
+ movi 1, r3
+ shlli r3, 63, r3
+ bne r2, r3, tr0
+
+and5:
+ movi 1, r0
+ shlli r0, 63, r0
+ movi 1, r1
+ shlli r1, 63, r1
+ ori r1, 1, r1
+ and r0, r1, r2
+ # Check it.
+ movi 1, r3
+ shlli r1, 63, r1
+ bne r1, r2, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for andc $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+andc1:
+ # X . !X = 0.
+ movi 3, r0
+ movi 3, r1
+ andc r0, r1, r2
+ bnei r2, 0, tr0
+
+andc2:
+ # X . 0 = X.
+ movi 3, r0
+ movi 0, r1
+ andc r0, r1, r2
+ bnei r2, 3, tr0
+
+andc3:
+ # wide X . 0 = wide X.
+ movi 0x1020, r0
+ shlli r0, 8, r0
+ ori r0, 0x30, r0
+ shlli r0, 8, r0
+ ori r0, 0x40, r0
+ shlli r0, 8, r0
+ ori r0, 0x50, r0
+ shlli r0, 8, r0
+ ori r0, 0x60, r0
+ shlli r0, 8, r0
+ ori r0, 0x70, r0
+ shlli r0, 8, r0
+ ori r0, 0x80, r0
+ movi 0, r1
+ andc r0, r1, r2
+ bne r0, r2, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for andi $rm, $disp10, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+andi0:
+ # 0 and 0 is 0.
+ movi 0, r0
+ andi r0, 0, r2
+ bnei r2, 0, tr0
+
+and1:
+ # 0 and 1 is 0.
+ movi 0, r0
+ andi r0, 1, r2
+ bnei r2, 0, tr0
+
+and2:
+ # 1 and 0 is 0.
+ movi 1, r0
+ andi r0, 0, r2
+ bnei r2, 0, tr0
+
+and3:
+ # 1 and 1 is 1.
+ movi 1, r0
+ andi r0, 1, r2
+ bnei r2, 1, tr0
+
+and4:
+ movi 15, r0
+ andi r0, 3, r2
+ bnei r2, 3, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for beq$likely $rm, $rn, $tra -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global beq
+init:
+ # Load up the branch target registers.
+ pta beq2, tr0
+ pta beq3, tr1
+ pta wrong, tr2
+
+beq1:
+ # Compare r0 with itself.
+ # Always true, so branch likely.
+ movi 1, r0
+ beq/l r0, r0, tr0
+ # We should branch over this.
+ fail
+
+beq2:
+ # Ensure high order bits are compared, too.
+ movi 1, r0
+ shlli r0, 35, r0
+ addi r0, 10, r0
+ movi 1, r1
+ shlli r1, 35, r1
+ addi r1, 10, r1
+ beq r0, r1, tr1
+ # We should branch over this, too.
+ fail
+
+beq3:
+ movi 1, r0
+ shlli r0, 35, r0
+ addi r0, 10, r0
+ movi 2, r1
+ shlli r1, 35, r1
+ addi r1, 9, r1
+ # Unlikely we'll branch!
+ beq/u r0, r1, tr2
+ # We should proceed to pass here.
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for beqi$likely $rm, $imm6, $tra -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global beqi
+init:
+ # Load up the branch target registers.
+ pta beqi2, tr0
+ pta beqi3, tr1
+ pta wrong, tr2
+
+beqi1:
+ # Always true, so branch likely.
+ movi 1, r0
+ beqi/l r0, 1, tr0
+ # We should branch over this.
+ fail
+
+beqi2:
+ movi 22, r3
+ beqi r3, 22, tr1
+ # We should branch over this.
+ fail
+
+beqi3:
+ movi 27, r7
+ # We shouldn't branch here.
+ beqi/u r7, 23, tr2
+ # We should proceed to pass here.
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for bge$likely $rm, $rn, $tra -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global bge
+init:
+ pta bge2, tr0
+ pta bge3, tr1
+ pta wrong, tr2
+ movi 0, r0
+
+bge1:
+ # Compare r0 with itself.
+ bge/l r0, r0, tr0
+ # We should branch here.
+ fail
+
+bge2:
+ movi 1, r1
+ movi 1, r2
+ bge r1, r2, tr1
+ # We should branch here.
+ fail
+
+bge3:
+ movi -1, r1
+ movi 1, r2
+ bge r1, r2, tr2
+ # We should not branch here.
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for bgeu$likely $rm, $rn, $tra -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global bgeu
+init:
+ movi 0, r0
+
+bgeu1:
+ # Compare r0 with itself.
+ pta bgeu2, tr0
+ bgeu/l r0, r0, tr0
+ # We should branch here.
+ fail
+
+bgeu2:
+ movi 1, r1
+ movi 1, r2
+ pta bge3, tr0
+ bgeu r1, r2, tr0
+ # We should branch here.
+ fail
+
+bge3:
+ movi -1, r1
+ movi 1, r2
+ # We SHOULD branch here.
+ pta bge4, tr0
+ bgeu r1, r2, tr0
+ fail
+
+bge4:
+ movi 1, r1
+ movi -1, r2
+ # We should not branch here.
+ pta wrong, tr0
+ bgeu r1, r2, tr0
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for bgt$likely $rm, $rn, $tra -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+
+init:
+ pta wrong, tr0
+
+bgt1:
+ movi 1, r0
+ movi -1, r1
+ bgt r1, r0, tr0
+
+bgt2:
+ bgt r0, r0, tr0
+
+bgt3:
+ pta okay, tr1
+ movi -1, r0
+ movi 1, r1
+ bgt r0, r1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for bgtu$likely $rm, $rn, $tra -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+
+init:
+ pta wrong, tr0
+
+bgtu1:
+ movi 1, r0
+ movi -1, r1
+ pta bgt2, tr1
+ bgtu r1, r0, tr1
+ fail
+
+bgt2:
+ bgtu r0, r0, tr0
+
+bgt3:
+ pta okay, tr1
+ movi -1, r0
+ movi 1, r1
+ pta okay, tr1
+ bgtu r0, r1, tr1
+ fail
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for blink $trb, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+blink:
+ pta target, tr0
+ gettr tr0, r1
+ ptabs r1, tr0
+ blink tr0, r0
+ fail
+
+target:
+ pass
--- /dev/null
+# sh testcase for bne$likely $rm, $rn, $tra -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ movi 1, r0
+ pta wrong, tr0
+ pta okay, tr1
+
+bne1:
+ bne r63, r63, tr0
+bne2:
+ bne r0, r63, tr1
+bad:
+ fail
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for bnei$likely $rm, $imm6, $tra -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ movi 1, r0
+ pta wrong, tr0
+ pta okay, tr1
+
+bnei1:
+ bnei r63, 0, tr0
+bnei2:
+ bnei r0, 3, tr1
+bad:
+ fail
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for brk -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ # brk will cause the sim to trap, so avoid it.
+ pass
+ brk
--- /dev/null
+# sh testcase for byterev $rm, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ pta wrong, tr0
+init:
+ # Put a distinctive pattern in r0.
+ movi 10, r0
+ shlli r0, 8, r0
+ ori r0, 20, r0
+ shlli r0, 8, r0
+ ori r0, 30, r0
+ shlli r0, 8, r0
+ ori r0, 40, r0
+ shlli r0, 8, r0
+ ori r0, 50, r0
+ shlli r0, 8, r0
+ ori r0, 60, r0
+ shlli r0, 8, r0
+ ori r0, 70, r0
+ shlli r0, 8, r0
+ ori r0, 80, r0
+
+byterev:
+ byterev r0, r1
+
+check:
+ andi r1, 255, r2
+ movi 10, r3
+ bne r2, r3, tr0
+ shlri r1, 8, r1
+ andi r1, 255, r2
+ movi 20, r3
+ bne r2, r3, tr0
+ shlri r1, 8, r1
+ andi r1, 255, r2
+ movi 30, r3
+ bne r2, r3, tr0
+ shlri r1, 8, r1
+ andi r1, 255, r2
+ movi 40, r3
+ bne r2, r3, tr0
+ shlri r1, 8, r1
+ andi r1, 255, r2
+ movi 50, r3
+ bne r2, r3, tr0
+ shlri r1, 8, r1
+ andi r1, 255, r2
+ movi 60, r3
+ bne r2, r3, tr0
+ shlri r1, 8, r1
+ andi r1, 255, r2
+ movi 70, r3
+ bne r2, r3, tr0
+ shlri r1, 8, r1
+ andi r1, 255, r2
+ movi 80, r3
+ bne r2, r3, tr0
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for cmpeq $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+ movi 0, r0
+ movi 1, r1
+ movi 2, r2
+ movi 2, r3
+ movi 3, r4
+
+cmpeq1:
+ cmpeq r2, r2, r7
+ bne r7, r1, tr0
+
+cmpeq2:
+ cmpeq r2, r3, r7
+ bne r7, r1, tr0
+
+cmpeq3:
+ cmpeq r2, r4, r7
+ bne r7, r0, tr0
+
+cmpeq4:
+ movi 1, r2
+ shlli r2, 63, r2
+ movi 1, r3
+ shlli r3, 63, r3
+ cmpeq r2, r3, r7
+ bne r7, r1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for cmpgt $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+ movi 0, r0
+ movi 1, r1
+ movi 2, r2
+ movi 2, r3
+ movi 3, r4
+
+cmpgt1:
+ cmpgt r2, r2, r7
+ bne r7, r0, tr0
+
+cmpgt2:
+ cmpgt r2, r3, r7
+ bne r7, r0, tr0
+
+cmpgt3:
+ cmpgt r4, r2, r7
+ bne r7, r1, tr0
+
+cmpgt4:
+ movi 1, r2
+ shlli r2, 63, r2
+ movi 1, r3
+ shlli r3, 63, r3
+ addi r3, 1, r3
+ cmpgt r3, r2, r7
+ bne r7, r1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for cmpgtu $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+ movi 0, r0
+ movi 1, r1
+ movi 2, r2
+ movi 2, r3
+ movi 3, r4
+
+cmpgt1:
+ cmpgtu r2, r2, r7
+ bne r7, r0, tr0
+
+cmpgt2:
+ cmpgtu r2, r3, r7
+ bne r7, r0, tr0
+
+cmpgt3:
+ cmpgtu r4, r2, r7
+ bne r7, r1, tr0
+
+cmpgt4:
+ movi 1, r2
+ shlli r2, 63, r2
+ movi 1, r3
+ shlli r3, 63, r3
+ addi r3, 1, r3
+ cmpgtu r3, r2, r7
+ bne r7, r1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for cmveq $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+ movi 0, r0
+ movi 1, r1
+ movi 2, r2
+ movi 21, r3
+
+cmveq:
+ # Zap r7.
+ movi 0, r7
+
+ cmveq r0, r2, r7
+ bne r2, r7, tr0
+
+ cmveq r1, r3, r7
+ # Make sure r7 is still equal to r2.
+ bne r2, r7, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for cmvne $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+ movi 0, r0
+ movi 1, r1
+ movi 2, r2
+ movi 21, r3
+
+cmvne:
+ # Zap r7.
+ movi 0, r7
+
+ cmvne r1, r2, r7
+ bne r2, r7, tr0
+
+ cmvne r0, r3, r7
+ # Make sure r7 is still equal to r2.
+ bne r2, r7, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fabs.d $drgh, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+ movi 0, r0
+ movi 1, r1
+
+fabs0:
+ # Ensure fabs(-1) = 1.
+ fmov.ls r0, fr7
+ float.ld fr7, dr0
+ fmov.ls r1, fr7
+ float.ld fr7, dr2
+ fsub.d dr0, dr2, dr4
+ fabs.d dr4, dr6
+ fcmpeq.d dr6, dr2, r7
+ bnei r7, 1, tr0
+
+fabs1:
+ # Ensure fabs(1) = 1.
+ fmov.ls r0, fr7
+ float.ld fr7, dr0
+ fmov.ls r1, fr7
+ float.ld fr7, dr2
+ fabs.d dr2, dr4
+ fcmpeq.d dr2, dr4, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fabs.s $frgh, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+ movi 0, r0
+ movi 1, r1
+
+fabs0:
+ # Ensure fabs(-1) = 1.
+ fmov.ls r0, fr7
+ float.ls fr7, fr0
+ fmov.ls r1, fr7
+ float.ls fr7, fr1
+ fsub.s fr0, fr1, fr2
+ fabs.s fr2, fr3
+ fcmpeq.s fr3, fr1, r7
+ bnei r7, 1, tr0
+
+fabs1:
+ # Ensure fabs(1) = 1.
+ fmov.ls r0, fr7
+ float.ls fr7, fr0
+ fmov.ls r1, fr7
+ float.ls fr7, fr1
+ fabs.s fr1, fr2
+ fcmpeq.s fr1, fr2, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fadd.d $drg, $drh, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+ movi 2, r0
+ movi 3, r1
+
+fadd0:
+ # Add 2 and 3.
+ fmov.ls r0, fr7
+ float.ld fr7, dr0
+ fmov.ls r1, fr7
+ float.ld fr7, dr2
+ fadd.d dr0, dr2, dr4
+ # Check to make sure we got 5.
+ movi 5, r2
+ fmov.ls r2, fr7
+ float.ld fr7, dr6
+ fcmpeq.d dr4, dr6, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fadd.s $frg, $frh, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global fadds
+init:
+ pta wrong, tr0
+ movi 2, r0
+ movi 3, r1
+
+fadd0:
+ # Add 2 and 3.
+ fmov.ls r0, fr7
+ float.ls fr7, fr0
+ fmov.ls r1, fr7
+ float.ls fr7, fr1
+ fadd.s fr0, fr1, fr2
+ # Check to make sure we got 5.
+ movi 5, r2
+ fmov.ls r2, fr7
+ float.ls fr7, fr3
+ fcmpeq.s fr2, fr3, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fcmpeq.d $drg, $drh, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+fcmpeq1:
+ movi 1, r0
+ fmov.ls r0, fr0
+ fmov.ls r0, fr1
+ float.ld fr0, dr2
+ float.ld fr1, dr4
+ fcmpeq.d dr2, dr2, r7
+ bnei r7, 1, tr0
+
+fcmpeq2:
+ movi 1, r0
+ fmov.ls r0, fr0
+ movi 2, r1
+ fmov.ls r1, fr1
+ float.ld fr0, dr4
+ float.ld fr1, dr6
+ fcmpeq.d dr4, dr6, r7
+ bnei r7, 0, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fcmpeq.s $frg, $frh, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+fcmpeq1:
+ movi 1, r0
+ fmov.ls r0, fr0
+ fmov.ls r0, fr1
+ float.ls fr0, fr2
+ float.ls fr1, fr3
+ fcmpeq.s fr2, fr3, r7
+ bnei r7, 1, tr0
+
+fcmpeq2:
+ movi 1, r0
+ fmov.ls r0, fr0
+ movi 2, r1
+ fmov.ls r1, fr1
+ float.ls fr0, fr2
+ float.ls fr1, fr3
+ fcmpeq.s fr2, fr3, r7
+ bnei r7, 0, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fcmpge.d $drg, $drh, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+fcmpge1: # 2 = 2.
+ movi 2, r0
+ fmov.ls r0, fr0
+ fmov.ls r0, fr1
+ float.ld fr0, dr2
+ float.ld fr1, dr4
+ fcmpge.d dr2, dr4, r7
+ bnei r7, 1, tr0
+
+fcmpge2: # 4 > 2.
+ movi 4, r0
+ fmov.ls r0, fr0
+ movi 2, r0
+ fmov.ls r0, fr1
+ float.ld fr0, dr2
+ float.ld fr1, dr4
+ fcmpge.d dr2, dr4, r7
+ bnei r7, 1, tr0
+
+fcmpge3: # 2 < 4.
+ movi 2, r0
+ fmov.ls r0, fr0
+ movi 4, r0
+ fmov.ls r0, fr1
+ float.ld fr0, dr2
+ float.ld fr1, dr4
+ fcmpge.d dr2, dr4, r7
+ bnei r7, 0, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fcmpge.s $frg, $frh, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+fcmpge1: # 2 = 2.
+ movi 2, r0
+ fmov.ls r0, fr0
+ fmov.ls r0, fr1
+ float.ls fr0, fr2
+ float.ls fr1, fr3
+ fcmpge.s fr2, fr3, r7
+ bnei r7, 1, tr0
+
+fcmpge2: # 3 > 2.
+ movi 3, r0
+ fmov.ls r0, fr0
+ movi 2, r0
+ fmov.ls r0, fr1
+ float.ls fr0, fr2
+ float.ls fr1, fr3
+ fcmpge.s fr2, fr3, r7
+ bnei r7, 1, tr0
+
+fcmpge3: # 2 < 3.
+ movi 2, r0
+ fmov.ls r0, fr0
+ movi 3, r0
+ fmov.ls r0, fr1
+ float.ls fr0, fr2
+ float.ls fr1, fr3
+ fcmpge.s fr2, fr3, r7
+ bnei r7, 0, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fcmpgt.d $drg, $drh, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+fcmpgt1:
+ movi 2, r0
+ fmov.qd r0, dr0
+ movi 1, r1
+ fmov.qd r1, dr2
+ float.qd dr0, dr4
+ float.qd dr2, dr6
+ fcmpgt.d dr4, dr6, r7
+ bnei r7, 1, tr0
+
+fcmpgt2:
+ movi 1, r0
+ fmov.qd r0, dr0
+ fmov.qd r0, dr2
+ float.qd dr0, dr4
+ float.qd dr2, dr6
+ fcmpgt.d dr4, dr6, r7
+ bnei r7, 0, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fcmpgt.s $frg, $frh, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+fcmpgt1:
+ movi 2, r0
+ fmov.ls r0, fr0
+ movi 1, r1
+ fmov.ls r1, fr1
+ float.ls fr0, fr2
+ float.ls fr1, fr3
+ fcmpgt.s fr2, fr3, r7
+ bnei r7, 1, tr0
+
+fcmpgt2:
+ movi 1, r0
+ fmov.ls r0, fr0
+ fmov.ls r0, fr1
+ float.ls fr0, fr2
+ float.ls fr1, fr3
+ fcmpgt.s fr2, fr3, r7
+ bnei r7, 0, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fcmpun.d $drg, $drh, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+fcmpund:
+ movi 0, r0
+ movi 1, r1
+ fmov.qd r0, dr0
+ float.qd dr0, dr0
+ fmov.qd r1, dr2
+ float.qd dr2, dr2
+ fcmpun.d dr0, dr2, r7
+ bnei r7, 0, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fcmpun.s $frg, $frh, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+fcmpuns:
+ movi 0, r0
+ movi 1, r1
+ fmov.ls r0, fr0
+ float.ls fr0, fr0
+ fmov.ls r1, fr1
+ float.ls fr1, fr1
+ fcmpun.s fr0, fr1, r7
+ bnei r7, 0, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fcnv.ds $drgh, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+fcnvds:
+ movi 9, r0
+ fmov.qd r0, dr0
+ float.qd dr0, dr0
+ fcnv.ds dr0, fr3
+ movi 9, r0
+ fmov.ls r0, fr4
+ float.ls fr4, fr4
+ fcmpeq.s fr3, fr4, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fcnv.sd $frgh, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+fcnvsd:
+ movi 9, r0
+ fmov.ls r0, fr0
+ float.ls fr0, fr0
+ fcnv.sd fr0, dr2
+ movi 9, r0
+ fmov.qd r0, dr4
+ float.qd dr4, dr4
+ fcmpeq.d dr2, dr4, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fdiv.d $drg, $drh, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+fdivd1:
+ movi 1, r0
+ fmov.qd r0, dr0
+ float.qd dr0, dr0
+ movi 2, r1
+ fmov.qd r1, dr2
+ float.qd dr2, dr2
+ fdiv.d dr0, dr2, dr4
+
+fdvid2:
+ movi 6, r0
+ fmov.qd r0, dr0
+ float.qd dr0, dr0
+ movi 2, r1
+ fmov.qd r1, dr2
+ float.qd dr2, dr2
+ fdiv.d dr0, dr2, dr4
+ movi 3, r3
+ fmov.qd r3, dr6
+ float.qd dr6, dr6
+ fcmpeq.d dr4, dr6, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fdiv.s $frg, $frh, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+fdivs1:
+ movi 1, r0
+ fmov.ls r0, fr0
+ float.ls fr0, fr0
+ movi 2, r1
+ fmov.ls r1, fr1
+ float.ls fr1, fr1
+ fdiv.s fr0, fr1, fr2
+
+fdvis2:
+ movi 6, r0
+ fmov.ls r0, fr0
+ float.ls fr0, fr0
+ movi 2, r1
+ fmov.ls r1, fr1
+ float.ls fr1, fr1
+ fdiv.s fr0, fr1, fr2
+ movi 3, r3
+ fmov.ls r3, fr3
+ float.ls fr3, fr3
+ fcmpeq.s fr2, fr3, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fgetscr $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global fgetscr
+fgetscr:
+ fgetscr fr0
+
+ pass
--- /dev/null
+# sh testcase for fipr.s $fvg, $fvh, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ .macro _load val, fpreg
+ # This macro clobbers r0.
+ movi \val, r0
+ fmov.ls r0, \fpreg
+ float.ls \fpreg, \fpreg
+ .endm
+
+ start
+
+ .global fiprs
+init:
+ pta wrong, tr0
+
+ _load 1, fr0
+ _load 2, fr1
+ _load 3, fr2
+ _load 4, fr3
+ _load 1, fr4
+ _load 2, fr5
+ _load 3, fr6
+ _load 4, fr7
+
+fiprs:
+ fipr.s fv0, fv4, fr9
+
+check:
+ _load 30, fr10
+ fcmpeq.s fr9, fr10, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fld.d $rm, $disp10x8, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ movi 0x2800, r0
+ fld.d r0, 0, dr0
+ fld.d r0, 8, dr0
+ fld.d r0, -8, dr0
+ pass
--- /dev/null
+# sh testcase for fld.p $rm, $disp10x8, $fpf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ movi 0x2800, r0
+
+fldp:
+ fld.p r0, 0, fp0
+ fld.p r0, 8, fp2
+ fld.p r0, -8, fp4
+ pass
--- /dev/null
+# sh testcase for fld.s $rm, $disp10x4, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ movi 0x2800, r0
+ fld.s r0, 0, fr0
+ fld.s r0, 4, fr0
+ fld.s r0, -4, fr0
+ pass
--- /dev/null
+# sh testcase for fldx.d $rm, $rn, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ movi 0x2800, r0
+ movi 0, r1
+ fldx.d r0, r1, dr0
+ movi 8, r1
+ fldx.d r0, r1, dr0
+ movi -8, r1
+ fldx.d r0, r1, dr0
+ pass
--- /dev/null
+# sh testcase for fldx.p $rm, $rn, $fpf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ movi 0x2800, r0
+
+fldxp:
+ movi 0, r1
+ fldx.p r0, r1, fp0
+
+ movi 8, r1
+ fldx.p r0, r1, fp2
+
+ movi -8, r1
+ fldx.p r0, r1, fp4
+
+ pass
--- /dev/null
+# sh testcase for fldx.s $rm, $rn, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ movi 0x2800, r0
+ movi 0, r1
+ fldx.s r0, r1, fr0
+ movi 4, r1
+ fldx.s r0, r1, fr0
+ movi -4, r1
+ fldx.s r0, r1, fr0
+ pass
--- /dev/null
+# sh testcase for float.ld $frgh, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ movi 1, r0
+ fmov.ls r0, fr0
+ float.ld fr0, dr0
+ pass
--- /dev/null
+# sh testcase for float.ls $frgh, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ movi 1, r0
+ fmov.ls r0, fr0
+ float.ls fr0, fr0
+ pass
--- /dev/null
+# sh testcase for float.qd $drgh, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ movi 1, r0
+ fmov.qd r0, dr0
+ float.qd dr0, dr2
+ pass
--- /dev/null
+# sh testcase for float.qs $drgh, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ movi 1, r0
+ fmov.qd r0, dr0
+ float.qs dr0, fr1
+ pass
--- /dev/null
+# sh testcase for fmac.s $frg, $frh, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+fmacs:
+ movi 2, r0
+ fmov.ls r0, fr0
+ float.ls fr0, fr0
+
+ movi 3, r1
+ fmov.ls r1, fr1
+ float.ls fr1, fr1
+
+ movi 4, r2
+ fmov.ls r2, fr2
+ float.ls fr2, fr2
+
+ fmac.s fr0, fr1, fr2
+
+ movi 10, r3
+ fmov.ls r3, fr3
+ float.ls fr3, fr3
+
+ fcmpeq.s fr2, fr3, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fmov.d $drgh, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+fmovd:
+ movi 4, r0
+ fmov.qd r0, dr0
+ float.qd dr0, dr2
+ fmov.d dr2, dr4
+ fcmpeq.d dr2, dr4, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fmov.dq $drgh, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+fmovdq:
+ movi 4, r0
+ fmov.qd r0, dr0
+ fmov.dq dr0, r1
+ bne r0, r1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fmov.ls $rm, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+fmovls0:
+ movi 0, r0
+ fmov.ls r0, fr0
+
+fmovls1:
+ movi 1, r1
+ fmov.ls r1, fr1
+
+upper:
+ movi 1, r2
+ shlli r2, 63, r2
+ ori r2, 3, r2
+ # Bit 63 should be ignored.
+ fmov.ls r2, fr2
+
+okay:
+ pass
--- /dev/null
+# sh testcase for fmov.qd $rm, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+fmovdq:
+ movi 4, r0
+ fmov.qd r0, dr0
+ fmov.dq dr0, r1
+ bne r0, r1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fmov.s $frgh, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+fmovs:
+ movi 8, r0
+ fmov.ls r0, fr7
+ float.ls fr7, fr0
+ fmov.s fr0, fr1
+ fcmpeq.s fr0, fr1, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fmov.sl $frgh, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+fmovsl:
+ pta wrong, tr0
+ movi 9, r0
+ fmov.ls r0, fr0
+ fmov.sl fr0, r1
+ bne r0, r1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fmul.d $drg, $drh, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+fmuld1:
+ movi 2, r0
+ fmov.qd r0, dr0
+ float.qd dr0, dr0
+ movi 3, r1
+ fmov.qd r1, dr2
+ float.qd dr2, dr2
+ fmul.d dr0, dr2, dr4
+ movi 6, r2
+ fmov.qd r2, dr6
+ float.qd dr6, dr6
+ fcmpeq.d dr4, dr6, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fmul.s $frg, $frh, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+fmuls1:
+ movi 2, r0
+ fmov.ls r0, fr0
+ float.ls fr0, fr0
+ movi 3, r1
+ fmov.ls r1, fr1
+ float.ls fr1, fr1
+ fmul.s fr0, fr1, fr2
+ movi 6, r2
+ fmov.ls r2, fr3
+ float.ls fr3, fr3
+ fcmpeq.s fr2, fr3, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fneg.d $drgh, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+ movi 0, r0
+ movi 1, r1
+
+fnegd0:
+ # Ensure fnegd(0) = 0.
+ fmov.ls r0, fr7
+ float.ld fr7, dr0
+ fneg.d dr0, dr2
+ fcmpeq.d dr0, dr2, r7
+ bnei r7, 1, tr0
+
+fnegd1:
+ # Ensure fnegd(fnegd(1)) = 1.
+ fmov.ls r1, fr7
+ float.ld fr7, dr0
+ fneg.d dr0, dr2
+ fneg.d dr2, dr4
+ fcmpeq.d dr0, dr4, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fneg.s $frgh, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+ movi 0, r0
+ movi 1, r1
+
+fnegs0:
+ # Ensure fnegs(0) = 0.
+ fmov.ls r0, fr7
+ float.ls fr7, fr0
+ fneg.s fr0, fr1
+ fcmpeq.s fr0, fr1, r7
+ bnei r7, 1, tr0
+
+fnegs1:
+ # Ensure fnegs(fnegs(1)) = 1.
+ fmov.ls r1, fr7
+ float.ls fr7, fr0
+ fneg.s fr0, fr1
+ fneg.s fr1, fr2
+ fcmpeq.s fr0, fr2, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fputscr $frgh -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global fputscr
+fputscr:
+ fputscr fr0
+
+ pass
--- /dev/null
+# sh testcase for fsqrt.d $frgh, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+ movi 9, r0
+ fmov.ls r0, fr7
+ float.ld fr7, dr0
+ movi 3, r1
+ fmov.ls r1, fr7
+ float.ld fr7, dr2
+
+fsqrtd:
+ fsqrt.d dr0, dr4
+ fcmpeq.d dr2, dr4, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fsqrt.s $frgh, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+ movi 9, r0
+ fmov.ls r0, fr7
+ float.ls fr7, fr0
+ movi 3, r1
+ fmov.ls r1, fr7
+ float.ls fr7, fr2
+
+fsqrts:
+ fsqrt.s fr0, fr1
+ fcmpeq.s fr1, fr2, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fst.d $rm, $disp10x8, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global fstd
+fstd:
+ movi 0x1020, r0
+ shlli r0, 8, r0
+ ori r0, 0x30, r0
+ shlli r0, 8, r0
+ ori r0, 0x40, r0
+ shlli r0, 8, r0
+ ori r0, 0x50, r0
+ shlli r0, 8, r0
+ ori r0, 0x60, r0
+ shlli r0, 8, r0
+ ori r0, 0x70, r0
+ shlli r0, 8, r0
+ ori r0, 0x80, r0
+ # Set target address.
+ movi 0x2800, r1
+ fmov.qd r0, dr0
+
+ fst.d r1, 0, dr0
+ fst.d r1, 8, dr0
+ fst.d r1, -8, dr0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for fst.p $rm, $disp10x8, $fpf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global fstp
+fstp:
+ fst.p r0, 0, fp0
+
+ pass
--- /dev/null
+# sh testcase for fst.s $rm, $disp10x4, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global fsts
+fsts:
+ movi 0x1020, r0
+ shlli r0, 8, r0
+ ori r0, 0x30, r0
+ shlli r0, 8, r0
+ ori r0, 0x40, r0
+ shlli r0, 8, r0
+ ori r0, 0x50, r0
+ shlli r0, 8, r0
+ ori r0, 0x60, r0
+ shlli r0, 8, r0
+ ori r0, 0x70, r0
+ shlli r0, 8, r0
+ ori r0, 0x80, r0
+ # Set target address.
+ movi 0x2800, r1
+ fmov.ls r0, fr0
+
+ fst.s r1, 0, fr0
+ fst.s r1, 4, fr0
+ fst.s r1, -4, fr0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for fstx.d $rm, $rn, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global fstxd
+fstxd:
+ movi 0x1020, r0
+ shlli r0, 8, r0
+ ori r0, 0x30, r0
+ shlli r0, 8, r0
+ ori r0, 0x40, r0
+ shlli r0, 8, r0
+ ori r0, 0x50, r0
+ shlli r0, 8, r0
+ ori r0, 0x60, r0
+ shlli r0, 8, r0
+ ori r0, 0x70, r0
+ shlli r0, 8, r0
+ ori r0, 0x80, r0
+ fmov.qd r0, dr0
+ movi 0x2800, r1
+ movi -8, r2
+ fstx.d r1, r2, dr0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for fstx.p $rm, $rn, $fpf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global fstxp
+fstxp:
+ fstx.p r0, r0, fp0
+
+ pass
--- /dev/null
+# sh testcase for fstx.s $rm, $rn, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ .global fstxs
+fstxs:
+ movi 0x1020, r0
+ shlli r0, 8, r0
+ ori r0, 0x30, r0
+ shlli r0, 8, r0
+ ori r0, 0x40, r0
+ shlli r0, 8, r0
+ ori r0, 0x50, r0
+ shlli r0, 8, r0
+ ori r0, 0x60, r0
+ shlli r0, 8, r0
+ ori r0, 0x70, r0
+ shlli r0, 8, r0
+ ori r0, 0x80, r0
+ fmov.ls r0, fr0
+ movi 0x2800, r1
+ movi -8, r2
+ fstx.s r1, r2, fr0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for fsub.d $drg, $drh, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global fsubd
+init:
+ pta wrong, tr0
+
+fsubd:
+ movi 9, r0
+ fmov.qd r0, dr0
+ float.qd dr0, dr0
+
+ movi 3, r0
+ fmov.qd r0, dr2
+ float.qd dr2, dr2
+
+ fsub.d dr0, dr2, dr4
+
+ movi 6, r0
+ fmov.qd r0, dr6
+ float.qd dr6, dr6
+
+ fcmpeq.d dr4, dr6, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for fsub.s $frg, $frh, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global fsubs
+init:
+ pta wrong, tr0
+
+fsubs:
+ movi 9, r0
+ fmov.ls r0, fr0
+ float.ls fr0, fr0
+
+ movi 3, r0
+ fmov.ls r0, fr1
+ float.ls fr1, fr1
+
+ fsub.s fr0, fr1, fr2
+
+ movi 6, r0
+ fmov.ls r0, fr3
+ float.ls fr3, fr3
+
+ fcmpeq.s fr2, fr3, r7
+ bnei r7, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for ftrc.dl $drgh, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global ftrcdl
+init:
+ pta wrong, tr0
+
+ftrcdl:
+ movi -9, r0
+ fmov.qd r0, dr0
+ float.qd dr0, dr0
+ ftrc.dl dr0, fr0
+ fmov.sl fr0, r1
+ bne r0, r1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for ftrc.dq $drgh, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+ftrcdq:
+ movi -9, r0
+ fmov.qd r0, dr0
+ float.qd dr0, dr0
+ ftrc.dq dr0, dr2
+ fmov.dq dr2, r1
+ bne r0, r1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for ftrc.sl $frgh, $frf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global ftrcsl
+init:
+ pta wrong, tr0
+
+ftrcsl:
+ movi -9, r0
+ fmov.ls r0, fr0
+ float.ls fr0, fr0
+ ftrc.sl fr0, fr1
+ fmov.sl fr1, r1
+ bne r0, r1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for ftrc.sq $frgh, $drf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+ftrcsq:
+ movi -9, r0
+ fmov.ls r0, fr0
+ float.ls fr0, fr0
+ ftrc.sq fr0, dr2
+ fmov.dq dr2, r1
+ bne r0, r1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for ftrv.s $mtrxg, $fvh, $fvf -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ .macro _load val, fpreg
+ # This macro clobbers r0.
+ movi \val, r0
+ fmov.ls r0, \fpreg
+ float.ls \fpreg, \fpreg
+ .endm
+
+ start
+
+init:
+ pta wrong, tr0
+
+ _load 1, fr0
+ _load 2, fr4
+ _load 3, fr8
+ _load 4, fr12
+ _load 5, fr1
+ _load 6, fr5
+ _load 7, fr9
+ _load 8, fr13
+ _load 9, fr2
+ _load 10, fr6
+ _load 11, fr10
+ _load 12, fr14
+ _load 13, fr3
+ _load 14, fr7
+ _load 15, fr11
+ _load 16, fr15
+
+ _load 1, fr16
+ _load 2, fr17
+ _load 3, fr18
+ _load 4, fr19
+
+ftrvs:
+ ftrv.s mtrx0, fv16, fv20
+
+check:
+ _load 30, fr0
+ _load 70, fr1
+ _load 110, fr2
+ _load 150, fr3
+
+ fcmpeq.s fr0, fr20, r0
+ bnei r0, 1, tr0
+
+ fcmpeq.s fr1, fr21, r0
+ bnei r0, 1, tr0
+
+ fcmpeq.s fr2, fr22, r0
+ bnei r0, 1, tr0
+
+ fcmpeq.s fr3, fr23, r0
+ bnei r0, 1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for getcfg $rm, $disp6, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ getcfg r0, 0, r0
+ pass
--- /dev/null
+# sh testcase for getcon $crk, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+getcon1:
+ movi 22, r0
+ putcon r0, cr0
+ getcon cr0, r1
+ bne r0, r1, tr0
+
+getcon2:
+ movi 12, r0
+ shlli r0, 35, r0
+ putcon r0, cr20
+ getcon cr20, r20
+ bne r0, r20, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for gettr $trb, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ # tr0 is reserved.
+ # don't use it anywhere else in this test.
+ pta wrong, tr0
+
+gettr1:
+ # Put garbage in r1, r2.
+ movi 20, r1
+ movi 30, r2
+
+ pta foo, tr1
+ pta foo, tr2
+
+check1:
+ gettr tr1, r1
+ gettr tr2, r2
+ bne r1, r2, tr0
+
+gettr2:
+ # Put garbage in r3, r4.
+ movi 21, r3
+ movi 42, r4
+
+check2:
+ pta foo, tr1
+ gettr tr1, r2
+ ptabs r2, tr2
+ gettr tr2, r3
+ ptabs r3, tr3
+ gettr tr3, r4
+ bne r2, r4, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
+
+foo:
+ nop
--- /dev/null
+# sh testcase for icbi $rm, $disp6x32 -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ icbi r0, 0
+ pass
--- /dev/null
+# sh testcase for ld.b $rm, $disp10, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ movi 20, r3
+ shlli r3, 8, r3
+
+ldb1:
+ ld.b r3, 0, r0
+ldb2:
+ ld.b r3, -1, r0
+ldb3:
+ ld.b r3, 1, r0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for ldhi.l $rm, $disp6, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global ldhil
+ldhil:
+ ldhi.l r0, 0, r0
+
+ pass
--- /dev/null
+# sh testcase for ldhi.q $rm, $disp6, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global ldhiq
+ldhiq:
+ ldhi.q r0, 0, r0
+
+ pass
--- /dev/null
+# sh testcase for ld.l $rm, $disp10x4, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ movi 20, r3
+ shlli r3, 8, r3
+
+ldl1:
+ ld.l r3, 0, r0
+ldl2:
+ ld.l r3, -4, r0
+ldl3:
+ ld.l r3, 4, r0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for ldlo.l $rm, $disp6, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global ldlol
+ldlol:
+ ldlo.l r0, 0, r0
+
+ pass
--- /dev/null
+# sh testcase for ldlo.q $rm, $disp6, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global ldloq
+ldloq:
+ ldlo.q r0, 0, r0
+
+ pass
--- /dev/null
+# sh testcase for ld.q $rm, $disp10x8, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ movi 20, r3
+ shlli r3, 8, r3
+
+ldl1:
+ ld.q r3, 0, r0
+ldl2:
+ ld.q r3, -8, r0
+ldl3:
+ ld.q r3, 8, r0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for ld.ub $rm, $disp10, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ movi 20, r3
+ shlli r3, 8, r3
+
+ldub1:
+ ld.ub r3, 0, r0
+ldub2:
+ ld.ub r3, -1, r0
+ldub3:
+ ld.ub r3, 1, r0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for ld.uw $rm, $disp10, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ movi 20, r3
+ shlli r3, 8, r3
+
+lduw1:
+ ld.uw r3, 0, r0
+lduw2:
+ ld.uw r3, -2, r0
+lduw3:
+ ld.uw r3, 2, r0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for ld.w $rm, $disp10, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ movi 20, r3
+ shlli r3, 8, r3
+
+ldw1:
+ ld.w r3, 0, r0
+ldw2:
+ ld.w r3, -2, r0
+ldw3:
+ ld.w r3, 2, r0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for ldx.b $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ldxb1:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi 0, r4
+ ldx.b r3, r4, r0
+
+ldxb2:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi 1, r4
+ ldx.b r3, r4, r0
+
+ldxb3:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi -1, r4
+ ldx.b r3, r4, r0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for ldx.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ldxl1:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi 0, r4
+ ldx.l r3, r4, r0
+
+ldxl2:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi 4, r4
+ ldx.l r3, r4, r0
+
+ldxl3:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi -4, r4
+ ldx.l r3, r4, r0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for ldx.q $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ldxq1:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi 0, r4
+ ldx.q r3, r4, r0
+
+ldxq2:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi 8, r4
+ ldx.q r3, r4, r0
+
+ldxq3:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi -8, r4
+ ldx.q r3, r4, r0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for ldx.ub $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ldxub1:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi 0, r4
+ ldx.ub r3, r4, r0
+
+ldxub2:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi 1, r4
+ ldx.ub r3, r4, r0
+
+ldxub3:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi -1, r4
+ ldx.ub r3, r4, r0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for ldx.uw $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ldxuw1:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi 0, r4
+ ldx.uw r3, r4, r0
+
+ldxuw2:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi 2, r4
+ ldx.uw r3, r4, r0
+
+ldxuw3:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi -2, r4
+ ldx.uw r3, r4, r0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for ldx.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ldxw1:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi 0, r4
+ ldx.w r3, r4, r0
+
+ldxw2:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi 2, r4
+ ldx.w r3, r4, r0
+
+ldxw3:
+ movi 20, r3
+ shlli r3, 8, r3
+ movi -2, r4
+ ldx.w r3, r4, r0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for mabs.l $rm, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mabsl
+init:
+ pta wrong, tr0
+
+mabsl1:
+ # Pack { 1 3 } into R0.
+ _packl 1, 3, r0
+
+ mabs.l r0, r1
+
+ # Test for { 1 3 } in R0.
+ _packl 1, 3, r2
+ bne r0, r2, tr0
+
+mabsl2:
+ # Pack { -1, -1 } into R0.
+ _packl 1, 1, r0
+
+ # Set the left sign bit.
+ movi 1, r1
+ shlli r1, 63, r1
+ or r0, r1, r0
+
+ mabs.l r0, r2
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mabs.w $rm, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+mabsw1:
+ # Pack { 1 3 5 7 } into R0.
+ _packw 1, 3, 5, 7, r0
+
+ mabs.l r0, r1
+
+ # Test for { 1 3 5 7 } in R0.
+ _packw 1, 3, 5, 7, r2
+ bne r0, r2, tr0
+
+mabsw2:
+ # Pack { -1, -1, -1, -1 } into R0.
+ _packw 1, 1, 1, 1, r0
+
+ # Set the left sign bit
+ movi 1, r1
+ shlli r1, 63, r1
+ or r0, r1, r0
+
+ mabs.w r0, r2
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for madd.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+maddl:
+ # Load { 1 2 } into r0.
+ _packl 1, 2, r0
+ # Load { 3 4 } into r1.
+ _packl 3, 4, r1
+
+ # Add slices to produce { 4 6 }.
+ madd.l r0, r1, r2
+
+ _packl 4, 6, r3
+ bne r2, r3, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for madds.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global maddsl
+maddsl:
+ madds.l r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for madds.ub $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global maddsub
+maddsub:
+ madds.ub r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for madds.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global maddsw
+maddsw:
+ madds.w r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for madd.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+maddw:
+ # Load { 1 2 3 4 } into R0.
+ _packw 1, 2, 3, 4, r0
+
+ # Load { 3 4 5 6 } into R1.
+ _packw 3, 4, 5, 6, r1
+
+ # Add slices to produce { 4 6 8 10 }.
+ madd.w r0, r1, r2
+
+ _packw 4, 6, 8, 10, r3
+ bne r2, r3, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mcmpeq.b $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mcmpeqb
+mcmpeqb:
+ mcmpeq.b r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mcmpeq.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mcmpeql
+mcmpeql:
+ mcmpeq.l r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mcmpeq.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mcmpeqw
+mcmpeqw:
+ mcmpeq.w r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mcmpgt.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mcmpgtl
+mcmpgtl:
+ mcmpgt.l r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mcmpgt.ub $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mcmpgtub
+mcmpgtub:
+ mcmpgt.ub r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mcmpgt.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mcmpgtw
+mcmpgtw:
+ mcmpgt.w r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mcmv $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mcmv
+mcmv:
+ mcmv r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mcnvs.lw $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mcnvslw
+mcnvslw:
+ mcnvs.lw r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mcnvs.wb $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mcnvswb
+mcnvswb:
+ mcnvs.wb r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mcnvs.wub $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mcnvswub
+mcnvswub:
+ mcnvs.wub r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mextr1 $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ # Put a distinguised bit pattern in R0.
+ movi 0x1020, r0
+ shlli r0, 8, r0
+ ori r0, 0x30, r0
+ shlli r0, 8, r0
+ ori r0, 0x40, r0
+ shlli r0, 8, r0
+ ori r0, 0x50, r0
+ shlli r0, 8, r0
+ ori r0, 0x60, r0
+ shlli r0, 8, r0
+ ori r0, 0x70, r0
+ shlli r0, 8, r0
+ ori r0, 0x80, r0
+
+ # Put another distinguished bit pattern in R1.
+ movi 0x1525, r1
+ shlli r1, 8, r1
+ ori r1, 0x35, r1
+ shlli r1, 8, r1
+ ori r1, 0x45, r1
+ shlli r1, 8, r1
+ ori r1, 0x55, r1
+ shlli r1, 8, r1
+ ori r1, 0x65, r1
+ shlli r1, 8, r1
+ ori r1, 0x75, r1
+ shlli r1, 8, r1
+ ori r1, 0x85, r1
+
+mextr1:
+ mextr1 r0, r1, r2
+
+check:
+ # Put the result in R3.
+ movi 0x2535, r3
+ shlli r3, 8, r3
+ ori r3, 0x45, r3
+ shlli r3, 8, r3
+ ori r3, 0x55, r3
+ shlli r3, 8, r3
+ ori r3, 0x65, r3
+ shlli r3, 8, r3
+ ori r3, 0x75, r3
+ shlli r3, 8, r3
+ ori r3, 0x85, r3
+ shlli r3, 8, r3
+ ori r3, 0x10, r3
+
+ pta wrong, tr0
+ bne r2, r3, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mextr2 $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ # Put a distinguised bit pattern in R0.
+ movi 0x1020, r0
+ shlli r0, 8, r0
+ ori r0, 0x30, r0
+ shlli r0, 8, r0
+ ori r0, 0x40, r0
+ shlli r0, 8, r0
+ ori r0, 0x50, r0
+ shlli r0, 8, r0
+ ori r0, 0x60, r0
+ shlli r0, 8, r0
+ ori r0, 0x70, r0
+ shlli r0, 8, r0
+ ori r0, 0x80, r0
+
+ # Put another distinguished bit pattern in R1.
+ movi 0x1525, r1
+ shlli r1, 8, r1
+ ori r1, 0x35, r1
+ shlli r1, 8, r1
+ ori r1, 0x45, r1
+ shlli r1, 8, r1
+ ori r1, 0x55, r1
+ shlli r1, 8, r1
+ ori r1, 0x65, r1
+ shlli r1, 8, r1
+ ori r1, 0x75, r1
+ shlli r1, 8, r1
+ ori r1, 0x85, r1
+
+mextr2:
+ mextr2 r0, r1, r2
+
+check:
+ # Put the result in R3.
+ movi 0x3545, r3
+ shlli r3, 8, r3
+ ori r3, 0x55, r3
+ shlli r3, 8, r3
+ ori r3, 0x65, r3
+ shlli r3, 8, r3
+ ori r3, 0x75, r3
+ shlli r3, 8, r3
+ ori r3, 0x85, r3
+ shlli r3, 8, r3
+ ori r3, 0x10, r3
+ shlli r3, 8, r3
+ ori r3, 0x20, r3
+
+ pta wrong, tr0
+ bne r2, r3, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mextr3 $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ # Put a distinguised bit pattern in R0.
+ movi 0x1020, r0
+ shlli r0, 8, r0
+ ori r0, 0x30, r0
+ shlli r0, 8, r0
+ ori r0, 0x40, r0
+ shlli r0, 8, r0
+ ori r0, 0x50, r0
+ shlli r0, 8, r0
+ ori r0, 0x60, r0
+ shlli r0, 8, r0
+ ori r0, 0x70, r0
+ shlli r0, 8, r0
+ ori r0, 0x80, r0
+
+ # Put another distinguished bit pattern in R1.
+ movi 0x1525, r1
+ shlli r1, 8, r1
+ ori r1, 0x35, r1
+ shlli r1, 8, r1
+ ori r1, 0x45, r1
+ shlli r1, 8, r1
+ ori r1, 0x55, r1
+ shlli r1, 8, r1
+ ori r1, 0x65, r1
+ shlli r1, 8, r1
+ ori r1, 0x75, r1
+ shlli r1, 8, r1
+ ori r1, 0x85, r1
+
+mextr3:
+ mextr3 r0, r1, r2
+
+check:
+ # Put the result in R3.
+ movi 0x4555, r3
+ shlli r3, 8, r3
+ ori r3, 0x65, r3
+ shlli r3, 8, r3
+ ori r3, 0x75, r3
+ shlli r3, 8, r3
+ ori r3, 0x85, r3
+ shlli r3, 8, r3
+ ori r3, 0x10, r3
+ shlli r3, 8, r3
+ ori r3, 0x20, r3
+ shlli r3, 8, r3
+ ori r3, 0x30, r3
+
+ pta wrong, tr0
+ bne r2, r3, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mextr4 $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ # Put a distinguised bit pattern in R0.
+ movi 0x1020, r0
+ shlli r0, 8, r0
+ ori r0, 0x30, r0
+ shlli r0, 8, r0
+ ori r0, 0x40, r0
+ shlli r0, 8, r0
+ ori r0, 0x50, r0
+ shlli r0, 8, r0
+ ori r0, 0x60, r0
+ shlli r0, 8, r0
+ ori r0, 0x70, r0
+ shlli r0, 8, r0
+ ori r0, 0x80, r0
+
+ # Put another distinguished bit pattern in R1.
+ movi 0x1525, r1
+ shlli r1, 8, r1
+ ori r1, 0x35, r1
+ shlli r1, 8, r1
+ ori r1, 0x45, r1
+ shlli r1, 8, r1
+ ori r1, 0x55, r1
+ shlli r1, 8, r1
+ ori r1, 0x65, r1
+ shlli r1, 8, r1
+ ori r1, 0x75, r1
+ shlli r1, 8, r1
+ ori r1, 0x85, r1
+
+mextr4:
+ mextr4 r0, r1, r2
+
+check:
+ # Put the result in R3.
+ movi 0x5565, r3
+ shlli r3, 8, r3
+ ori r3, 0x75, r3
+ shlli r3, 8, r3
+ ori r3, 0x85, r3
+ shlli r3, 8, r3
+ ori r3, 0x10, r3
+ shlli r3, 8, r3
+ ori r3, 0x20, r3
+ shlli r3, 8, r3
+ ori r3, 0x30, r3
+ shlli r3, 8, r3
+ ori r3, 0x40, r3
+
+ pta wrong, tr0
+ bne r2, r3, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mextr5 $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ # Put a distinguised bit pattern in R0.
+ movi 0x1020, r0
+ shlli r0, 8, r0
+ ori r0, 0x30, r0
+ shlli r0, 8, r0
+ ori r0, 0x40, r0
+ shlli r0, 8, r0
+ ori r0, 0x50, r0
+ shlli r0, 8, r0
+ ori r0, 0x60, r0
+ shlli r0, 8, r0
+ ori r0, 0x70, r0
+ shlli r0, 8, r0
+ ori r0, 0x80, r0
+
+ # Put another distinguished bit pattern in R1.
+ movi 0x1525, r1
+ shlli r1, 8, r1
+ ori r1, 0x35, r1
+ shlli r1, 8, r1
+ ori r1, 0x45, r1
+ shlli r1, 8, r1
+ ori r1, 0x55, r1
+ shlli r1, 8, r1
+ ori r1, 0x65, r1
+ shlli r1, 8, r1
+ ori r1, 0x75, r1
+ shlli r1, 8, r1
+ ori r1, 0x85, r1
+
+mextr5:
+ mextr5 r0, r1, r2
+
+check:
+ # Put the result in R3.
+ movi 0x6575, r3
+ shlli r3, 8, r3
+ ori r3, 0x85, r3
+ shlli r3, 8, r3
+ ori r3, 0x10, r3
+ shlli r3, 8, r3
+ ori r3, 0x20, r3
+ shlli r3, 8, r3
+ ori r3, 0x30, r3
+ shlli r3, 8, r3
+ ori r3, 0x40, r3
+ shlli r3, 8, r3
+ ori r3, 0x50, r3
+
+ pta wrong, tr0
+ bne r2, r3, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mextr6 $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ # Put a distinguised bit pattern in R0.
+ movi 0x1020, r0
+ shlli r0, 8, r0
+ ori r0, 0x30, r0
+ shlli r0, 8, r0
+ ori r0, 0x40, r0
+ shlli r0, 8, r0
+ ori r0, 0x50, r0
+ shlli r0, 8, r0
+ ori r0, 0x60, r0
+ shlli r0, 8, r0
+ ori r0, 0x70, r0
+ shlli r0, 8, r0
+ ori r0, 0x80, r0
+
+ # Put another distinguished bit pattern in R1.
+ movi 0x1525, r1
+ shlli r1, 8, r1
+ ori r1, 0x35, r1
+ shlli r1, 8, r1
+ ori r1, 0x45, r1
+ shlli r1, 8, r1
+ ori r1, 0x55, r1
+ shlli r1, 8, r1
+ ori r1, 0x65, r1
+ shlli r1, 8, r1
+ ori r1, 0x75, r1
+ shlli r1, 8, r1
+ ori r1, 0x85, r1
+
+mextr6:
+ mextr6 r0, r1, r2
+
+check:
+ # Put the result in R3.
+ movi 0x7585, r3
+ shlli r3, 8, r3
+ ori r3, 0x10, r3
+ shlli r3, 8, r3
+ ori r3, 0x20, r3
+ shlli r3, 8, r3
+ ori r3, 0x30, r3
+ shlli r3, 8, r3
+ ori r3, 0x40, r3
+ shlli r3, 8, r3
+ ori r3, 0x50, r3
+ shlli r3, 8, r3
+ ori r3, 0x60, r3
+
+ pta wrong, tr0
+ bne r2, r3, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mextr7 $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ # Put a distinguised bit pattern in R0.
+ movi 0x1020, r0
+ shlli r0, 8, r0
+ ori r0, 0x30, r0
+ shlli r0, 8, r0
+ ori r0, 0x40, r0
+ shlli r0, 8, r0
+ ori r0, 0x50, r0
+ shlli r0, 8, r0
+ ori r0, 0x60, r0
+ shlli r0, 8, r0
+ ori r0, 0x70, r0
+ shlli r0, 8, r0
+ ori r0, 0x80, r0
+
+ # Put another distinguished bit pattern in R1.
+ movi 0x1525, r1
+ shlli r1, 8, r1
+ ori r1, 0x35, r1
+ shlli r1, 8, r1
+ ori r1, 0x45, r1
+ shlli r1, 8, r1
+ ori r1, 0x55, r1
+ shlli r1, 8, r1
+ ori r1, 0x65, r1
+ shlli r1, 8, r1
+ ori r1, 0x75, r1
+ shlli r1, 8, r1
+ ori r1, 0x85, r1
+
+mextr7:
+ mextr7 r0, r1, r2
+
+check:
+ # Put the result in R3.
+ movi 0x8510, r3
+ shlli r3, 8, r3
+ ori r3, 0x20, r3
+ shlli r3, 8, r3
+ ori r3, 0x30, r3
+ shlli r3, 8, r3
+ ori r3, 0x40, r3
+ shlli r3, 8, r3
+ ori r3, 0x50, r3
+ shlli r3, 8, r3
+ ori r3, 0x60, r3
+ shlli r3, 8, r3
+ ori r3, 0x70, r3
+
+ pta wrong, tr0
+ bne r2, r3, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for mmacfx.wl $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mmacfxwl
+mmacfxwl:
+ mmacfx.wl r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mmacnfx.wl $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mmacnfx_wl
+mmacnfx_wl:
+ mmacnfx.wl r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mmulfx.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mmulfxl
+mmulfxl:
+ mmulfx.l r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mmulfxrp.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mmulfxrpw
+mmulfxrpw:
+ mmulfxrp.w r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mmulfx.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mmulfxw
+mmulfxw:
+ mmulfx.w r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mmulhi.wl $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mmulhiwl
+mmulhiwl:
+ mmulhi.wl r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mmul.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mmull
+mmull:
+ mmul.l r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mmullo.wl $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mmullowl
+mmullowl:
+ mmullo.wl r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mmulsum.wq $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mmulsumwq
+mmulsumwq:
+ mmulsum.wq r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mmul.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mmulw
+mmulw:
+ mmul.w r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for movi $imm16, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+movi0:
+ movi 0, r0
+ bnei r0, 0, tr0
+movi1:
+ movi 1, r0
+ bnei r0, 1, tr0
+movi2:
+ movi 23, r0
+ bnei r0, 23, tr0
+movn:
+ movi -1, r0
+ addi r0, 1, r0
+ bnei r0, 0, tr0
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for mperm.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+ movi 27, r1
+ movi 0x1020, r0
+ shlli r0, 8, r0
+ ori r0, 0x30, r0
+ shlli r0, 8, r0
+ ori r0, 0x40, r0
+ shlli r0, 8, r0
+ ori r0, 0x50, r0
+ shlli r0, 8, r0
+ ori r0, 0x60, r0
+ shlli r0, 8, r0
+ ori r0, 0x70, r0
+ shlli r0, 8, r0
+ ori r0, 0x80, r0
+
+mpermw:
+ mperm.w r0, r1, r2
+
+check:
+ # Expect 0x7080506030401020.
+ movi 0x7080, r0
+ shlli r0, 8, r0
+ ori r0, 0x50, r0
+ shlli r0, 8, r0
+ ori r0, 0x60, r0
+ shlli r0, 8, r0
+ ori r0, 0x30, r0
+ shlli r0, 8, r0
+ ori r0, 0x40, r0
+ shlli r0, 8, r0
+ ori r0, 0x10, r0
+ shlli r0, 8, r0
+ ori r0, 0x20, r0
+
+ bne r0, r2, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for msad.ubq $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global msadubq
+msadubq:
+ msad.ubq r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mshalds.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mshaldsl
+mshaldsl:
+ mshalds.l r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mshalds.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mshaldsw
+mshaldsw:
+ mshalds.w r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mshard.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mshardl
+mshardl:
+ mshard.l r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mshards.q $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mshardsq
+mshardsq:
+ mshards.q r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mshard.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mshardw
+mshardw:
+ mshard.w r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mshfhi.b $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mshfhib
+mshfhib:
+ mshfhi.b r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mshfhi.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mshfhil
+mshfhil:
+ mshfhi.l r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mshfhi.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mshfhiw
+mshfhiw:
+ mshfhi.w r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mshflo.b $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mshflob
+mshflob:
+ mshflo.b r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mshflo.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mshflol
+mshflol:
+ mshflo.l r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mshflo.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mshflow
+mshflow:
+ mshflo.w r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mshlld.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mshlldl
+mshlldl:
+ mshlld.l r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mshlld.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mshlldw
+mshlldw:
+ mshlld.w r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mshlrd.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mshlrdl
+mshlrdl:
+ mshlrd.l r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for mshlrd.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mshlrdw
+mshlrdw:
+ mshlrd.w r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for msub.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global msubl
+msubl:
+ msub.l r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for msubs.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global msubsl
+msubsl:
+ msubs.l r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for msubs.ub $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global msubsub
+msubsub:
+ msubs.ub r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for msubs.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global msubsw
+msubsw:
+ msubs.w r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for msub.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global msubw
+msubw:
+ msub.w r0, r0, r0
+
+ pass
--- /dev/null
+# sh testcase for muls.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mulsl
+init:
+ pta wrong, tr0
+
+mulsl1:
+ movi 0, r0
+ muls.l r0, r0, r1
+ bnei r1, 0, tr0
+
+mulsl2:
+ movi 0, r0
+ movi 1, r1
+ muls.l r0, r1, r2
+ bnei r2, 0, tr0
+
+mulsl3:
+ movi 1, r0
+ movi 0, r1
+ muls.l r0, r1, r2
+ bnei r2, 0, tr0
+
+mulsl4:
+ movi 1, r0
+ movi 1, r1
+ muls.l r0, r1, r2
+ bnei r2, 1, tr0
+
+mulsl5:
+ movi 2, r0
+ movi 9, r1
+ muls.l r0, r1, r2
+ bnei r2, 18, tr0
+
+mulsl6:
+ movi 2, r0
+ movi -9, r1
+ muls.l r0, r1, r2
+ bnei r2, -18, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for mulu.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global mulul
+init:
+ pta wrong, tr0
+
+mulul1:
+ movi 0, r0
+ mulu.l r0, r0, r1
+ bnei r1, 0, tr0
+
+mulul2:
+ movi 0, r0
+ movi 1, r1
+ mulu.l r0, r1, r2
+ bnei r2, 0, tr0
+
+mulul3:
+ movi 1, r0
+ movi 0, r1
+ mulu.l r0, r1, r2
+ bnei r2, 0, tr0
+
+mulul4:
+ movi 1, r0
+ movi 1, r1
+ mulu.l r0, r1, r2
+ bnei r2, 1, tr0
+
+mulul5:
+ movi 2, r0
+ movi 9, r1
+ mulu.l r0, r1, r2
+ bnei r2, 18, tr0
+
+mulul6:
+ movi 2, r0
+ movi -9, r1
+ mulu.l r0, r1, r2
+ beqi r2, -18, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for nop -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ nop
+ pass
--- /dev/null
+# sh testcase for nsb $rm, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+nsb0:
+ movi 0, r0
+ nsb r0, r1
+check0:
+ movi 63, r4
+ bne r1, r4, tr0
+
+nsb1:
+ # set up a loop target reg.
+ pta again1, tr1
+ # r4 holds the loop count.
+ movi 62, r4
+ movi 1, r0
+again1:
+ nsb r0, r1
+ bne r1, r4, tr0
+ # okay? go around again.
+ shlli r0, 1, r0
+ addi r4, -1, r4
+ bnei r4, 0, tr1
+
+nsb2:
+ # set up a loop target reg.
+ pta again2, tr1
+ # r4 holds the loop count.
+ movi 63, r4
+ movi -1, r0
+again2:
+ nsb r0, r1
+ bne r1, r4, tr0
+ # okay? go around again.
+ shlli r0, 1, r0
+ addi r4, -1, r4
+ bnei r4, 0, tr1
+
+nsb3:
+ movi 1, r0
+ shlli r0, 63, r0
+ nsb r0, r1
+check3:
+ movi 0, r4
+ bne r1, r4, tr0
+
+nsb4:
+ movi 7, r0
+ shlli r0, 61, r0
+ nsb r0, r1
+check4:
+ movi 2, r4
+ bne r1, r4, tr0
+
+okay:
+ pass
+wrong:
+ fail
--- /dev/null
+# sh testcase for ocbi $rm, $disp6x32 -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ ocbi r0, 0
+ pass
--- /dev/null
+# sh testcase for ocbp $rm, $disp6x32 -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ ocbp r0, 0
+ pass
--- /dev/null
+# sh testcase for ocbwb $rm, $disp6x32 -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ ocbwb r0, 0
+ pass
--- /dev/null
+# sh testcase for or $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+or1:
+ movi 0, r0
+ or r0, r0, r1
+ bnei r1, 0, tr0
+
+or2:
+ movi 0, r0
+ movi 1, r1
+ or r0, r1, r2
+ bnei r2, 1, tr0
+
+or3:
+ movi 1, r0
+ movi 0, r1
+ or r0, r1, r2
+ bnei r2, 1, tr0
+
+or4:
+ movi 1, r0
+ or r0, r0, r1
+ bnei r1, 1, tr0
+
+or5:
+ movi 1, r0
+ shlli r0, 63, r0
+ movi 1, r1
+ or r0, r1, r2
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for ori $rm, $imm10, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+or1:
+ movi 0, r0
+ ori r0, 0, r1
+ bnei r1, 0, tr0
+
+or2:
+ movi 0, r0
+ ori r0, 1, r2
+ bnei r2, 1, tr0
+
+or3:
+ movi 1, r0
+ ori r0, 0, r2
+ bnei r2, 1, tr0
+
+or4:
+ movi 1, r0
+ ori r0, 1, r1
+ bnei r1, 1, tr0
+
+or5:
+ movi 1, r0
+ shlli r0, 63, r0
+ ori r0, 1, r2
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for prefi $rm, $disp6x32 -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ prefi r0, 0
+ pass
--- /dev/null
+# sh testcase for pta$likely $disp16, $tra -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+pta0:
+ pta foo, tr0
+pta1:
+ pta/l bar, tr1
+pta2:
+ pta/u baz, tr2
+ movi 0, r0
+ bnei r0, 1, tr2
+ fail
+
+foo:
+bar:
+baz:
+ pass
+ fail
+ fail
+ fail
+ fail
--- /dev/null
+# sh testcase for ptabs$likely $rn, $tra -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global ptabs
+ptabs:
+ movi 16, r0
+ shlli r0, 8, r0
+ # Add one to stay in SHmedia mode.
+ addi r0, 29, r0
+ ptabs r0, tr0
+
+ # Now jump.
+ beqi r63, 0, tr0
+
+wrong:
+ fail
+
+okay:
+ pass
--- /dev/null
+# sh testcase for ptb$likely $disp16, $tra -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ptb0:
+ ptb foo, tr0
+ptb:
+ ptb/l bar, tr1
+ptb2:
+ ptb/u baz, tr2
+ movi 0, r0
+ bnei r0, 1, tr2
+ fail
+
+.mode SHcompact
+
+foo:
+bar:
+baz:
+ trapa #253
+ trapa #254
+ trapa #254
+ trapa #254
+ trapa #254
--- /dev/null
+# sh testcase for ptrel$likely $rn, $tra -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ # Add one to stay in SHmedia mode.
+ movi 53, r0
+ ptrel r0, tr0
+ movi 0, r0
+ # Always branch.
+ bnei r0, 1, tr0
+ fail
+ fail
+ fail
+ fail
+ fail
+ pass
+ fail
+ fail
--- /dev/null
+# sh testcase for putcfg $rm, $disp6, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ putcfg r0, 0, r0
+ pass
--- /dev/null
+# sh testcase for putcon $rm, $crj -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+putcon1:
+ movi 22, r0
+ putcon r0, cr0
+ getcon cr0, r1
+ bne r0, r1, tr0
+
+putcon2:
+ movi 12, r0
+ shlli r0, 35, r0
+ putcon r0, cr20
+ getcon cr20, r20
+ bne r0, r20, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for rte -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ # Unimplemented.
+ rte
+ pass
--- /dev/null
+# sh testcase for shard $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+shard1:
+ movi 128, r0
+ movi 3, r1
+ shard r0, r1, r2
+ bnei r2, 16, tr0
+
+shard2:
+ movi -4, r0
+ movi 2, r1
+ shard r0, r1, r2
+ addi r2, 1, r2
+ bnei r2, 0, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for shard.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+shardl1:
+ movi 0x1020, r0
+ shlli r0, 8, r0
+ ori r0, 0x30, r0
+ shlli r0, 8, r0
+ ori r0, 0x40, r0
+ shlli r0, 8, r0
+ ori r0, 0x50, r0
+ shlli r0, 8, r0
+ ori r0, 0x60, r0
+ shlli r0, 8, r0
+ ori r0, 0x70, r0
+ shlli r0, 8, r0
+ ori r0, 0x80, r0
+
+ movi 1, r1
+ shard.l r0, r1, r0
+ shard.l r0, r1, r0
+ shard.l r0, r1, r0
+ shard.l r0, r1, r0
+ shard.l r0, r1, r0
+ shard.l r0, r1, r0
+ shard.l r0, r1, r0
+ shard.l r0, r1, r0
+ movi 20, r1
+ shard.l r0, r1, r0
+ bnei r0, 5, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for shari $rm, $imm, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+shari1:
+ movi 128, r0
+ shari r0, 3, r2
+ bnei r2, 16, tr0
+
+shari2:
+ movi -4, r0
+ shari r0, 2, r2
+ addi r2, 1, r2
+ bnei r2, 0, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for shari.l $rm, $imm6, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+sharil1:
+ movi 0x1020, r0
+ shlli r0, 8, r0
+ ori r0, 0x30, r0
+ shlli r0, 8, r0
+ ori r0, 0x40, r0
+ shlli r0, 8, r0
+ ori r0, 0x50, r0
+ shlli r0, 8, r0
+ ori r0, 0x60, r0
+ shlli r0, 8, r0
+ ori r0, 0x70, r0
+ shlli r0, 8, r0
+ ori r0, 0x80, r0
+
+ movi 1, r1
+ shari.l r0, 1, r0
+ shari.l r0, 1, r0
+ shari.l r0, 1, r0
+ shari.l r0, 1, r0
+ shari.l r0, 1, r0
+ shari.l r0, 1, r0
+ shari.l r0, 1, r0
+ shari.l r0, 1, r0
+ shari.l r0, 20, r0
+ bnei r0, 5, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for shlld $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+shlld1:
+ movi 1, r0
+ movi 5, r1
+ shlld r0, r1, r2
+ movi 32, r7
+ bne r2, r7, tr0
+
+shlld2:
+ movi 2, r1
+ shlld r2, r1, r3
+ movi 128, r7
+ bne r3, r7, tr0
+
+shlld3:
+ movi 32, r1
+ shlld r0, r1, r7
+ shlld r7, r1, r2
+ bnei r2, 0, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for shlld.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+shlldl1:
+ movi 1, r0
+ shlli r0, 32, r0
+ ori r0, 1, r0
+ movi 1, r1
+ shlli r1, 7, r1
+ ori r1, 3, r1
+
+ shlld.l r0, r1, r2
+
+check1:
+ bnei r2, 8, tr0
+
+shlldl2:
+ movi 1, r0
+ movi 31, r1
+ shlld.l r0, r1, r2
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for shlli $rm, $imm6, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+shlli:
+ movi 1, r0
+ shlli r0, 3, r0
+ bnei r0, 8, tr0
+
+shlli2:
+ shlli r0, 3, r0
+
+shlli3:
+ # Shift all bits out of sight.
+ shlli r0, 63, r0
+ bnei r0, 0, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for shlli.l $rm, $imm6, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global shllil
+shllil:
+ shlli.l r0, 0, r0
+
+ pass
--- /dev/null
+# sh testcase for shlrd $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+shlrd1:
+ movi 128, r0
+ movi 3, r1
+ shlrd r0, r1, r2
+ bnei r2, 16, tr0
+
+shlrd2:
+ movi -4, r0
+ movi 2, r1
+ shlrd r0, r1, r2
+ addi r2, 1, r2
+ beqi r2, 0, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for shlrd.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+shlrdl1:
+ movi 1, r0
+ shlli r0, 32, r0
+ ori r0, 8, r0
+ movi 1, r1
+ shlli r1, 7, r1
+ ori r1, 3, r1
+
+ shlrd.l r0, r1, r2
+
+check1:
+ bnei r2, 1, tr0
+
+shlrdl2:
+ movi 1, r0
+ shlli r0, 31, r0
+ movi 31, r1
+ shlld.l r0, r1, r2
+ bnei r2, 0, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for shlri $rm, $imm, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+shlri1:
+ movi 128, r0
+ shlri r0, 3, r2
+ bnei r2, 16, tr0
+
+shlri2:
+ movi -4, r0
+ shlri r0, 2, r2
+ addi r2, 1, r2
+ beqi r2, 0, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for shlri.l $rm, $imm6, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global shlril
+shlril:
+ shlri.l r0, 0, r0
+
+ pass
--- /dev/null
+# sh testcase for shori $imm16, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+shori1:
+ movi 1, r0
+ shori 7, r0
+ # check it.
+ andi r0, 15, r7
+ bnei r7, 7, tr0
+ shlri r0, 16, r0
+ bnei r0, 1, tr0
+
+shori2:
+ # Test for zero extension bug reported by
+ # Alexandre Oliva <aoliva@redhat.com>.
+ movi 0, r0
+ shori 65535, r0
+ # check it.
+ movi 0xffff, r1
+ bne r0, r1, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for sleep -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ sleep
+ pass
--- /dev/null
+# sh testcase for st.b $rm, $disp10, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ movi -1, r7
+ xori r7, 13, r7
+ movi 40, r0
+ shlli r0, 8, r0
+
+stb1:
+ st.b r0, 0, r7
+
+stb2:
+ st.b r0, 1, r7
+
+stb3:
+ st.b r0, -1, r7
+
+okay:
+ pass
--- /dev/null
+# sh testcase for sthi.l $rm, $disp6, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+ movi 40, r0
+ shlli r0, 8, r0
+
+ movi 0x1020, r1
+ shlli r1, 8, r1
+ addi r1, 0x30, r1
+ shlli r1, 8, r1
+ addi r1, 0x40, r1
+ shlli r1, 8, r1
+ addi r1, 0x50, r1
+ shlli r1, 8, r1
+ addi r1, 0x60, r1
+ shlli r1, 8, r1
+ addi r1, 0x70, r1
+ shlli r1, 8, r1
+ addi r1, 0x80, r1
+
+sthil1:
+ sthi.l r0, 0, r1
+
+sthil2:
+ sthi.l r0, 1, r1
+
+sthil3:
+ sthi.l r0, 2, r1
+
+sthil4:
+ sthi.l r0, 3, r1
+
+sthil5:
+ sthi.l r0, -1, r1
+
+sthil6:
+ sthi.l r0, -2, r1
+
+sthil7:
+ sthi.l r0, -3, r1
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for sthi.q $rm, $disp6, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+ movi 40, r0
+ shlli r0, 8, r0
+
+ movi 0x1020, r1
+ shlli r1, 8, r1
+ addi r1, 0x30, r1
+ shlli r1, 8, r1
+ addi r1, 0x40, r1
+ shlli r1, 8, r1
+ addi r1, 0x50, r1
+ shlli r1, 8, r1
+ addi r1, 0x60, r1
+ shlli r1, 8, r1
+ addi r1, 0x70, r1
+ shlli r1, 8, r1
+ addi r1, 0x80, r1
+
+sthiq1:
+ sthi.q r0, 0, r1
+
+sthiq2:
+ sthi.q r0, 1, r1
+
+sthiq3:
+ sthi.q r0, 2, r1
+
+sthiq4:
+ sthi.q r0, 3, r1
+
+sthiq5:
+ sthi.q r0, 4, r1
+
+sthiq6:
+ sthi.q r0, 5, r1
+
+sthiq7:
+ sthi.q r0, 6, r1
+
+sthiq8:
+ sthi.q r0, 7, r1
+
+sthiq9:
+ sthi.q r0, -1, r1
+
+sthiq10:
+ sthi.q r0, -2, r1
+
+sthiq11:
+ sthi.q r0, -3, r1
+
+sthiq12:
+ sthi.q r0, -4, r1
+
+sthiq13:
+ sthi.q r0, -5, r1
+
+sthiq14:
+ sthi.q r0, -6, r1
+
+sthiq15:
+ sthi.q r0, -7, r1
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for st.l $rm, $disp10, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ movi -1, r7
+ xori r7, 13, r7
+ movi 40, r0
+ shlli r0, 8, r0
+
+stl1:
+ st.l r0, 0, r7
+
+stl2:
+ st.l r0, 4, r7
+
+stl3:
+ st.l r0, -4, r7
+
+okay:
+ pass
--- /dev/null
+# sh testcase for stlo.l $rm, $disp6, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global stlol
+stlol:
+ stlo.l r0, 0, r0
+
+ pass
--- /dev/null
+# sh testcase for stlo.q $rm, $disp6, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+ .global stloq
+stloq:
+ stlo.q r0, 0, r0
+
+ pass
--- /dev/null
+# sh testcase for st.q $rm, $disp10, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ movi -1, r7
+ xori r7, 13, r7
+ movi 40, r0
+ shlli r0, 8, r0
+
+stq1:
+ st.q r0, 0, r7
+
+stq2:
+ st.q r0, 8, r7
+
+stq3:
+ st.q r0, -8, r7
+
+okay:
+ pass
--- /dev/null
+# sh testcase for st.q $rm, $disp10, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ movi -1, r7
+ xori r7, 13, r7
+ movi 40, r0
+ shlli r0, 8, r0
+
+stw1:
+ st.w r0, 0, r7
+
+stw2:
+ st.w r0, 2, r7
+
+stw3:
+ st.w r0, -2, r7
+
+okay:
+ pass
--- /dev/null
+# sh testcase for stx.b $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ movi -1, r7
+ xori r7, 13, r7
+ movi 40, r0
+ shlli r0, 8, r0
+
+stxb1:
+ movi 0, r1
+ stx.b r0, r1, r7
+
+stxb2:
+ movi 1, r1
+ stx.b r0, r1, r7
+
+stxb3:
+ movi -1, r1
+ stx.b r0, r1, r7
+
+okay:
+ pass
--- /dev/null
+# sh testcase for stx.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ movi -1, r7
+ xori r7, 13, r7
+ movi 40, r0
+ shlli r0, 8, r0
+
+stxl1:
+ movi 0, r1
+ stx.l r0, r1, r7
+
+stxl2:
+ movi 4, r1
+ stx.l r0, r1, r7
+
+stxl3:
+ movi -4, r1
+ stx.l r0, r1, r7
+
+okay:
+ pass
--- /dev/null
+# sh testcase for stx.q $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ movi -1, r7
+ xori r7, 13, r7
+ movi 40, r0
+ shlli r0, 8, r0
+
+stxq1:
+ movi 0, r1
+ stx.q r0, r1, r7
+
+stxq2:
+ movi 8, r1
+ stx.q r0, r1, r7
+
+stxq3:
+ movi -8, r1
+ stx.q r0, r1, r7
+
+okay:
+ pass
--- /dev/null
+# sh testcase for stx.w $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ movi -1, r7
+ xori r7, 13, r7
+ movi 40, r0
+ shlli r0, 8, r0
+
+stxw1:
+ movi 0, r1
+ stx.w r0, r1, r7
+
+stxw2:
+ movi 2, r1
+ stx.w r0, r1, r7
+
+stxw3:
+ movi -2, r1
+ stx.w r0, r1, r7
+
+okay:
+ pass
--- /dev/null
+# sh testcase for sub $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+ movi 0, r0
+ movi 1, r1
+
+sub1:
+ # 0 - 0 = 0.
+ sub r0, r0, r2
+ bnei r2, 0, tr0
+
+sub2:
+ # 1 - 0 = 1.
+ sub r1, r0, r2
+ bnei r2, 1, tr0
+
+sub3:
+ # 0 - 1 = -1.
+ sub r0, r1, r2
+ addi r2, 1, r2
+ bnei r2, 0, tr0
+
+sub4:
+ # 5 - 2 = 3.
+ movi 5, r0
+ movi 2, r1
+ sub r0, r1, r2
+ bnei r2, 3, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for sub.l $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+
+init:
+ pta wrong, tr0
+
+subl1:
+ # Test that the top 32 bits are ignored.
+ movi 1, r0
+ shlli r0, 32, r0
+ ori r0, 7, r0
+
+ movi 1, r1
+ shlli r1, 32, r1
+ ori r1, 2, r1
+
+ sub.l r0, r1, r2
+ bnei r2, 5, tr0
+
+subl2:
+ # Test that 0 - 1 is sign extended.
+ movi 0, r0
+ movi 1, r1
+ sub.l r0, r1, r2
+ addi r2, 1, r2
+ bnei r2, 0, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for swap.q $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ movi 10, r0
+ shlli r0, 8, r0
+ ori r0, 20, r0
+ shlli r0, 8, r0
+ ori r0, 30, r0
+ shlli r0, 8, r0
+ ori r0, 40, r0
+ shlli r0, 8, r0
+ ori r0, 50, r0
+ shlli r0, 8, r0
+ ori r0, 60, r0
+ shlli r0, 8, r0
+ ori r0, 70, r0
+ shlli r0, 8, r0
+ ori r0, 80, r0
+
+ # Set up two address operands.
+
+ movi 40, r1
+ shlli r1, 8, r1
+ movi 8, r2
+
+swapq:
+ swap.q r1, r2, r0
+
+okay:
+ pass
--- /dev/null
+# sh testcase for synci -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ synci
+ pass
--- /dev/null
+# sh testcase for synco -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ synco
+ pass
--- /dev/null
+# Support macros for the assembly test cases.
+
+ .macro start
+ .text
+ .global start
+start:
+ .endm
+
+ .macro pass
+ movi 253, r0
+ trapa r0
+ .endm
+
+ .macro fail
+ movi 254, r0
+ trapa r0
+ .endm
+
+ .macro _packb v1 v2 v3 v4 v5 v6 v7 v8 reg
+ movi \v1, \reg
+ shlli \reg, 8, \reg
+ addi \reg, \v2, \reg
+ shlli \reg, 8, \reg
+ addi \reg, \v3, \reg
+ shlli \reg, 8, \reg
+ addi \reg, \v4, \reg
+ shlli \reg, 8, \reg
+ addi \reg, \v5, \reg
+ shlli \reg, 8, \reg
+ addi \reg, \v6, \reg
+ shlli \reg, 8, \reg
+ addi \reg, \v7, \reg
+ shlli \reg, 8, \reg
+ addi \reg, \v8, \reg
+ .endm
+
+ .macro _packw v1 v2 v3 v4 reg
+ movi \v1, \reg
+ shlli \reg, 16, \reg
+ addi \reg, \v2, \reg
+ shlli \reg, 16, \reg
+ addi \reg, \v3, \reg
+ shlli \reg, 16, \reg
+ addi \reg, \v4, \reg
+ .endm
+
+ .macro _packl v1 v2 reg
+ movi \v1, \reg
+ shlli \reg, 32, \reg
+ addi \reg, \v2, \reg
+ .endm
--- /dev/null
+# sh testcase for trapa $rm -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+ # This performs a trap to emit "pass".
+ movi 253, r0
+ trapa r0
--- /dev/null
+# sh testcase for xor $rm, $rn, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+xor1:
+ # 0 xor 0 = 0.
+ movi 0, r0
+ movi 0, r1
+ xor r0, r1, r2
+ bnei r2, 0, tr0
+
+xor2:
+ # 0 xor 1 = 1.
+ movi 0, r0
+ movi 1, r1
+ xor r0, r1, r2
+ bnei r2, 1, tr0
+
+xor3:
+ # 1 xor 0 = 1.
+ movi 1, r0
+ movi 0, r1
+ xor r0, r1, r2
+ bnei r2, 1, tr0
+
+xor4:
+ # 1 xor 1 = 0.
+ movi 1, r0
+ movi 1, r1
+ xor r0, r1, r2
+ bnei r2, 0, tr0
+
+xor5:
+ movi 1, r0
+ shlli r0, 63, r0
+ ori r0, 1, r0
+ movi 3, r1
+ xor r0, r1, r2
+ andi r2, 255, r2
+ bnei r2, 2, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
+
--- /dev/null
+# sh testcase for xori $rm, $imm6, $rd -*- Asm -*-
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+ .include "media/testutils.inc"
+
+ start
+init:
+ pta wrong, tr0
+
+xori1:
+ # 0 xor 0 = 0.
+ movi 0, r0
+ xori r0, 0, r2
+ bnei r2, 0, tr0
+
+xori2:
+ # 0 xor 1 = 1.
+ movi 0, r0
+ xori r0, 1, r2
+ bnei r2, 1, tr0
+
+xori3:
+ # 1 xor 0 = 1.
+ movi 1, r0
+ xori r0, 0, r2
+ bnei r2, 1, tr0
+
+xori4:
+ # 1 xor 1 = 0.
+ movi 1, r0
+ xori r0, 1, r2
+ bnei r2, 0, tr0
+
+xori5:
+ movi 1, r0
+ shlli r0, 63, r0
+ ori r0, 1, r0
+ xori r0, 3, r2
+ andi r2, 255, r2
+ bnei r2, 2, tr0
+
+okay:
+ pass
+
+wrong:
+ fail
--- /dev/null
+# sh testcase for floating point register shared state (see below).
+# mach: all
+# as: -isa=shmedia
+# ld: -m shelf64
+
+# (fr, dr, fp, fv amd mtrx provide different views of the same architecrual state).
+# Hitachi SH-5 CPU volume 1, p. 15.
+
+ .include "media/testutils.inc"
+
+ start
+
+ movi 42, r0
+ fmov.ls r0, fr12
+ # save this reg.
+ fmov.s fr12, fr14
+
+ movi 42, r0
+ fmov.qd r0, dr12
+
+okay:
+ pass
projects / external / binutils.git / commitdiff