ir3: memory_barrier also controls shared memory access order

nir_intrinsic_memory_barrier has the same semantic as memoryBarrier()
in GLSL, which is:

GLSL 4.60, 4.10. "Memory Qualifiers":
 "The built-in function memoryBarrier() can be used if needed to
 guarantee the completion and relative ordering of memory accesses
 performed by a single shader invocation."

GLSL 4.60, 8.17. "Shader Memory Control Functions":
 "The built-in functions memoryBarrier() and groupMemoryBarrier() wait
 for the completion of accesses to all of the above variable types."

Fixes tests:
 dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.image.guard_nonlocal.workgroup.comp
 dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_nonlocal.workgroup.guard_local.image.comp

Fixes: 819a613a ("freedreno/ir3: moar better scheduler")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9054>

diff --git a/src/freedreno/ci/deqp-freedreno-a630-fails.txt b/src/freedreno/ci/deqp-freedreno-a630-fails.txt
index 4ac5c10..265e166 100644 (file)
--- a/src/freedreno/ci/deqp-freedreno-a630-fails.txt
+++ b/src/freedreno/ci/deqp-freedreno-a630-fails.txt
@@ -129,8 +129,6 @@ dEQP-VK.image.subresource_layout.3d.all_levels.r16g16b16a16_snorm,Fail
 dEQP-VK.image.subresource_layout.3d.all_levels.r8_snorm,Fail
 dEQP-VK.image.subresource_layout.3d.all_levels.r8g8b8a8_snorm,Fail
 dEQP-VK.info.device_mandatory_features,Fail
-dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.image.guard_nonlocal.workgroup.comp,Fail
-dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_nonlocal.workgroup.guard_local.image.comp,Fail
 dEQP-VK.pipeline.framebuffer_attachment.diff_attachments_2d_19x27_32x32_ms,Fail
 dEQP-VK.pipeline.push_descriptor.compute.binding0_numcalls2_combined_image_sampler,Crash
 dEQP-VK.pipeline.push_descriptor.compute.binding0_numcalls2_sampled_image,Crash

diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h
index 89b3474..fb71303 100644 (file)
--- a/src/freedreno/ir3/ir3.h
+++ b/src/freedreno/ir3/ir3.h
@@ -391,7 +391,7 @@ struct ir3_instruction {
         *                            shared  image  atomic  SSBO  everything
         *   barrier()/            -   R/W     R/W    R/W     R/W       X
         *     groupMemoryBarrier()
-        *   memoryBarrier()       -           R/W    R/W
+        *     memoryBarrier()
         *     (but only images declared coherent?)
         *   memoryBarrierAtomic() -                  R/W
         *   memoryBarrierBuffer() -                          R/W

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index 34f165b..5ff5705 100644 (file)
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -1318,18 +1318,6 @@ emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
                barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
                barrier->barrier_class = IR3_BARRIER_EVERYTHING;
                break;
-       case nir_intrinsic_memory_barrier:
-               barrier = ir3_FENCE(b);
-               barrier->cat7.g = true;
-               barrier->cat7.r = true;
-               barrier->cat7.w = true;
-               barrier->cat7.l = true;
-               barrier->barrier_class = IR3_BARRIER_IMAGE_W |
-                               IR3_BARRIER_BUFFER_W;
-               barrier->barrier_conflict =
-                               IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
-                               IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
-               break;
        case nir_intrinsic_memory_barrier_buffer:
                barrier = ir3_FENCE(b);
                barrier->cat7.g = true;
@@ -1359,6 +1347,7 @@ emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
                barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
                                IR3_BARRIER_SHARED_W;
                break;
+       case nir_intrinsic_memory_barrier:
        case nir_intrinsic_group_memory_barrier:
                barrier = ir3_FENCE(b);
                barrier->cat7.g = true;