2013-04-05 Greta Yorsh <Greta.Yorsh@arm.com>
+ * config/arm/arm.md: Comment on splitting Thumb1 patterns.
+
+2013-04-05 Greta Yorsh <Greta.Yorsh@arm.com>
+
* config/arm/arm.md (arm_smax_insn): Convert define_insn into
define_insn_and_split.
(arm_smin_insn,arm_umaxsi3,arm_uminsi3): Likewise.
;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
+;; Beware of splitting Thumb1 patterns that output multiple
+;; assembly instructions, in particular instruction such as SBC and
+;; ADC which consume flags. For example, in the pattern thumb_subdi3
+;; below, the output SUB implicitly sets the flags (assembled to SUBS)
+;; and then the Carry flag is used by SBC to compute the correct
+;; result. If we split thumb_subdi3 pattern into two separate RTL
+;; insns (using define_insn_and_split), the scheduler might place
+;; other RTL insns between SUB and SBC, possibly modifying the Carry
+;; flag used by SBC. This might happen because most Thumb1 patterns
+;; for flag-setting instructions do not have explicit RTL for setting
+;; or clobbering the flags. Instead, they have the attribute "conds"
+;; with value "set" or "clob". However, this attribute is not used to
+;; identify dependencies and therefore the scheduler might reorder
+;; these instruction. Currenly, this problem cannot happen because
+;; there are no separate Thumb1 patterns for individual instruction
+;; that consume flags (except conditional execution, which is treated
+;; differently). In particular there is no Thumb1 armv6-m pattern for
+;; sbc or adc.
+
\f
;;---------------------------------------------------------------------------
;; Constants