emmc: run hs400 200M on sm1 [1/1]
authorRuixuan Li <ruixuan.li@amlogic.com>
Tue, 23 Apr 2019 08:07:12 +0000 (16:07 +0800)
committerJianxin Pan <jianxin.pan@amlogic.com>
Mon, 29 Apr 2019 07:24:59 +0000 (00:24 -0700)
PD#SWPL-5404

Problem:
run hs400 200M on sm1

Solution:
config sm1 and modify dts

Verify:
passed on ac200

Change-Id: I34e54f88db79ce42f9effbf8d673ade613de328f
Signed-off-by: Ruixuan Li <ruixuan.li@amlogic.com>
arch/arm/boot/dts/amlogic/mesonsm1.dtsi
arch/arm/boot/dts/amlogic/sm1_s905d3_ac200.dts
arch/arm64/boot/dts/amlogic/mesonsm1.dtsi
arch/arm64/boot/dts/amlogic/sm1_s905d3_ac200.dts
drivers/amlogic/mmc/aml_sd_emmc.c
drivers/amlogic/mmc/aml_sd_emmc_v3.c

index 3da533ad2ee840942ea040e79cbc6ed0482672a6..26199d1703a4e312c9c19fac62a1332493f8aaac 100644 (file)
                clocks = <&clkc CLKID_SD_EMMC_C>,
                           <&clkc CLKID_SD_EMMC_C_P0_COMP>,
                           <&clkc CLKID_FCLK_DIV2>,
-                          <&clkc CLKID_FCLK_DIV5>,
+                          <&clkc CLKID_FCLK_DIV2P5>,
                           <&xtal>;
                clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
 
                        function = "emmc";
                        input-enable;
                        bias-pull-up;
+                       drive-strength = <3>;
                };
        };
 
                        function = "emmc";
                        input-enable;
                        bias-pull-up;
+                       drive-strength = <3>;
                };
        };
 
                        function = "emmc";
                        input-enable;
                        bias-pull-down;
+                       drive-strength = <3>;
                };
        };
 
index 6a92134389e1c2d964a853643455dfff8022bf3d..99a899e980d7a088270b69988b7bc9e34648a05d 100644 (file)
                         "MMC_CAP_HW_RESET",
                         "MMC_CAP_ERASE",
                         "MMC_CAP_CMD23";
-               caps2 = "MMC_CAP2_HS200";
-               /* "MMC_CAP2_HS400";*/
+               caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
                f_max = <200000000>;
        };
index 25c57a6bf13406f91c062816142e1b703e5d75dd..1548a4be8b884b29436f80535864fa3e4b7450d5 100644 (file)
                clocks = <&clkc CLKID_SD_EMMC_C>,
                           <&clkc CLKID_SD_EMMC_C_P0_COMP>,
                           <&clkc CLKID_FCLK_DIV2>,
-                          <&clkc CLKID_FCLK_DIV5>,
+                          <&clkc CLKID_FCLK_DIV2P5>,
                           <&xtal>;
                clock-names = "core", "clkin0", "clkin1", "clkin2", "xtal";
 
                        function = "emmc";
                        input-enable;
                        bias-pull-up;
+                       drive-strength = <3>;
                };
        };
 
                        function = "emmc";
                        input-enable;
                        bias-pull-up;
+                       drive-strength = <3>;
                };
        };
 
                        function = "emmc";
                        input-enable;
                        bias-pull-down;
+                       drive-strength = <3>;
                };
        };
 
index 3a2c1232439bd0eb206acb8830790ec4a15bd75f..f61aefe65ea337c0226835380e1d7d68e0c66faf 100644 (file)
                         "MMC_CAP_HW_RESET",
                         "MMC_CAP_ERASE",
                         "MMC_CAP_CMD23";
-               caps2 = "MMC_CAP2_HS200";
-               /* "MMC_CAP2_HS400";*/
+               caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
                f_min = <400000>;
                f_max = <200000000>;
        };
index 4c009bbc7862c1f8b8d3d590450d23d016bb8394..5b899c675ab4ae8ac4eccca149da8f4554ac96fc 100644 (file)
@@ -3643,7 +3643,7 @@ static struct meson_mmc_data mmc_data_sm1 = {
        .sdmmc.ddr.tx_phase = 0,
        .sdmmc.hs2.core_phase = 2,
        .sdmmc.hs2.tx_phase = 0,
-       .sdmmc.hs4.tx_delay = 0,
+       .sdmmc.hs4.tx_delay = 16,
        .sdmmc.sd_hs.core_phase = 3,
        .sdmmc.sdr104.core_phase = 2,
        .sdmmc.sdr104.tx_phase = 0,
index 52922d095d1b70f44a9a43b1013048591fccf7c7..4b8480b3142cc97fff4c57de3381d9b7f0b5922a 100644 (file)
@@ -350,7 +350,7 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_platform *pdata,
                                if (pdata->tx_delay != 0)
                                        clkc->tx_delay = pdata->tx_delay;
 
-                               if (((host->data->chip_type == MMC_CHIP_TL1)
+                               if (((host->data->chip_type >= MMC_CHIP_TL1)
                                || (host->data->chip_type == MMC_CHIP_G12B))
                                        && aml_card_type_mmc(pdata)) {
                                        clkc->core_phase = para->hs4.core_phase;
@@ -1883,7 +1883,7 @@ int aml_mmc_execute_tuning_v3(struct mmc_host *mmc, u32 opcode)
                intf3 |= (1<<22);
                writel(intf3, (host->base + SD_EMMC_INTF3));
                pdata->intf3 = intf3;
-               if ((host->data->chip_type == MMC_CHIP_TL1)
+               if ((host->data->chip_type >= MMC_CHIP_TL1)
                        || (host->data->chip_type == MMC_CHIP_G12B))
                        aml_emmc_hs200_tl1(mmc);
                err = 0;
@@ -1901,7 +1901,8 @@ int aml_post_hs400_timming(struct mmc_host *mmc)
        struct amlsd_platform *pdata = mmc_priv(mmc);
        struct amlsd_host *host = pdata->host;
        aml_sd_emmc_clktest(mmc);
-       if (host->data->chip_type == MMC_CHIP_TL1)
+       if ((host->data->chip_type == MMC_CHIP_TL1)
+               || (host->data->chip_type == MMC_CHIP_SM1))
                aml_emmc_hs400_tl1(mmc);
        else if (host->data->chip_type == MMC_CHIP_G12B)
                aml_emmc_hs400_Revb(mmc);