The purpose of this commit is to synchronize opcode definitions across
the gen4asm assembler and mesa.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
GLuint dest_address_mode:1;
} ia16; /* indirect align16 */
+ struct {
+ GLuint dest_reg_file:2;
+ GLuint dest_reg_type:3;
+ GLuint src0_reg_file:2;
+ GLuint src0_reg_type:3;
+ GLuint src1_reg_file:2;
+ GLuint src1_reg_type:3;
+ GLuint pad:1;
+
+ GLint jump_count:16;
+ } branch_gen6;
+
struct
{
GLuint dest_reg_file:1; /* used in Gen6, deleted in Gen7 */
GLuint dest_reg_nr:8;
} da3src;
- struct
- {
- GLuint pad:16;
- GLint JIP:16;
- } branch; /* conditional branch JIP for Gen6 only */
} bits1;
if(opcode == BRW_OPCODE_CALL || opcode == BRW_OPCODE_JMPI)
entry->instruction.bits3.JIP = offset; // for CALL, JMPI
else
- entry->instruction.bits1.branch.JIP = offset; // for CASE,ELSE,FORK,IF,WHILE
+ entry->instruction.bits1.branch_gen6.jump_count = offset; // for CASE,ELSE,FORK,IF,WHILE
} else if(IS_GENp(7)) {
int opcode = entry->instruction.header.opcode;
/* Gen7 JMPI Restrictions in bspec: