arm64: dts: qcom: db845c: Add support for MCP2517FD

Add support for onboard MCP2517FD SPI CAN transceiver attached to
SPI0 of RB3.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220421073438.1824061-1-vkoul@kernel.org

diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index 9206efa..194ebeb 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -28,6 +28,13 @@
                stdout-path = "serial0:115200n8";
        };
 
+       /* Fixed crystal oscillator dedicated to MCP2517FD */
+       clk40M: can-clock {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <40000000>;
+       };
+
        dc12v: dc12v-regulator {
                compatible = "regulator-fixed";
                regulator-name = "DC12V";
@@ -746,6 +753,23 @@
        };
 };
 
+&spi0 {
+       status = "okay";
+       pinctrl-names = "default";
+       pinctrl-0 = <&qup_spi0_default>;
+       cs-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
+
+       can@0 {
+               compatible = "microchip,mcp2517fd";
+               reg = <0>;
+               clocks = <&clk40M>;
+               interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
+               spi-max-frequency = <10000000>;
+               vdd-supply = <&vdc_5v>;
+               xceiver-supply = <&vdc_5v>;
+       };
+};
+
 &spi2 {
        /* On Low speed expansion */
        label = "LS-SPI0";
@@ -1220,3 +1244,11 @@
                };
        };
 };
+
+/* PINCTRL - additions to nodes defined in sdm845.dtsi */
+&qup_spi0_default {
+       config {
+               drive-strength = <6>;
+               bias-disable;
+       };
+};