MIPS: don't use camel-case style

Replace camel-case style with upper-case style globally.

Signed-off-by: Zhizhou Zhang <etou.zh@gmail.com>

diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index e683e8be8cb9e8b42c1f53ac300fafea7672bdff..64dfad026324fc573d0b4a17965792826acec3e6 100644 (file)
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -85,17 +85,17 @@ LEAF(mips_init_icache)
        /* clear tag to invalidate */
        PTR_LI          t0, INDEX_BASE
        PTR_ADDU        t1, t0, a1
-1:     cache_op        Index_Store_Tag_I t0
+1:     cache_op        INDEX_STORE_TAG_I t0
        PTR_ADDU        t0, a2
        bne             t0, t1, 1b
        /* fill once, so data field parity is correct */
        PTR_LI          t0, INDEX_BASE
-2:     cache_op        Fill t0
+2:     cache_op        FILL t0
        PTR_ADDU        t0, a2
        bne             t0, t1, 2b
        /* invalidate again - prudent but not strictly neccessary */
        PTR_LI          t0, INDEX_BASE
-1:     cache_op        Index_Store_Tag_I t0
+1:     cache_op        INDEX_STORE_TAG_I t0
        PTR_ADDU        t0, a2
        bne             t0, t1, 1b
 9:     jr              ra
@@ -110,7 +110,7 @@ LEAF(mips_init_dcache)
        /* clear all tags */
        PTR_LI          t0, INDEX_BASE
        PTR_ADDU        t1, t0, a1
-1:     cache_op        Index_Store_Tag_D t0
+1:     cache_op        INDEX_STORE_TAG_D t0
        PTR_ADDU        t0, a2
        bne             t0, t1, 1b
        /* load from each line (in cached space) */
@@ -120,7 +120,7 @@ LEAF(mips_init_dcache)
        bne             t0, t1, 2b
        /* clear all tags */
        PTR_LI          t0, INDEX_BASE
-1:     cache_op        Index_Store_Tag_D t0
+1:     cache_op        INDEX_STORE_TAG_D t0
        PTR_ADDU        t0, a2
        bne             t0, t1, 1b
 9:     jr              ra

diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c
index 7b49e1b612b70b876e6b78c27d4a52a7dc176b2b..50bb248bd0102ab12f04952572ecc32edc6d76b4 100644 (file)
--- a/arch/mips/cpu/mips32/cpu.c
+++ b/arch/mips/cpu/mips32/cpu.c
@@ -61,8 +61,8 @@ void flush_cache(ulong start_addr, ulong size)
                return;
 
        while (1) {
-               cache_op(Hit_Writeback_Inv_D, addr);
-               cache_op(Hit_Invalidate_I, addr);
+               cache_op(HIT_WRITEBACK_INV_D, addr);
+               cache_op(HIT_INVALIDATE_I, addr);
                if (addr == aend)
                        break;
                addr += lsize;
@@ -76,7 +76,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
        unsigned long aend = (stop - 1) & ~(lsize - 1);
 
        while (1) {
-               cache_op(Hit_Writeback_Inv_D, addr);
+               cache_op(HIT_WRITEBACK_INV_D, addr);
                if (addr == aend)
                        break;
                addr += lsize;
@@ -90,7 +90,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
        unsigned long aend = (stop - 1) & ~(lsize - 1);
 
        while (1) {
-               cache_op(Hit_Invalidate_D, addr);
+               cache_op(HIT_INVALIDATE_D, addr);
                if (addr == aend)
                        break;
                addr += lsize;

diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index ddcbfaa47c93f858d7a68f6fb9812ed35cb57636..cc190dfe56e13f45f2b92000ffb6e042ef2095e3 100644 (file)
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -84,8 +84,8 @@ void flush_cache(ulong start_addr, ulong size)
        unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
 
        for (; addr <= aend; addr += lsize) {
-               cache_op(Hit_Writeback_Inv_D, addr);
-               cache_op(Hit_Invalidate_I, addr);
+               cache_op(HIT_WRITEBACK_INV_D, addr);
+               cache_op(HIT_INVALIDATE_I, addr);
        }
 }
 
@@ -96,7 +96,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
        unsigned long aend = (stop - 1) & ~(lsize - 1);
 
        for (; addr <= aend; addr += lsize)
-               cache_op(Hit_Writeback_Inv_D, addr);
+               cache_op(HIT_WRITEBACK_INV_D, addr);
 }
 
 void invalidate_dcache_range(ulong start_addr, ulong stop)
@@ -106,7 +106,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
        unsigned long aend = (stop - 1) & ~(lsize - 1);
 
        for (; addr <= aend; addr += lsize)
-               cache_op(Hit_Invalidate_D, addr);
+               cache_op(HIT_INVALIDATE_D, addr);
 }
 
 void flush_icache_all(void)
@@ -118,7 +118,7 @@ void flush_icache_all(void)
 
        for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
             addr += CONFIG_SYS_CACHELINE_SIZE) {
-               cache_op(Index_Store_Tag_I, addr);
+               cache_op(INDEX_STORE_TAG_I, addr);
        }
 
        /* invalidate btb */
@@ -139,7 +139,7 @@ void flush_dcache_all(void)
 
        for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
             addr += CONFIG_SYS_CACHELINE_SIZE) {
-               cache_op(Index_Writeback_Inv_D, addr);
+               cache_op(INDEX_WRITEBACK_INV_D, addr);
        }
 
        __asm__ __volatile__("sync");

diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S
index d846104d10151ed8a4b40c4a2a2f60254b29fba0..3a8280cb0ab850deaf36731e4c705f449a832866 100644 (file)
--- a/arch/mips/cpu/xburst/start.S
+++ b/arch/mips/cpu/xburst/start.S
@@ -96,7 +96,7 @@ relocate_code:
        li      t0, KSEG0
        addi    t1, t0, CONFIG_SYS_DCACHE_SIZE
 2:
-       cache   Index_Writeback_Inv_D, 0(t0)
+       cache   INDEX_WRITEBACK_INV_D, 0(t0)
        bne     t0, t1, 2b
         addi   t0, CONFIG_SYS_CACHELINE_SIZE
 
@@ -106,7 +106,7 @@ relocate_code:
        li      t0, KSEG0
        addi    t1, t0, CONFIG_SYS_ICACHE_SIZE
 3:
-       cache   Index_Invalidate_I, 0(t0)
+       cache   INDEX_INVALIDATE_I, 0(t0)
        bne     t0, t1, 3b
         addi   t0, CONFIG_SYS_CACHELINE_SIZE
 

diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 608cfcfbb3eaad36da1e19f539bb3efa5084cfef..933ccb1b7864abb9993bcaa187f25f15c9878dbf 100644 (file)
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -401,7 +401,7 @@ symbol              =       value
 #ifdef CONFIG_SGI_IP28
 /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
 #include <asm/cacheops.h>
-#define R10KCBARRIER(addr)  cache   Cache_Barrier, addr;
+#define R10KCBARRIER(addr)  cache   CACHE_BARRIER, addr;
 #else
 #define R10KCBARRIER(addr)
 #endif

diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 70bcad7694dfc48410551c3a7c571fadfef764db..6464250d8486ec6261c1c6066dd7bb104dd61ee9 100644 (file)
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -14,54 +14,54 @@
 /*
  * Cache Operations available on all MIPS processors with R4000-style caches
  */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
-#define Index_Load_Tag_I       0x04
-#define Index_Load_Tag_D       0x05
-#define Index_Store_Tag_I      0x08
-#define Index_Store_Tag_D      0x09
+#define INDEX_INVALIDATE_I      0x00
+#define INDEX_WRITEBACK_INV_D   0x01
+#define INDEX_LOAD_TAG_I       0x04
+#define INDEX_LOAD_TAG_D       0x05
+#define INDEX_STORE_TAG_I      0x08
+#define INDEX_STORE_TAG_D      0x09
 #if defined(CONFIG_CPU_LOONGSON2)
-#define Hit_Invalidate_I       0x00
+#define HIT_INVALIDATE_I       0x00
 #else
-#define Hit_Invalidate_I       0x10
+#define HIT_INVALIDATE_I       0x10
 #endif
-#define Hit_Invalidate_D       0x11
-#define Hit_Writeback_Inv_D    0x15
+#define HIT_INVALIDATE_D       0x11
+#define HIT_WRITEBACK_INV_D    0x15
 
 /*
  * R4000-specific cacheops
  */
-#define Create_Dirty_Excl_D    0x0d
-#define Fill                   0x14
-#define Hit_Writeback_I                0x18
-#define Hit_Writeback_D                0x19
+#define CREATE_DIRTY_EXCL_D    0x0d
+#define FILL                   0x14
+#define HIT_WRITEBACK_I                0x18
+#define HIT_WRITEBACK_D                0x19
 
 /*
  * R4000SC and R4400SC-specific cacheops
  */
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_SI      0x06
-#define Index_Load_Tag_SD      0x07
-#define Index_Store_Tag_SI     0x0A
-#define Index_Store_Tag_SD     0x0B
-#define Create_Dirty_Excl_SD   0x0f
-#define Hit_Invalidate_SI      0x12
-#define Hit_Invalidate_SD      0x13
-#define Hit_Writeback_Inv_SD   0x17
-#define Hit_Writeback_SD       0x1b
-#define Hit_Set_Virtual_SI     0x1e
-#define Hit_Set_Virtual_SD     0x1f
+#define INDEX_INVALIDATE_SI     0x02
+#define INDEX_WRITEBACK_INV_SD  0x03
+#define INDEX_LOAD_TAG_SI      0x06
+#define INDEX_LOAD_TAG_SD      0x07
+#define INDEX_STORE_TAG_SI     0x0A
+#define INDEX_STORE_TAG_SD     0x0B
+#define CREATE_DIRTY_EXCL_SD   0x0f
+#define HIT_INVALIDATE_SI      0x12
+#define HIT_INVALIDATE_SD      0x13
+#define HIT_WRITEBACK_INV_SD   0x17
+#define HIT_WRITEBACK_SD       0x1b
+#define HIT_SET_VIRTUAL_SI     0x1e
+#define HIT_SET_VIRTUAL_SD     0x1f
 
 /*
  * R5000-specific cacheops
  */
-#define R5K_Page_Invalidate_S  0x17
+#define R5K_PAGE_INVALIDATE_S  0x17
 
 /*
  * RM7000-specific cacheops
  */
-#define Page_Invalidate_T      0x16
+#define PAGE_INVALIDATE_T      0x16
 
 /*
  * R10000-specific cacheops
@@ -69,17 +69,17 @@
  * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
  * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
  */
-#define Index_Writeback_Inv_S  0x03
-#define Index_Load_Tag_S       0x07
-#define Index_Store_Tag_S      0x0B
-#define Hit_Invalidate_S       0x13
-#define Cache_Barrier          0x14
-#define Hit_Writeback_Inv_S    0x17
-#define Index_Load_Data_I      0x18
-#define Index_Load_Data_D      0x19
-#define Index_Load_Data_S      0x1b
-#define Index_Store_Data_I     0x1c
-#define Index_Store_Data_D     0x1d
-#define Index_Store_Data_S     0x1f
+#define INDEX_WRITEBACK_INV_S  0x03
+#define INDEX_LOAD_TAG_S       0x07
+#define INDEX_STORE_TAG_S      0x0B
+#define HIT_INVALIDATE_S       0x13
+#define CACHE_BARRIER          0x14
+#define HIT_WRITEBACK_INV_S    0x17
+#define INDEX_LOAD_DATA_I      0x18
+#define INDEX_LOAD_DATA_D      0x19
+#define INDEX_LOAD_DATA_S      0x1b
+#define INDEX_STORE_DATA_I     0x1c
+#define INDEX_STORE_DATA_D     0x1d
+#define INDEX_STORE_DATA_S     0x1f
 
 #endif /* __ASM_CACHEOPS_H */