Fix MSVC 'result of 32-bit shift implicitly converted to 64 bits' warning. NFCI.

llvm-svn: 316271

diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
index 946f99cdb52eef95afeab6c62f884d289544553c..b23da692498e5aa7c3e1e1cce9e2d3e1843ef938 100644 (file)
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -1298,7 +1298,7 @@ inline bool HexagonDAGToDAGISel::SelectAnyInt(SDValue &N, SDValue &R) {
 bool HexagonDAGToDAGISel::SelectAnyImmediate(SDValue &N, SDValue &R,
                                              uint32_t LogAlign) {
   auto IsAligned = [LogAlign] (uint64_t V) -> bool {
-    return alignTo(V, 1u << LogAlign) == V;
+    return alignTo(V, (uint64_t)1 << LogAlign) == V;
   };
 
   switch (N.getOpcode()) {
@@ -1342,7 +1342,7 @@ bool HexagonDAGToDAGISel::SelectAnyImmediate(SDValue &N, SDValue &R,
 bool HexagonDAGToDAGISel::SelectGlobalAddress(SDValue &N, SDValue &R,
                                               bool UseGP, uint32_t LogAlign) {
   auto IsAligned = [LogAlign] (uint64_t V) -> bool {
-    return alignTo(V, 1u << LogAlign) == V;
+    return alignTo(V, (uint64_t)1 << LogAlign) == V;
   };
 
   switch (N.getOpcode()) {