drm/amd/display: Align bw context with hw config when system resume
authorLewis Huang <Lewis.Huang@amd.com>
Wed, 29 Sep 2021 08:32:15 +0000 (16:32 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 28 Oct 2021 18:26:13 +0000 (14:26 -0400)
[Why]
When the vbios config and driver config are different, if we update
clock to lower before call program_timing and program_pixel_clk, garbage
appear.

[How]
Align bw context with hw config when system resume

Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: Lewis Huang <Lewis.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

index 44d2757..a25732d 100644 (file)
@@ -1378,6 +1378,12 @@ void dcn10_init_hw(struct dc *dc)
        if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
                dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
 
+       /* Align bw context with hw config when system resume. */
+       if (dc->clk_mgr->clks.dispclk_khz != 0 && dc->clk_mgr->clks.dppclk_khz != 0) {
+               dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz = dc->clk_mgr->clks.dispclk_khz;
+               dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz = dc->clk_mgr->clks.dppclk_khz;
+       }
+
        // Initialize the dccg
        if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->dccg_init)
                dc->res_pool->dccg->funcs->dccg_init(res_pool->dccg);