dt-bindings: usb: dwc3-xilinx: Add documentation for Versal DWC3 Controller

Add documentation for Versal DWC3 controller. Add required property
'reg' for the same. Also add optional properties for snps,dwc3.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Link: https://lore.kernel.org/r/1615963949-75320-2-git-send-email-manish.narani@xilinx.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
index a668f43..04813a4 100644 (file)
--- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
@@ -1,32 +1,56 @@
 Xilinx SuperSpeed DWC3 USB SoC controller
 
 Required properties:
-- compatible:  Should contain "xlnx,zynqmp-dwc3"
+- compatible:  May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3"
+- reg:         Base address and length of the register control block
 - clocks:      A list of phandles for the clocks listed in clock-names
 - clock-names: Should contain the following:
   "bus_clk"     Master/Core clock, have to be >= 125 MHz for SS
                 operation and >= 60MHz for HS operation
 
   "ref_clk"     Clock source to core during PHY power down
+- resets:      A list of phandles for resets listed in reset-names
+- reset-names:
+  "usb_crst"    USB core reset
+  "usb_hibrst"  USB hibernation reset
+  "usb_apbrst"  USB APB reset
 
 Required child node:
 A child node must exist to represent the core DWC3 IP block. The name of
 the node is not important. The content of the node is defined in dwc3.txt.
 
+Optional properties for snps,dwc3:
+- dma-coherent:        Enable this flag if CCI is enabled in design. Adding this
+               flag configures Global SoC bus Configuration Register and
+               Xilinx USB 3.0 IP - USB coherency register to enable CCI.
+- interrupt-names: Should contain the following:
+  "dwc_usb3"   USB gadget mode interrupts
+  "otg"                USB OTG mode interrupts
+  "hiber"      USB hibernation interrupts
+
 Example device node:
 
                usb@0 {
                        #address-cells = <0x2>;
                        #size-cells = <0x1>;
                        compatible = "xlnx,zynqmp-dwc3";
+                       reg = <0x0 0xff9d0000 0x0 0x100>;
                        clock-names = "bus_clk", "ref_clk";
                        clocks = <&clk125>, <&clk125>;
+                       resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
+                                <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
+                                <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
+                       reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
                        ranges;
 
                        dwc3@fe200000 {
                                compatible = "snps,dwc3";
                                reg = <0x0 0xfe200000 0x40000>;
-                               interrupts = <0x0 0x41 0x4>;
+                               interrupt-names = "dwc_usb3", "otg", "hiber";
+                               interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
+                               phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+                               phy-names = "usb3-phy";
                                dr_mode = "host";
+                               dma-coherent;
                        };
                };