* c - Hotfix Release
* xxxx - Graphics internal build #
*/
-#define PSB_PACKAGE_VERSION "5.6.0.1152"
+#define PSB_PACKAGE_VERSION "5.6.0.1153"
#define DRM_PSB_SAREA_MAJOR 0
#define DRM_PSB_SAREA_MINOR 2
LNC_VIDEO_DEVICE_INFO,
LNC_VIDEO_GETPARAM_RAR_INFO,
LNC_VIDEO_GETPARAM_CI_INFO,
- LNC_VIDEO_GETPARAM_RAR_HANDLER_OFFSET,
LNC_VIDEO_FRAME_SKIP,
IMG_VIDEO_DECODE_STATUS,
IMG_VIDEO_NEW_CONTEXT,
#ifdef CONFIG_GFX_RTPM
#include <linux/pm_runtime.h>
#endif
-#if defined(CONFIG_RAR_REGISTER)
-#include "../../rar_register/rar_register.h"
-#include "../../memrar/memrar.h"
-#endif
#include <asm/intel_scu_ipc.h>
return;
}
-static void get_rar_info(struct drm_psb_private *dev_priv)
-{
-#if defined(CONFIG_RAR_REGISTER)
- int ret;
- dma_addr_t start_addr, end_addr;
-
- dev_priv->rar_region_start = 0;
- dev_priv->rar_region_size = 0;
- end_addr = 0;
- ret = 0;
-
- ret = rar_get_address(RAR_TYPE_VIDEO, &start_addr,
- &end_addr);
- if (ret) {
- printk(KERN_ERR "failed to get rar region info\n");
- return;
- }
- dev_priv->rar_region_start = (uint32_t) start_addr;
- if ((!ret) && (start_addr != 0) && (end_addr != 0))
- dev_priv->rar_region_size =
- end_addr - dev_priv->rar_region_start + 1;
-
-#endif
- return;
-}
static void get_imr_info(struct drm_psb_private *dev_priv)
u32 high, low, start, end;
int size = 0;
- low = MDFLD_MSG_READ32(PNW_IMR_MSG_PORT, PNW_IMR3L_MSG_REGADDR);
- high = MDFLD_MSG_READ32(PNW_IMR_MSG_PORT, PNW_IMR3H_MSG_REGADDR);
+ low = MDFLD_MSG_READ32(PNW_IMR_MSG_PORT, PNW_IMR4L_MSG_REGADDR);
+ high = MDFLD_MSG_READ32(PNW_IMR_MSG_PORT, PNW_IMR4H_MSG_REGADDR);
start = (low & PNW_IMR_ADDRESS_MASK) << PNW_IMR_ADDRESS_SHIFT;
end = (high & PNW_IMR_ADDRESS_MASK) << PNW_IMR_ADDRESS_SHIFT;
if (end > start)
size = end - start + 1;
if (size > 0) {
dev_priv->rar_region_start = start;
- dev_priv->rar_region_size = size;
+ dev_priv->rar_region_size = size & PAGE_MASK;
} else {
dev_priv->rar_region_start = 0;
dev_priv->rar_region_size = 0;
}
- DRM_INFO("IMR3 start=0x%08x, size=%dB\n",
+ DRM_INFO("IMR4 start=0x%08x, size=%dB (%d pages)\n",
dev_priv->rar_region_start,
- dev_priv->rar_region_size);
+ dev_priv->rar_region_size,
+ dev_priv->rar_region_size >> PAGE_SHIFT);
return;
}
struct ttm_bo_device *bdev = &dev_priv->bdev;
struct psb_gtt *pg = dev_priv->pg;
+ uint32_t tmp;
uint32_t stolen_gtt;
uint32_t tt_start;
uint32_t tt_pages;
tt_pages -= tt_start >> PAGE_SHIFT;
dev_priv->sizes.ta_mem_size = 0;
-#ifdef CONFIG_MDFD_VIDEO_DECODE
-
+ /* CI region managed by TTM */
+ tmp = dev_priv->ci_region_size >> PAGE_SHIFT; /* CI region size */
if (IS_MRST(dev) &&
(dev_priv->ci_region_size != 0) &&
- !ttm_bo_init_mm(bdev, TTM_PL_CI,
- dev_priv->ci_region_size >> PAGE_SHIFT)) {
+ !ttm_bo_init_mm(bdev, TTM_PL_CI, tmp))
dev_priv->have_camera = 1;
- }
- /* since there is always rar region for video, it is ok */
+ /* RAR region managed by TTM */
+ tmp = dev_priv->rar_region_size >> PAGE_SHIFT; /* RAR region size */
if ((dev_priv->rar_region_size != 0) &&
- !ttm_bo_init_mm(bdev, TTM_PL_RAR,
- dev_priv->rar_region_size >> PAGE_SHIFT)) {
+ !ttm_bo_init_mm(bdev, TTM_PL_RAR, tmp))
dev_priv->have_rar = 1;
- }
/* TT region managed by TTM. */
- if (!ttm_bo_init_mm(bdev, TTM_PL_TT,
- pg->gatt_pages -
- (pg->ci_start >> PAGE_SHIFT) -
- ((dev_priv->ci_region_size + dev_priv->rar_region_size)
- >> PAGE_SHIFT))) {
-
+ tmp = pg->gatt_pages -
+ (pg->ci_start >> PAGE_SHIFT) -
+ (dev_priv->ci_region_size >> PAGE_SHIFT); /* TT region size */
+ if (!ttm_bo_init_mm(bdev, TTM_PL_TT, tmp))
dev_priv->have_tt = 1;
- dev_priv->sizes.tt_size =
- (tt_pages << PAGE_SHIFT) / (1024 * 1024) / 2;
- }
- if (!ttm_bo_init_mm(bdev,
- DRM_PSB_MEM_MMU,
- PSB_MEM_TT_START >> PAGE_SHIFT)) {
+ /* MMU region managed by TTM */
+ tmp = PSB_MEM_RAR_START >> PAGE_SHIFT; /* MMU region size:MMU->RAR */
+ if (!ttm_bo_init_mm(bdev, DRM_PSB_MEM_MMU, tmp))
dev_priv->have_mem_mmu = 1;
- dev_priv->sizes.mmu_size =
- PSB_MEM_TT_START / (1024 * 1024);
- }
-
PSB_DEBUG_INIT("Init MSVDX\n");
psb_msvdx_init(dev);
else
ospm_power_island_down(OSPM_VIDEO_ENC_ISLAND);
}
-#endif
return 0;
out_err:
PSB_DEBUG_INIT("Init TTM fence and BO driver\n");
- if (IS_MRST(dev)) {
+ if (IS_MRST(dev))
get_ci_info(dev_priv);
- get_rar_info(dev_priv);
- }
if (IS_MDFLD(dev))
get_imr_info(dev_priv);
ret = psb_mmu_insert_pfn_sequence(
psb_mmu_get_default_pd(dev_priv->mmu),
dev_priv->rar_region_start >> PAGE_SHIFT,
- pg->mmu_gatt_start + pg->rar_start,
+ PSB_MEM_RAR_START,
pg->rar_stolen_size >> PAGE_SHIFT, 0);
up_read(&pg->sem);
if (ret)
#define IS_MSVDX(dev) (IS_MRST(dev) || IS_MDFLD(dev))
#define IS_TOPAZ(dev) ((IS_MRST(dev) && (((dev)->pci_device & 0xfffc) != PCI_ID_TOPAZ_DISABLED)) || IS_MDFLD(dev))
-#define IS_D0(dev) ((dev)->pdev->revision == 0xc)
+#define IS_D0(dev) ((dev)->pdev->revision >= 0xc)
extern int drm_psb_ospm;
extern int drm_psb_cpurelax;
pte = psb_gtt_mask_pte(pfn_base + i, 0);
iowrite32(pte, ttm_gtt_map + i);
}
-
- /*
- * insert RAR stolen pages
- */
- if (rar_stolen_size != 0) {
- pfn_base = dev_priv->rar_region_start >> PAGE_SHIFT;
- num_pages = rar_stolen_size >> PAGE_SHIFT;
- printk(KERN_INFO"Set up %d RAR stolen pages starting at 0x%08x, GTT offset %dK\n",
- num_pages, pfn_base,
- (ttm_gtt_map - pg->gtt_map + i) * 4);
- for (; i < num_pages + ci_pages; ++i) {
- pte = psb_gtt_mask_pte(pfn_base + i - ci_pages, 0);
- iowrite32(pte, ttm_gtt_map + i);
- }
- }
/*
* Init rest of gtt managed by TTM.
*/
vdc_stat &= dev_priv->vdc_irq_mask;
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irq_flags);
+ /*
+ Ignore interrupt if sub-system is already
+ powered gated; nothing needs to be done,
+ when HW is already power-gated
+ - saftey check to avoid illegal HW access.
+ */
if (dsp_int && ospm_power_is_hw_on(OSPM_DISPLAY_ISLAND)) {
psb_vdc_interrupt(dev, vdc_stat);
handled = 1;
}
#ifdef CONFIG_MDFD_VIDEO_DECODE
- if (msvdx_int && (IS_MDFLD(dev)
- || ospm_power_is_hw_on(OSPM_VIDEO_DEC_ISLAND))) {
+ if (msvdx_int && IS_MDFLD(dev)
+ && ospm_power_is_hw_on(OSPM_VIDEO_DEC_ISLAND)) {
psb_msvdx_interrupt(dev);
handled = 1;
}
- if ((IS_MDFLD(dev) && topaz_int)) {
+ if ((IS_MDFLD(dev) && topaz_int
+ && ospm_power_is_hw_on(OSPM_VIDEO_ENC_ISLAND))) {
pnw_topaz_interrupt(dev);
handled = 1;
} else if (IS_MRST(dev) && topaz_int &&
ospm_power_is_hw_on(OSPM_VIDEO_ENC_ISLAND)) {
- /* sometimes, even topaz power down, IIR
- * may still have topaz bit set
- */
lnc_topaz_interrupt(dev);
handled = 1;
}
#endif
- if (sgx_int) {
+ if (sgx_int && ospm_power_is_hw_on(OSPM_GRAPHICS_ISLAND)) {
if (SYSPVRServiceSGXInterrupt(dev) != 0)
handled = 1;
}
#ifdef CONFIG_MDFD_GL3
- if (gl3_int) {
+ if (gl3_int && ospm_power_is_hw_on(OSPM_GL3_CACHE_ISLAND)) {
mdfld_gl3_interrupt(dev, vdc_stat);
handled = 1;
}
If pmu_nc_set_power_state fails then accessing HW
reg would result in a crash - IERR/Fabric error.
*/
+ spin_lock_irqsave(&dev_priv->ospm_lock, flags);
if (pmu_nc_set_power_state(dc_islands,
OSPM_ISLAND_UP, OSPM_REG_TYPE))
BUG();
+ g_hw_power_status_mask |= OSPM_DISPLAY_ISLAND;
+ spin_unlock_irqrestore(&dev_priv->ospm_lock, flags);
/* handle other islands */
gfx_islands = hw_islands & ~OSPM_DISPLAY_ISLAND;
If pmu_nc_set_power_state fails then accessing HW
reg would result in a crash - IERR/Fabric error.
*/
+
+ if (IS_D0(gpDrmDevice)) {
+ /*
+ * GL3 power island needs to be on for MSVDX working.
+ * We found this during enabling new MSVDX firmware
+ * uploading mechanism(by PUNIT) for Penwell D0.
+ */
+ if ((gfx_islands & OSPM_VIDEO_DEC_ISLAND) &&
+ !ospm_power_is_hw_on(OSPM_GL3_CACHE_ISLAND))
+ gfx_islands |= OSPM_GL3_CACHE_ISLAND;
+ }
+
+ spin_lock_irqsave(&dev_priv->ospm_lock, flags);
if (pmu_nc_set_power_state(gfx_islands,
- OSPM_ISLAND_UP, APM_REG_TYPE))
+ OSPM_ISLAND_UP, APM_REG_TYPE))
BUG();
+ g_hw_power_status_mask |= gfx_islands;
+ spin_unlock_irqrestore(&dev_priv->ospm_lock, flags);
}
-
- spin_lock_irqsave(&dev_priv->ospm_lock, flags);
- g_hw_power_status_mask |= hw_islands;
- spin_unlock_irqrestore(&dev_priv->ospm_lock, flags);
}
/*
* ospm_power_resume
struct drm_psb_private *dev_priv =
(struct drm_psb_private *) gpDrmDevice->dev_private;
- spin_lock_irqsave(&dev_priv->ospm_lock, flags);
- g_hw_power_status_mask &= ~hw_islands;
- spin_unlock_irqrestore(&dev_priv->ospm_lock, flags);
-
#ifdef OSPM_GFX_DPK
printk(KERN_ALERT "%s hw_islands: %x\n",
__func__, hw_islands);
If pmu_nc_set_power_state fails then accessing HW
reg would result in a crash - IERR/Fabric error.
*/
+ spin_lock_irqsave(&dev_priv->ospm_lock, flags);
+ g_hw_power_status_mask &= ~OSPM_DISPLAY_ISLAND;
if (pmu_nc_set_power_state(dc_islands,
- OSPM_ISLAND_DOWN, OSPM_REG_TYPE))
+ OSPM_ISLAND_DOWN, OSPM_REG_TYPE))
BUG();
+ spin_unlock_irqrestore(&dev_priv->ospm_lock, flags);
+
#ifdef CONFIG_MDFD_HDMI
/* Turn off MSIC VCC330 and VHDMI if HDMI is disconnected. */
if (!hdmi_state) {
printk(KERN_ALERT "%s other hw_islands: %x\n",
__func__, gfx_islands);
#endif
+ spin_lock_irqsave(&dev_priv->ospm_lock, flags);
if (gfx_islands & OSPM_GL3_CACHE_ISLAND) {
/*
Make sure both GFX & Video aren't
using GL3
*/
if (atomic_read(&g_graphics_access_count) ||
- ospm_power_is_hw_on(OSPM_VIDEO_DEC_ISLAND) ||
- ospm_power_is_hw_on(OSPM_VIDEO_ENC_ISLAND) ||
- (drm_psb_gl3_enable == 0)) {
+ (g_hw_power_status_mask &
+ (OSPM_VIDEO_DEC_ISLAND |
+ OSPM_VIDEO_ENC_ISLAND |
+ OSPM_GRAPHICS_ISLAND)) ||
+ (drm_psb_gl3_enable == 0)) {
#ifdef OSPM_GFX_DPK
printk(KERN_ALERT
"%s GL3 in use - can't turn OFF\n",
__func__);
#endif
-
gfx_islands &= ~OSPM_GL3_CACHE_ISLAND;
- /*restore the mask back*/
- spin_lock_irqsave(&dev_priv->ospm_lock, flags);
- g_hw_power_status_mask |= OSPM_GL3_CACHE_ISLAND;
- spin_unlock_irqrestore(
- &dev_priv->ospm_lock, flags);
if (!gfx_islands)
- return;
+ goto out;
}
}
+
/*
If pmu_nc_set_power_state fails then accessing HW
reg would result in a crash - IERR/Fabric error.
*/
+ g_hw_power_status_mask &= ~gfx_islands;
if (pmu_nc_set_power_state(gfx_islands,
OSPM_ISLAND_DOWN, APM_REG_TYPE))
BUG();
+out:
+ spin_unlock_irqrestore(&dev_priv->ospm_lock, flags);
}
}
/* printk(KERN_ALERT "%s power on video decode\n", __func__); */
deviceID = gui32MRSTMSVDXDeviceID;
#ifdef CONFIG_MDFD_GL3
- ospm_power_island_up(OSPM_VIDEO_DEC_ISLAND);
- ospm_power_island_up(OSPM_GL3_CACHE_ISLAND);
+ ospm_power_island_up(OSPM_GL3_CACHE_ISLAND | OSPM_VIDEO_DEC_ISLAND);
+ if (IS_D0(gpDrmDevice)) {
+ struct drm_psb_private *dev_priv =
+ (struct drm_psb_private *) gpDrmDevice->dev_private;
+ int ret;
+
+ ret = psb_wait_for_register(dev_priv, MSVDX_COMMS_SIGNATURE,
+ MSVDX_COMMS_SIGNATURE_VALUE,
+ 0xffffffff);
+ if (ret)
+ DRM_ERROR("MSVDX: firmware fails to initialize.\n");
+ }
#else
ospm_power_island_up(OSPM_VIDEO_DEC_ISLAND);
#endif
break;
case OSPM_VIDEO_ENC_ISLAND:
- if(!ospm_power_is_hw_on(OSPM_DISPLAY_ISLAND)) {
- /* printk(KERN_ALERT "%s power on display for video encode\n", __func__); */
+ if (IS_MRST(gpDrmDevice) &&
+ (!ospm_power_is_hw_on(
+ OSPM_DISPLAY_ISLAND))) {
deviceID = gui32MRSTDisplayDeviceID;
ospm_resume_display(pdev);
psb_irq_preinstall_islands(gpDrmDevice, OSPM_DISPLAY_ISLAND);
psb_irq_postinstall_islands(gpDrmDevice, OSPM_DISPLAY_ISLAND);
}
- else{
- /* printk(KERN_ALERT "%s display is already on for video encode use\n", __func__); */
- }
if(!ospm_power_is_hw_on(OSPM_VIDEO_ENC_ISLAND)) {
/* printk(KERN_ALERT "%s power on video encode\n", __func__); */
#define PNW_IMR_ADDRESS_MASK 0x00fffffcu
#define PNW_IMR_ADDRESS_SHIFT 8
#define PNW_IMR_MSG_PORT 3
-#define PNW_IMR3L_MSG_REGADDR 0x4C
-#define PNW_IMR3H_MSG_REGADDR 0x4D
+#define PNW_IMR4L_MSG_REGADDR 0x50
+#define PNW_IMR4H_MSG_REGADDR 0x51
#endif
unsigned long irq_flags;
mutex_lock(&msvdx_priv->msvdx_mutex);
- msvdx_priv->msvdx_needs_reset = 1;
+ if (IS_D0(dev_priv->dev))
+ msvdx_priv->msvdx_needs_reset |= MSVDX_RESET_NEEDS_REUPLOAD_FW |
+ MSVDX_RESET_NEEDS_INIT_FW;
+ else
+ msvdx_priv->msvdx_needs_reset = 1;
msvdx_priv->msvdx_current_sequence++;
PSB_DEBUG_GENERAL
("MSVDXFENCE: incremented msvdx_current_sequence to :%d\n",
return ret;
if (arg->engine == PSB_ENGINE_VIDEO) {
+ if (IS_D0(dev))
+ psb_msvdx_check_reset_fw(dev);
if (!ospm_power_using_hw_begin(OSPM_VIDEO_DEC_ISLAND,
OSPM_UHB_FORCE_POWER_ON))
return -EBUSY;
projects / platform / kernel / kernel-mfld-blackbay.git / commitdiff