kMaxBlockTrampolineSectionSize;
internal_trampoline_exception_ = false;
last_bound_pos_ = 0;
+ optimizable_cmpi_pos_ = -1;
trampoline_emitted_ = FLAG_force_long_branches;
unbound_labels_count_ = 0;
ClearRecordedAstId();
void Assembler::cmpwi(Register src1, const Operand& src2, CRegister cr) {
intptr_t imm16 = src2.imm_;
int L = 0;
+ int pos = pc_offset();
DCHECK(is_int16(imm16));
DCHECK(cr.code() >= 0 && cr.code() <= 7);
imm16 &= kImm16Mask;
+
+ // For cmpwi against 0, save postition and cr for later examination
+ // of potential optimization.
+ if (imm16 == 0 && pos > 0 && last_bound_pos_ != pos) {
+ optimizable_cmpi_pos_ = pos;
+ cmpi_cr_ = cr;
+ }
emit(CMPI | cr.code() * B23 | L * B21 | src1.code() * B16 | imm16);
}
// Convenience branch instructions using labels
void b(Label* L, LKBit lk = LeaveLK) { b(branch_offset(L, false), lk); }
+ inline CRegister cmpi_optimization(CRegister cr) {
+ // Check whether the branch is preceeded by an optimizable cmpi against 0.
+ // The cmpi can be deleted if it is also preceeded by an instruction that
+ // sets the register used by the compare and supports a dot form.
+ unsigned int sradi_mask = kOpcodeMask | kExt2OpcodeVariant2Mask;
+ unsigned int srawi_mask = kOpcodeMask | kExt2OpcodeMask;
+ int pos = pc_offset();
+ int cmpi_pos = pc_offset() - kInstrSize;
+
+ if (cmpi_pos > 0 && optimizable_cmpi_pos_ == cmpi_pos &&
+ cmpi_cr_.code() == cr.code() && last_bound_pos_ != pos) {
+ int xpos = cmpi_pos - kInstrSize;
+ int xinstr = instr_at(xpos);
+ int cmpi_ra = (instr_at(cmpi_pos) & 0x1f0000) >> 16;
+ // ra is at the same bit position for the three cases below.
+ int ra = (xinstr & 0x1f0000) >> 16;
+ if (cmpi_ra == ra) {
+ if ((xinstr & sradi_mask) == (EXT2 | SRADIX)) {
+ cr = cr0;
+ instr_at_put(xpos, xinstr | SetRC);
+ pc_ -= kInstrSize;
+ } else if ((xinstr & srawi_mask) == (EXT2 | SRAWIX)) {
+ cr = cr0;
+ instr_at_put(xpos, xinstr | SetRC);
+ pc_ -= kInstrSize;
+ } else if ((xinstr & kOpcodeMask) == ANDIx) {
+ cr = cr0;
+ pc_ -= kInstrSize;
+ // nothing to do here since andi. records.
+ }
+ // didn't match one of the above, must keep cmpwi.
+ }
+ }
+ return cr;
+ }
+
void bc_short(Condition cond, Label* L, CRegister cr = cr7,
LKBit lk = LeaveLK) {
DCHECK(cond != al);
DCHECK(cr.code() >= 0 && cr.code() <= 7);
+ cr = cmpi_optimization(cr);
+
int b_offset = branch_offset(L, false);
switch (cond) {
DCHECK(cond != al);
DCHECK(cr.code() >= 0 && cr.code() <= 7);
+ cr = cmpi_optimization(cr);
+
switch (cond) {
case eq:
isel(rt, ra, rb, encode_crbit(cr, CR_EQ));
// The bound position, before this we cannot do instruction elimination.
int last_bound_pos_;
+ // Optimizable cmpi information.
+ int optimizable_cmpi_pos_;
+ CRegister cmpi_cr_;
ConstantPoolBuilder constant_pool_builder_;
kBOfieldMask = 0x1f << 21,
kOpcodeMask = 0x3f << 26,
kExt1OpcodeMask = 0x3ff << 1,
- kExt2OpcodeMask = 0x1f << 1,
+ kExt2OpcodeMask = 0x3ff << 1,
+ kExt2OpcodeVariant2Mask = 0x1ff << 2,
kExt5OpcodeMask = 0x3 << 2,
kBOMask = 0x1f << 21,
kBIMask = 0x1F << 16,