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arm64: dts: imx8mn-ddr4-evk: Move iomuxc node to end of file
authorAnson Huang <Anson.Huang@nxp.com>
Wed, 9 Oct 2019 02:34:39 +0000 (10:34 +0800)
committerShawn Guo <shawnguo@kernel.org>
Mon, 14 Oct 2019 13:33:27 +0000 (21:33 +0800)
All nodes are better to follow alphabetical sort except iomuxc
which has huge pinctrl data, better to put it at the end of
file.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts patch | blob | history

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index d78d657..1b90faa 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -43,158 +43,6 @@
        cpu-supply = <&buck2_reg>;
 };
 
-&iomuxc {
-       pinctrl-names = "default";
-
-       pinctrl_fec1: fec1grp {
-               fsl,pins = <
-                       MX8MN_IOMUXC_ENET_MDC_ENET1_MDC         0x3
-                       MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
-                       MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
-                       MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
-                       MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
-                       MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
-                       MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
-                       MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
-                       MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
-                       MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
-                       MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
-                       MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
-                       MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
-                       MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
-                       MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
-               >;
-       };
-
-       pinctrl_gpio_led: gpioledgrp {
-               fsl,pins = <
-                       MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16    0x19
-               >;
-       };
-
-       pinctrl_i2c1: i2c1grp {
-               fsl,pins = <
-                       MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
-                       MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
-               >;
-       };
-
-       pinctrl_pmic: pmicirq {
-               fsl,pins = <
-                       MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x41
-               >;
-       };
-
-       pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
-               fsl,pins = <
-                       MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
-               >;
-       };
-
-       pinctrl_uart2: uart2grp {
-               fsl,pins = <
-                       MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
-                       MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
-               >;
-       };
-
-       pinctrl_usdhc2_gpio: usdhc2grpgpio {
-               fsl,pins = <
-                       MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x1c4
-               >;
-       };
-
-       pinctrl_usdhc2: usdhc2grp {
-               fsl,pins = <
-                       MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
-                       MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
-                       MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
-                       MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
-                       MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
-                       MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
-                       MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
-               >;
-       };
-
-       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
-               fsl,pins = <
-                       MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
-                       MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
-                       MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
-                       MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
-                       MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
-                       MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
-                       MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
-               >;
-       };
-
-       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
-               fsl,pins = <
-                       MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
-                       MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
-                       MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
-                       MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
-                       MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
-                       MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
-                       MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
-               >;
-       };
-
-       pinctrl_usdhc3: usdhc3grp {
-               fsl,pins = <
-                       MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000190
-                       MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
-                       MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
-                       MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
-                       MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
-                       MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
-                       MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
-                       MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
-                       MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
-                       MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
-                       MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
-               >;
-       };
-
-       pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
-               fsl,pins = <
-                       MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000194
-                       MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
-                       MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
-                       MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
-                       MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
-                       MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
-                       MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
-                       MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
-                       MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
-                       MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
-                       MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
-               >;
-       };
-
-       pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
-               fsl,pins = <
-                       MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000196
-                       MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
-                       MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
-                       MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
-                       MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
-                       MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
-                       MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
-                       MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
-                       MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
-                       MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
-                       MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
-               >;
-       };
-
-       pinctrl_wdog: wdoggrp {
-               fsl,pins = <
-                       MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
-               >;
-       };
-};
-
 &fec1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_fec1>;
@@ -364,3 +212,155 @@
        fsl,ext-reset-output;
        status = "okay";
 };
+
+&iomuxc {
+       pinctrl-names = "default";
+
+       pinctrl_fec1: fec1grp {
+               fsl,pins = <
+                       MX8MN_IOMUXC_ENET_MDC_ENET1_MDC         0x3
+                       MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
+                       MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
+                       MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
+                       MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
+                       MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
+                       MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
+                       MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
+                       MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
+                       MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
+                       MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
+                       MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
+                       MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
+                       MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
+                       MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
+               >;
+       };
+
+       pinctrl_gpio_led: gpioledgrp {
+               fsl,pins = <
+                       MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16    0x19
+               >;
+       };
+
+       pinctrl_i2c1: i2c1grp {
+               fsl,pins = <
+                       MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
+                       MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
+               >;
+       };
+
+       pinctrl_pmic: pmicirq {
+               fsl,pins = <
+                       MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x41
+               >;
+       };
+
+       pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+               fsl,pins = <
+                       MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
+               >;
+       };
+
+       pinctrl_uart2: uart2grp {
+               fsl,pins = <
+                       MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
+                       MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
+               >;
+       };
+
+       pinctrl_usdhc2_gpio: usdhc2grpgpio {
+               fsl,pins = <
+                       MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x1c4
+               >;
+       };
+
+       pinctrl_usdhc2: usdhc2grp {
+               fsl,pins = <
+                       MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
+                       MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
+                       MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
+                       MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
+                       MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
+                       MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
+                       MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+               >;
+       };
+
+       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+               fsl,pins = <
+                       MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
+                       MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
+                       MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
+                       MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
+                       MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
+                       MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
+                       MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+               >;
+       };
+
+       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+               fsl,pins = <
+                       MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
+                       MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
+                       MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
+                       MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
+                       MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
+                       MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
+                       MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+               >;
+       };
+
+       pinctrl_usdhc3: usdhc3grp {
+               fsl,pins = <
+                       MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000190
+                       MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
+                       MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
+                       MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
+                       MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
+                       MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
+                       MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
+                       MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
+                       MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
+                       MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
+                       MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
+               >;
+       };
+
+       pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+               fsl,pins = <
+                       MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000194
+                       MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
+                       MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
+                       MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
+                       MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
+                       MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
+                       MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
+                       MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
+                       MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
+                       MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
+                       MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
+               >;
+       };
+
+       pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+               fsl,pins = <
+                       MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000196
+                       MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
+                       MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
+                       MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
+                       MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
+                       MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
+                       MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
+                       MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
+                       MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
+                       MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
+                       MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
+               >;
+       };
+
+       pinctrl_wdog: wdoggrp {
+               fsl,pins = <
+                       MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
+               >;
+       };
+};
Domain: System / Kernel;