mtd: add a macro to hide the env region in rsv zone
authorYi Zeng <yi.zeng@amlogic.com>
Mon, 12 Mar 2018 07:38:55 +0000 (15:38 +0800)
committerJianxin Pan <jianxin.pan@amlogic.com>
Sun, 18 Mar 2018 03:08:57 +0000 (19:08 -0800)
PD#160529: mtd: add a macro to hide the env region in rsv zone

when we save the env data in normal partition, the env region
in the rsv zone is no needed anymore, so hide it with a macro.

Change-Id: Id1b92079d1127ffabf4c1f208b486daad0af3934
Signed-off-by: Yi Zeng <yi.zeng@amlogic.com>
drivers/amlogic/mtd/aml_env.c
drivers/amlogic/mtd/aml_mtd.h
drivers/amlogic/mtd/aml_nand.c
drivers/amlogic/mtd/m3_nand.c
drivers/amlogic/mtd/rsv_manage.c

index d468e72..ef700e1 100644 (file)
@@ -21,6 +21,7 @@
 #include<linux/cdev.h>
 #include <linux/device.h>
 
+#ifndef CONFIG_MTD_ENV_IN_NAND
 #define ENV_NAME "nand_env"
 static DEFINE_MUTEX(env_mutex);
 static dev_t uboot_env_no;
@@ -28,6 +29,7 @@ struct cdev uboot_env;
 struct device *uboot_dev;
 struct class *uboot_env_class;
 #endif  /* AML_NAND_UBOOT */
+#endif
 
 struct aml_nand_chip *aml_chip_env;
 
@@ -136,7 +138,7 @@ exit_err:
 
        return ret;
 }
-
+#ifndef CONFIG_MTD_ENV_IN_NAND
 #ifndef AML_NAND_UBOOT
 
 ssize_t env_show(struct class *class, struct class_attribute *attr,
@@ -437,5 +439,5 @@ exit:
        }
        return 0;
 }
-
+#endif
 
index 5dff1a7..a218982 100644 (file)
@@ -63,6 +63,16 @@ extern unsigned char pagelist_hynix256[128];
 #define CONFIG_ENV_SIZE  (64*1024U)
 
 /*
+ * open this macro, the env will store in
+ * normal partition: "environment". and the
+ * env region in reserve zone will be hidden
+ *
+ * please remember add a partition named
+ * "environment" in dts file.
+ * #define CONFIG_MTD_ENV_IN_NAND
+ */
+
+/*
  ** Max page list cnt for usrdef mode
  */
 #define NAND_PAGELIST_CNT 16
index e60ffd4..48d848e 100644 (file)
@@ -2127,7 +2127,9 @@ int aml_nand_init(struct aml_nand_chip *aml_chip)
                pr_info("invalid nand bbt\n");
                goto exit_error;
        }
+#ifndef CONFIG_MTD_ENV_IN_NAND
        aml_nand_env_check(mtd);
+#endif
        aml_nand_key_check(mtd);
        aml_nand_dtb_check(mtd);
 
index 47760c1..7aea511 100644 (file)
@@ -1010,7 +1010,9 @@ static int m3_nand_probe(struct aml_nand_platform *plat, unsigned int dev_num)
 
 #endif
        } else {
+       #ifndef CONFIG_MTD_ENV_IN_NAND
                aml_ubootenv_init(aml_chip);
+       #endif
                aml_key_init(aml_chip);
                amlnf_dtb_init(aml_chip);
        }
index 8ae5cf6..25a9f62 100644 (file)
@@ -802,7 +802,7 @@ int aml_nand_rsv_info_init(struct mtd_info *mtd)
 {
        struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
        struct nand_chip *chip = mtd->priv;
-       unsigned int pages_per_blk_shift, bbt_start_block;
+       unsigned int pages_per_blk_shift, bbt_start_block, vernier;
        int phys_erase_shift, i;
 
        phys_erase_shift = fls(mtd->erasesize) - 1;
@@ -812,6 +812,7 @@ int aml_nand_rsv_info_init(struct mtd_info *mtd)
        bbt_start_block = BOOT_TOTAL_PAGES >> pages_per_blk_shift;
        bbt_start_block += NAND_GAP_BLOCK_NUM; /*gap occupy 4 blocks*/
 
+       vernier = bbt_start_block;
        aml_chip->rsv_data_buf = kzalloc(mtd->writesize, GFP_KERNEL);
        if (aml_chip->rsv_data_buf == NULL)
                return -ENOMEM;
@@ -836,9 +837,10 @@ int aml_nand_rsv_info_init(struct mtd_info *mtd)
                return -ENOMEM;
 
        aml_chip->aml_nandbbt_info->valid_node->phy_blk_addr = -1;
-       aml_chip->aml_nandbbt_info->start_block = bbt_start_block;
+       aml_chip->aml_nandbbt_info->start_block = vernier;
        aml_chip->aml_nandbbt_info->end_block =
-               aml_chip->aml_nandbbt_info->start_block + NAND_BBT_BLOCK_NUM;
+               vernier + NAND_BBT_BLOCK_NUM;
+       vernier += NAND_BBT_BLOCK_NUM;
        aml_chip->aml_nandbbt_info->size = mtd->size >> phys_erase_shift;
        memcpy(aml_chip->aml_nandbbt_info->name, BBT_NAND_MAGIC, 4);
 
@@ -850,7 +852,7 @@ int aml_nand_rsv_info_init(struct mtd_info *mtd)
                return -ENOMEM;
        }
        memset(aml_chip->block_status, 0, (mtd->size >> phys_erase_shift));
-
+#ifndef CONFIG_MTD_ENV_IN_NAND
        /*env info init*/
        aml_chip->aml_nandenv_info =
                kzalloc(sizeof(struct aml_nandrsv_info_t), GFP_KERNEL);
@@ -864,13 +866,13 @@ int aml_nand_rsv_info_init(struct mtd_info *mtd)
                return -ENOMEM;
 
        aml_chip->aml_nandenv_info->valid_node->phy_blk_addr = -1;
-       aml_chip->aml_nandenv_info->start_block =
-               aml_chip->aml_nandbbt_info->end_block;
+       aml_chip->aml_nandenv_info->start_block = vernier;
        aml_chip->aml_nandenv_info->end_block =
-               aml_chip->aml_nandbbt_info->end_block + NAND_ENV_BLOCK_NUM;
+               vernier + NAND_ENV_BLOCK_NUM;
+       vernier += NAND_ENV_BLOCK_NUM;
        aml_chip->aml_nandenv_info->size = CONFIG_ENV_SIZE;
        memcpy(aml_chip->aml_nandenv_info->name, ENV_NAND_MAGIC, 4);
-
+#endif
        aml_chip->aml_nandkey_info =
                kzalloc(sizeof(struct aml_nandrsv_info_t), GFP_KERNEL);
        if (aml_chip->aml_nandkey_info == NULL)
@@ -884,10 +886,10 @@ int aml_nand_rsv_info_init(struct mtd_info *mtd)
                return -ENOMEM;
 
        aml_chip->aml_nandkey_info->valid_node->phy_blk_addr = -1;
-       aml_chip->aml_nandkey_info->start_block =
-               aml_chip->aml_nandenv_info->end_block;
+       aml_chip->aml_nandkey_info->start_block = vernier;
        aml_chip->aml_nandkey_info->end_block =
-               aml_chip->aml_nandenv_info->end_block + NAND_KEY_BLOCK_NUM;
+               vernier + NAND_KEY_BLOCK_NUM;
+       vernier += NAND_KEY_BLOCK_NUM;
        aml_chip->aml_nandkey_info->size = aml_chip->keysize;
        memcpy(aml_chip->aml_nandkey_info->name, KEY_NAND_MAGIC, 4);
 
@@ -904,18 +906,28 @@ int aml_nand_rsv_info_init(struct mtd_info *mtd)
                return -ENOMEM;
 
        aml_chip->aml_nanddtb_info->valid_node->phy_blk_addr = -1;
-       aml_chip->aml_nanddtb_info->start_block =
-               aml_chip->aml_nandkey_info->end_block;
+       aml_chip->aml_nanddtb_info->start_block = vernier;
        aml_chip->aml_nanddtb_info->end_block =
-               aml_chip->aml_nandkey_info->end_block + NAND_DTB_BLOCK_NUM;
+               vernier + NAND_DTB_BLOCK_NUM;
+       vernier += NAND_DTB_BLOCK_NUM;
        aml_chip->aml_nanddtb_info->size = aml_chip->dtbsize;
        memcpy(aml_chip->aml_nanddtb_info->name, DTB_NAND_MAGIC, 4);
 
-       pr_info("bbt_start=%d env_start=%d key_start=%d dtb_start=%d\n",
-               aml_chip->aml_nandbbt_info->start_block,
-               aml_chip->aml_nandenv_info->start_block,
-               aml_chip->aml_nandkey_info->start_block,
-               aml_chip->aml_nanddtb_info->start_block);
+       if ((vernier - (BOOT_TOTAL_PAGES >> pages_per_blk_shift)) >
+           RESERVED_BLOCK_NUM) {
+               pr_info("ERROR: total blk number is over the limit\n");
+               return -ENOMEM;
+               }
+               pr_info("bbt_start=%d\n",
+                               aml_chip->aml_nandbbt_info->start_block);
+#ifndef CONFIG_MTD_ENV_IN_NAND
+               pr_info("env_start=%d\n",
+                               aml_chip->aml_nandenv_info->start_block);
+#endif
+               pr_info("key_start=%d\n",
+                               aml_chip->aml_nandkey_info->start_block);
+               pr_info("dtb_start=%d\n",
+                               aml_chip->aml_nanddtb_info->start_block);
 
        return 0;
 }