arm64/sysreg: Standardise naming for ID_AA64MMFR2_EL1.CnP

The kernel refers to ID_AA64MMFR2_EL1.CnP as CNP. In preparation for
automatic generation of defines for the system registers bring the naming
used by the kernel in sync with that of DDI0487H.a. No functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-13-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index c80f1f7..7795a04 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -819,7 +819,7 @@
 #define ID_AA64MMFR2_EL1_IESB_SHIFT    12
 #define ID_AA64MMFR2_EL1_LSM_SHIFT     8
 #define ID_AA64MMFR2_EL1_UAO_SHIFT     4
-#define ID_AA64MMFR2_EL1_CNP_SHIFT     0
+#define ID_AA64MMFR2_EL1_CnP_SHIFT     0
 
 /* id_aa64dfr0 */
 #define ID_AA64DFR0_MTPMU_SHIFT                48

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index f927b44..2de9b28 100644 (file)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -392,7 +392,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
        ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0),
        ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0),
        ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CNP_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
@@ -2380,7 +2380,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
                .matches = has_useable_cnp,
                .sys_reg = SYS_ID_AA64MMFR2_EL1,
                .sign = FTR_UNSIGNED,
-               .field_pos = ID_AA64MMFR2_EL1_CNP_SHIFT,
+               .field_pos = ID_AA64MMFR2_EL1_CnP_SHIFT,
                .field_width = 4,
                .min_field_value = 1,
                .cpu_enable = cpu_enable_cnp,

diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
index 1653299..0ba290e 100644 (file)
--- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
@@ -120,7 +120,7 @@
  * - E0PDx mechanism
  */
 #define PVM_ID_AA64MMFR2_ALLOW (\
-       ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_CNP) | \
+       ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_CnP) | \
        ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_UAO) | \
        ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_IESB) | \
        ARM64_FEATURE_MASK(ID_AA64MMFR2_EL1_AT) | \