#define ARM64_HARDEN_BRANCH_PREDICTOR 24
#define ARM64_HARDEN_BP_POST_GUEST_EXIT 25
#define ARM64_HAS_RAS_EXTN 26
+#define ARM64_WORKAROUND_843419 27
-#define ARM64_NCAPS 27
+#define ARM64_NCAPS 28
#endif /* __ASM_CPUCAPS_H */
MIDR_CPU_VAR_REV(1, 2)),
},
#endif
+#ifdef CONFIG_ARM64_ERRATUM_843419
+ {
+ /* Cortex-A53 r0p[01234] */
+ .desc = "ARM erratum 843419",
+ .capability = ARM64_WORKAROUND_843419,
+ MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
+ MIDR_FIXED(0x4, BIT(8)),
+ },
+#endif
#ifdef CONFIG_ARM64_ERRATUM_845719
{
/* Cortex-A53 r0p[01234] */
break;
case R_AARCH64_ADR_PREL_PG_HI21_NC:
case R_AARCH64_ADR_PREL_PG_HI21:
- if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419))
+ if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) ||
+ !cpus_have_const_cap(ARM64_WORKAROUND_843419))
break;
/*
u32 insn;
if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) ||
+ !cpus_have_const_cap(ARM64_WORKAROUND_843419) ||
((u64)place & 0xfff) < 0xff8)
return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21,
AARCH64_INSN_IMM_ADR);