* config/frv/frv.h (enum reg_class): Delete EVEN_ACC_REGS,

	ACC_REGS, FEVEN_REGS, FPR_REGS, EVEN_REGS.
	(REG_CLASS_NAMES): Likewise.
	(REG_CLASS_CONTENTS): Likewise.
	(EVEN_ACC_REGS): New macro.  Alias for QUAD_ACC_REGS.
	(ACC_REGS): New macro.  Alias for QUAD_ACC_REGS.
	(FEVEN_REGS): New macro.  Alias for QUAD_ACC_REGS.
	(FPR_REGS): New macro.  Alias for QUAD_ACC_REGS.
	(EVEN_REGS): New macro.  Alias for QUAD_REGS.
	* config/frv/frv.c (frv_secondary_reload_class): Remove use of
	duplicate register classes.
	(frv_class_likely_spileld_p): Likewise.
	(frv_register_move_cost): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@173016 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9c06f8b..d3b78bf 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,19 @@
 2011-04-27  Nick Clifton  <nickc@redhat.com>
 
+       * config/frv/frv.h (enum reg_class): Delete EVEN_ACC_REGS,
+       ACC_REGS, FEVEN_REGS, FPR_REGS, EVEN_REGS.
+       (REG_CLASS_NAMES): Likewise.
+       (REG_CLASS_CONTENTS): Likewise.
+       (EVEN_ACC_REGS): New macro.  Alias for QUAD_ACC_REGS.
+       (ACC_REGS): New macro.  Alias for QUAD_ACC_REGS.
+       (FEVEN_REGS): New macro.  Alias for QUAD_ACC_REGS.
+       (FPR_REGS): New macro.  Alias for QUAD_ACC_REGS.
+       (EVEN_REGS): New macro.  Alias for QUAD_REGS.
+       * config/frv/frv.c (frv_secondary_reload_class): Remove use of
+       duplicate register classes.
+       (frv_class_likely_spileld_p): Likewise.
+       (frv_register_move_cost): Likewise.
+
        * config/mcore/mcore.h (REGNO_REG_CLASS): Do not index beyond the
        end of the regno_reg_class array.
 

diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index ddd3fa0..c16a905 100644 (file)
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -6371,7 +6371,6 @@ frv_secondary_reload_class (enum reg_class rclass,
       /* Accumulators/Accumulator guard registers need to go through floating
          point registers.  */
     case QUAD_REGS:
-    case EVEN_REGS:
     case GPR_REGS:
       ret = NO_REGS;
       if (x && GET_CODE (x) == REG)
@@ -6385,8 +6384,6 @@ frv_secondary_reload_class (enum reg_class rclass,
 
       /* Nonzero constants should be loaded into an FPR through a GPR.  */
     case QUAD_FPR_REGS:
-    case FEVEN_REGS:
-    case FPR_REGS:
       if (x && CONSTANT_P (x) && !ZERO_P (x))
        ret = GPR_REGS;
       else
@@ -6406,8 +6403,6 @@ frv_secondary_reload_class (enum reg_class rclass,
       break;
 
       /* The accumulators need fpr registers.  */
-    case ACC_REGS:
-    case EVEN_ACC_REGS:
     case QUAD_ACC_REGS:
     case ACCG_REGS:
       ret = FPR_REGS;
@@ -6481,8 +6476,6 @@ frv_class_likely_spilled_p (reg_class_t rclass)
     case LR_REG:
     case SPR_REGS:
     case QUAD_ACC_REGS:
-    case EVEN_ACC_REGS:
-    case ACC_REGS:
     case ACCG_REGS:
       return true;
     }
@@ -6842,19 +6835,16 @@ frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
       break;
 
     case QUAD_REGS:
-    case EVEN_REGS:
     case GPR_REGS:
       switch (to)
        {
        default:
          break;
 
-       case QUAD_REGS:
-       case EVEN_REGS:
+       case QUAD_REGS: 
        case GPR_REGS:
          return LOW_COST;
 
-       case FEVEN_REGS:
        case FPR_REGS:
          return LOW_COST;
 
@@ -6864,24 +6854,19 @@ frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
          return LOW_COST;
        }
 
-    case FEVEN_REGS:
-    case FPR_REGS:
+    case QUAD_FPR_REGS:
       switch (to)
        {
        default:
          break;
 
        case QUAD_REGS:
-       case EVEN_REGS:
        case GPR_REGS:
-       case ACC_REGS:
-       case EVEN_ACC_REGS:
        case QUAD_ACC_REGS:
        case ACCG_REGS:
          return MEDIUM_COST;
 
-       case FEVEN_REGS:
-       case FPR_REGS:
+       case QUAD_FPR_REGS:
          return LOW_COST;
        }
 
@@ -6894,13 +6879,10 @@ frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
          break;
 
        case QUAD_REGS:
-       case EVEN_REGS:
        case GPR_REGS:
          return MEDIUM_COST;
        }
 
-    case ACC_REGS:
-    case EVEN_ACC_REGS:
     case QUAD_ACC_REGS:
     case ACCG_REGS:
       switch (to)
@@ -6908,8 +6890,7 @@ frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
        default:
          break;
 
-       case FEVEN_REGS:
-       case FPR_REGS:
+       case QUAD_FPR_REGS:
          return MEDIUM_COST;
 
        }

diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h
index 0255951..e103dd7 100644 (file)
--- a/gcc/config/frv/frv.h
+++ b/gcc/config/frv/frv.h
@@ -864,14 +864,9 @@ enum reg_class
   FDPIC_CALL_REGS,
   SPR_REGS,
   QUAD_ACC_REGS,
-  EVEN_ACC_REGS,
-  ACC_REGS,
   ACCG_REGS,
   QUAD_FPR_REGS,
-  FEVEN_REGS,
-  FPR_REGS,
   QUAD_REGS,
-  EVEN_REGS,
   GPR_REGS,
   ALL_REGS,
   LIM_REG_CLASSES
@@ -904,14 +899,9 @@ enum reg_class
    "FDPIC_CALL_REGS",                                                  \
    "SPR_REGS",                                                         \
    "QUAD_ACC_REGS",                                                    \
-   "EVEN_ACC_REGS",                                                    \
-   "ACC_REGS",                                                         \
    "ACCG_REGS",                                                                \
    "QUAD_FPR_REGS",                                                    \
-   "FEVEN_REGS",                                                       \
-   "FPR_REGS",                                                         \
    "QUAD_REGS",                                                                \
-   "EVEN_REGS",                                                                \
    "GPR_REGS",                                                         \
    "ALL_REGS"                                                          \
 }
@@ -945,18 +935,19 @@ enum reg_class
   { 0x0000c000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_CALL_REGS */\
   { 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x1e00}, /* SPR_REGS */\
   { 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* QUAD_ACC */\
-  { 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* EVEN_ACC */\
-  { 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* ACC_REGS */\
   { 0x00000000,0x00000000,0x00000000,0x00000000,0xf0000000,0xff}, /* ACCG_REGS*/\
   { 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* QUAD_FPR */\
-  { 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* FEVEN_REG*/\
-  { 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* FPR_REGS */\
   { 0x0ffffffc,0xffffffff,0x00000000,0x00000000,0x00000000,0x0}, /* QUAD_REGS*/\
-  { 0xfffffffc,0xffffffff,0x00000000,0x00000000,0x00000000,0x0}, /* EVEN_REGS*/\
   { 0xffffffff,0xffffffff,0x00000000,0x00000000,0x00000000,0x100}, /* GPR_REGS */\
   { 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0x1fff}, /* ALL_REGS */\
 }
 
+#define EVEN_ACC_REGS   QUAD_ACC_REGS
+#define ACC_REGS        QUAD_ACC_REGS
+#define FEVEN_REGS      QUAD_FPR_REGS
+#define FPR_REGS        QUAD_FPR_REGS
+#define EVEN_REGS       QUAD_REGS
+
 /* A C expression whose value is a register class containing hard register
    REGNO.  In general there is more than one such class; choose a class which
    is "minimal", meaning that no smaller class also contains the register.  */