drm/radeon/si: enable DMA pg by default

Enable DMA powergating by default.  The DMA engines
will be powergated when not in use.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 3bd96cd..78e9bbc 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -2389,9 +2389,9 @@ int radeon_asic_init(struct radeon_device *rdev)
                                RADEON_CG_SUPPORT_UVD_MGCG |
                                RADEON_CG_SUPPORT_HDP_LS |
                                RADEON_CG_SUPPORT_HDP_MGCG;
-                       rdev->pg_flags = 0;
-                                       /*RADEON_PG_SUPPORT_GFX_CG |
-                                         RADEON_PG_SUPPORT_SDMA;*/
+                       rdev->pg_flags = 0 |
+                               /*RADEON_PG_SUPPORT_GFX_CG | */
+                               RADEON_PG_SUPPORT_SDMA;
                        break;
                case CHIP_OLAND:
                        rdev->cg_flags =

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index ebe04e4..d5f77eb 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -5279,13 +5279,6 @@ static void si_fini_cg(struct radeon_device *rdev)
                            RADEON_CG_BLOCK_HDP), false);
 }
 
-void si_update_pg(struct radeon_device *rdev,
-                 bool enable)
-{
-       si_enable_dma_pg(rdev, enable);
-       si_enable_gfx_cgpg(rdev, enable);
-}
-
 u32 si_get_csb_size(struct radeon_device *rdev)
 {
        u32 count = 0;
@@ -5387,7 +5380,8 @@ static void si_init_pg(struct radeon_device *rdev)
                if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG) {
                        si_init_gfx_cgpg(rdev);
                }
-               si_update_pg(rdev, false);
+               si_enable_dma_pg(rdev, true);
+               si_enable_gfx_cgpg(rdev, true);
        } else {
                WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
                WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8);
@@ -5397,10 +5391,8 @@ static void si_init_pg(struct radeon_device *rdev)
 static void si_fini_pg(struct radeon_device *rdev)
 {
        if (rdev->pg_flags) {
-               if (rdev->pg_flags & RADEON_PG_SUPPORT_SDMA)
-                       si_enable_dma_pg(rdev, false);
-               if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_CG)
-                       si_enable_gfx_cgpg(rdev, false);
+               si_enable_dma_pg(rdev, false);
+               si_enable_gfx_cgpg(rdev, false);
        }
 }