drm/amd/pm: add the fine grain tuning function for renoir

This patch is to add the fine grain tuning function for renoir.
This function uses the pp_od_clk_voltage sysfs file to configure the min
and max value of gfx clock frequency manually or restore the default value.

Command guide:
echo "s level value" > pp_od_clk_voltage
        "s" - set the sclk frequency
        "level" - 0 or 1, "0" represents the min value,  "1" represents
        the max value
        "value" - the target value of sclk frequency, it should
        be limited in the safe range
echo "r" > pp_od_clk_voltage
        "r" - reset the sclk frequency, restore the default value instantly
echo "c" > pp_od_clk_voltage
        "c" - commit the min and max value of sclk frequency to the system
        only after the commit command, the target values set by "s" command
        will take effect.
Example:
1)change power profile from "auto" to "standard"
        $ cat power_dpm_force_performance_level
        auto
        $ echo "profile_standard" > power_dpm_force_performance_level
        $ cat power_dpm_force_performance_level
        profile_standard
2)check the default sclk frequency
        $ cat pp_od_clk_voltage
        OD_SCLK:
        0:        200Mhz
        1:       1400Mhz
        OD_RANGE:
        SCLK:     200MHz       1400MHz
3)use "s" -- set command to configure the min and max sclk frequency
        $ echo "s 0 600" > pp_od_clk_voltage
        $ echo "s 1 1000" > pp_od_clk_voltage
        $ echo "c" > pp_od_clk_voltage
        $ cat pp_od_clk_voltage
        OD_SCLK:
        0:        600Mhz
        1:       1000Mhz
        OD_RANGE:
        SCLK:     200MHz       1400MHz
4)use "r" -- reset command to restore the min or max sclk frequency
        $ echo "r" > pp_od_clk_voltage
        $ cat pp_od_clk_voltage
        OD_SCLK:
        0:        200Mhz
        1:       1400Mhz
        OD_RANGE:
        SCLK:     200MHz       1400MHz

Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
index dc75db8..801e785 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c
@@ -343,6 +343,129 @@ failed:
        return ret;
 }
 
+static int renoir_od_edit_dpm_table(struct smu_context *smu,
+                                                       enum PP_OD_DPM_TABLE_COMMAND type,
+                                                       long input[], uint32_t size)
+{
+       int ret = 0;
+
+       if (!smu->od_enabled) {
+               dev_warn(smu->adev->dev, "Fine grain is not enabled!\n");
+               return -EINVAL;
+       }
+
+       switch (type) {
+       case PP_OD_EDIT_SCLK_VDDC_TABLE:
+               if (size != 2) {
+                       dev_err(smu->adev->dev, "Input parameter number not correct\n");
+                       return -EINVAL;
+               }
+
+               if (input[0] == 0) {
+                       if (input[1] < smu->gfx_default_hard_min_freq) {
+                               dev_warn(smu->adev->dev, "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
+                                       input[1], smu->gfx_default_hard_min_freq);
+                               return -EINVAL;
+                       }
+                       smu->gfx_actual_hard_min_freq = input[1];
+               } else if (input[0] == 1) {
+                       if (input[1] > smu->gfx_default_soft_max_freq) {
+                               dev_warn(smu->adev->dev, "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
+                                       input[1], smu->gfx_default_soft_max_freq);
+                               return -EINVAL;
+                       }
+                       smu->gfx_actual_soft_max_freq = input[1];
+               } else {
+                       return -EINVAL;
+               }
+               break;
+       case PP_OD_RESTORE_DEFAULT_TABLE:
+               if (size != 0) {
+                       dev_err(smu->adev->dev, "Input parameter number not correct\n");
+                       return -EINVAL;
+               }
+               smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
+               smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
+
+               ret = smu_cmn_send_smc_msg_with_param(smu,
+                                                               SMU_MSG_SetHardMinGfxClk,
+                                                               smu->gfx_actual_hard_min_freq,
+                                                               NULL);
+               if (ret) {
+                       dev_err(smu->adev->dev, "Restore the default hard min sclk failed!");
+                       return ret;
+               }
+
+               ret = smu_cmn_send_smc_msg_with_param(smu,
+                                                               SMU_MSG_SetSoftMaxGfxClk,
+                                                               smu->gfx_actual_soft_max_freq,
+                                                               NULL);
+               if (ret) {
+                       dev_err(smu->adev->dev, "Restore the default soft max sclk failed!");
+                       return ret;
+               }
+               break;
+       case PP_OD_COMMIT_DPM_TABLE:
+               if (size != 0) {
+                       dev_err(smu->adev->dev, "Input parameter number not correct\n");
+                       return -EINVAL;
+               } else {
+                       if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
+                               dev_err(smu->adev->dev, "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
+                               smu->gfx_actual_hard_min_freq, smu->gfx_actual_soft_max_freq);
+                               return -EINVAL;
+                       }
+
+                       ret = smu_cmn_send_smc_msg_with_param(smu,
+                                                               SMU_MSG_SetHardMinGfxClk,
+                                                               smu->gfx_actual_hard_min_freq,
+                                                               NULL);
+                       if (ret) {
+                               dev_err(smu->adev->dev, "Set hard min sclk failed!");
+                               return ret;
+                       }
+
+                       ret = smu_cmn_send_smc_msg_with_param(smu,
+                                                               SMU_MSG_SetSoftMaxGfxClk,
+                                                               smu->gfx_actual_soft_max_freq,
+                                                               NULL);
+                       if (ret) {
+                               dev_err(smu->adev->dev, "Set soft max sclk failed!");
+                               return ret;
+                       }
+               }
+               break;
+       default:
+               return -ENOSYS;
+       }
+
+       return ret;
+}
+
+static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
+{
+       uint32_t min = 0, max = 0;
+       uint32_t ret = 0;
+
+       ret = smu_cmn_send_smc_msg_with_param(smu,
+                                                               SMU_MSG_GetMinGfxclkFrequency,
+                                                               0, &min);
+       if (ret)
+               return ret;
+       ret = smu_cmn_send_smc_msg_with_param(smu,
+                                                               SMU_MSG_GetMaxGfxclkFrequency,
+                                                               0, &max);
+       if (ret)
+               return ret;
+
+       smu->gfx_default_hard_min_freq = min;
+       smu->gfx_default_soft_max_freq = max;
+       smu->gfx_actual_hard_min_freq = 0;
+       smu->gfx_actual_soft_max_freq = 0;
+
+       return 0;
+}
+
 static int renoir_print_clk_levels(struct smu_context *smu,
                        enum smu_clk_type clk_type, char *buf)
 {
@@ -358,6 +481,28 @@ static int renoir_print_clk_levels(struct smu_context *smu,
                return ret;
 
        switch (clk_type) {
+       case SMU_OD_RANGE:
+               if (smu->od_enabled) {
+                       ret = smu_cmn_send_smc_msg_with_param(smu,
+                                               SMU_MSG_GetMinGfxclkFrequency,
+                                               0, &min);
+                       if (ret)
+                               return ret;
+                       ret = smu_cmn_send_smc_msg_with_param(smu,
+                                               SMU_MSG_GetMaxGfxclkFrequency,
+                                               0, &max);
+                       if (ret)
+                               return ret;
+                       size += sprintf(buf + size, "OD_RANGE\nSCLK: %10uMhz %10uMhz\n", min, max);
+               }
+               break;
+       case SMU_OD_SCLK:
+                       min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
+                       max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
+                       size += sprintf(buf + size, "OD_SCLK\n");
+                       size += sprintf(buf + size, "0:%10uMhz\n", min);
+                       size += sprintf(buf + size, "1:%10uMhz\n", max);
+               break;
        case SMU_GFXCLK:
        case SMU_SCLK:
                /* retirve table returned paramters unit is MHz */
@@ -398,23 +543,35 @@ static int renoir_print_clk_levels(struct smu_context *smu,
                cur_value = metrics.ClockFrequency[CLOCK_FCLK];
                break;
        default:
-               return -EINVAL;
+               break;
        }
 
-       for (i = 0; i < count; i++) {
-               ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value);
-               if (ret)
-                       return ret;
-               if (!value)
-                       continue;
-               size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
-                               cur_value == value ? "*" : "");
-               if (cur_value == value)
-                       cur_value_match_level = true;
-       }
+       switch (clk_type) {
+       case SMU_GFXCLK:
+       case SMU_SCLK:
+       case SMU_SOCCLK:
+       case SMU_MCLK:
+       case SMU_DCEFCLK:
+       case SMU_FCLK:
+               for (i = 0; i < count; i++) {
+                       ret = renoir_get_dpm_clk_limited(smu, clk_type, i, &value);
+                       if (ret)
+                               return ret;
+                       if (!value)
+                               continue;
+                       size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
+                                       cur_value == value ? "*" : "");
+                       if (cur_value == value)
+                               cur_value_match_level = true;
+               }
 
-       if (!cur_value_match_level)
-               size += sprintf(buf + size, "   %uMhz *\n", cur_value);
+               if (!cur_value_match_level)
+                       size += sprintf(buf + size, "   %uMhz *\n", cur_value);
+
+               break;
+       default:
+               break;
+       }
 
        return size;
 }
@@ -1159,6 +1316,8 @@ static const struct pptable_funcs renoir_ppt_funcs = {
        .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
        .get_gpu_metrics = renoir_get_gpu_metrics,
        .gfx_state_change_set = renoir_gfx_state_change_set,
+       .set_fine_grain_gfx_freq_parameters = renoir_set_fine_grain_gfx_freq_parameters,
+       .od_edit_dpm_table = renoir_od_edit_dpm_table,
 };
 
 void renoir_set_ppt_funcs(struct smu_context *smu)