Merge branches 'features/assorted', 'features/imx-pata' and 'features/imx-multi-irq...

Conflicts:
	arch/arm/plat-mxc/avic.c
	arch/arm/plat-mxc/include/mach/common.h

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

diff --cc arch/arm/mach-imx/Kconfig
Simple merge

diff --cc arch/arm/mach-imx/mach-mx25_3ds.c
Simple merge

diff --cc arch/arm/mach-imx/mach-mx31moboard.c
Simple merge

diff --cc arch/arm/mach-imx/mach-qong.c
Simple merge

diff --cc arch/arm/mach-mx5/board-mx51_efikamx.c
Simple merge

diff --cc arch/arm/mach-mx5/board-mx51_efikasb.c
Simple merge

diff --cc arch/arm/mach-mx5/board-mx53_loco.c
Simple merge

diff --cc arch/arm/mach-mx5/mx51_efika.c
Simple merge

diff --cc arch/arm/plat-mxc/avic.c
index 55d2534,846636a,55d2534,4d68c5a..8875fb4
--- 1/arch/arm/plat-mxc/avic.c
--- 2/arch/arm/plat-mxc/avic.c
--- 3/arch/arm/plat-mxc/avic.c
--- 4/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@@@@ -90,24 -92,8 -90,24 -90,24 +92,8 @@@@@ static int avic_set_irq_fiq(unsigned in
    }
    #endif /* CONFIG_FIQ */
    
- --/* Disable interrupt number "irq" in the AVIC */
- --static void mxc_mask_irq(struct irq_data *d)
- --{
- --    __raw_writel(d->irq, avic_base + AVIC_INTDISNUM);
   -}
   -
   -/* Enable interrupt number "irq" in the AVIC */
   -static void mxc_unmask_irq(struct irq_data *d)
   -{
   -    __raw_writel(d->irq, avic_base + AVIC_INTENNUM);
- --}
    
- - /* Enable interrupt number "irq" in the AVIC */
- - static void mxc_unmask_irq(struct irq_data *d)
- - {
- -     __raw_writel(d->irq, avic_base + AVIC_INTENNUM);
- - }
- - 
- --static struct mxc_irq_chip mxc_avic_chip = {
- --    .base = {
- --            .irq_ack = mxc_mask_irq,
- --            .irq_mask = mxc_mask_irq,
- --            .irq_unmask = mxc_unmask_irq,
- --    },
+ ++static struct mxc_extra_irq avic_extra_irq = {
    #ifdef CONFIG_MXC_IRQ_PRIOR
        .set_priority = avic_irq_set_priority,
    #endif
@@@@@ -116,6 -102,56 -116,6 -116,19 +102,68 @@@@@
    #endif
    };
    
 -  
+ ++#ifdef CONFIG_PM
+ ++static void avic_irq_suspend(struct irq_data *d)
+ ++{
+ ++    struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ ++    struct irq_chip_type *ct = gc->chip_types;
+ ++    int idx = gc->irq_base >> 5;
+ ++
+ ++    avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
+ ++    __raw_writel(gc->wake_active, avic_base + ct->regs.mask);
+ ++}
+ ++
+ ++static void avic_irq_resume(struct irq_data *d)
+ ++{
+ ++    struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ ++    struct irq_chip_type *ct = gc->chip_types;
+ ++    int idx = gc->irq_base >> 5;
+ ++
+ ++    __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
+ ++}
+ ++
+ ++#else
+ ++#define avic_irq_suspend NULL
+ ++#define avic_irq_resume NULL
+ ++#endif
+ ++
+ ++static __init void avic_init_gc(unsigned int irq_start)
+ ++{
+ ++    struct irq_chip_generic *gc;
+ ++    struct irq_chip_type *ct;
+ ++    int idx = irq_start >> 5;
+ ++
+ ++    gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
+ ++                                handle_level_irq);
+ ++    gc->private = &avic_extra_irq;
+ ++    gc->wake_enabled = IRQ_MSK(32);
+ ++
+ ++    ct = gc->chip_types;
+ ++    ct->chip.irq_mask = irq_gc_mask_clr_bit;
+ ++    ct->chip.irq_unmask = irq_gc_mask_set_bit;
+ ++    ct->chip.irq_ack = irq_gc_mask_clr_bit;
+ ++    ct->chip.irq_set_wake = irq_gc_set_wake;
+ ++    ct->chip.irq_suspend = avic_irq_suspend;
+ ++    ct->chip.irq_resume = avic_irq_resume;
+ ++    ct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;
+ ++    ct->regs.ack = ct->regs.mask;
+ ++
+ ++    irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
+ ++}
+ ++
+++ asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
+++ {
+++     u32 nivector;
+++ 
+++     do {
+++             nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
+++             if (nivector == 0xffff)
+++                     break;
+++ 
+++             handle_IRQ(nivector, regs);
+++     } while (1);
+++ }
+++ 
    /*
     * This function initializes the AVIC hardware and disables all the
     * interrupts. It registers the interrupt enable and disable functions

diff --cc arch/arm/plat-mxc/include/mach/common.h
index 318e0da,4e3d978,4e3d978,893ec91..5bee446
--- 1/arch/arm/plat-mxc/include/mach/common.h
--- 2/arch/arm/plat-mxc/include/mach/common.h
--- 3/arch/arm/plat-mxc/include/mach/common.h
--- 4/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@@@@ -72,5 -72,4 -72,4 -72,18 +72,19 @@@@@ extern void mxc_arch_reset_init(void __
    extern void mx51_efikamx_reset(void);
    extern int mx53_revision(void);
    extern int mx53_display_revision(void);
 +++extern void imx_print_silicon_rev(const char *cpu, int srev);
+++ 
+++ void avic_handle_irq(struct pt_regs *);
+++ void tzic_handle_irq(struct pt_regs *);
+++ 
+++ #define imx1_handle_irq avic_handle_irq
+++ #define imx21_handle_irq avic_handle_irq
+++ #define imx25_handle_irq avic_handle_irq
+++ #define imx27_handle_irq avic_handle_irq
+++ #define imx31_handle_irq avic_handle_irq
+++ #define imx35_handle_irq avic_handle_irq
+++ #define imx50_handle_irq tzic_handle_irq
+++ #define imx51_handle_irq tzic_handle_irq
+++ #define imx53_handle_irq tzic_handle_irq
+++ 
    #endif

diff --cc arch/arm/plat-mxc/include/mach/mx25.h
Simple merge

diff --cc arch/arm/plat-mxc/tzic.c
Simple merge