arm64: zynqmp: Remove clock-names from GEM in zynqmp-clk-ccf.dtsi
authorMichal Simek <michal.simek@xilinx.com>
Thu, 18 Nov 2021 12:42:28 +0000 (13:42 +0100)
committerMichal Simek <michal.simek@xilinx.com>
Wed, 5 Jan 2022 09:22:02 +0000 (10:22 +0100)
Remove clock-names from GEM nodes from clk-ccf because they should be only
present in zynqmp.dtsi. And as is visible both clock-names defined didn't
really match.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/d6045d81b3e7e97df0ba3eeacb9f3f75ed7cff18.1637239345.git.michal.simek@xilinx.com
arch/arm/dts/zynqmp-clk-ccf.dtsi
arch/arm/dts/zynqmp.dtsi

index b27b0aa..664e658 100644 (file)
        clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
                 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
                 <&zynqmp_clk GEM_TSU>;
-       clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gem1 {
        clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
                 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
                 <&zynqmp_clk GEM_TSU>;
-       clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gem2 {
        clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
                 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
                 <&zynqmp_clk GEM_TSU>;
-       clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gem3 {
        clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
                 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
                 <&zynqmp_clk GEM_TSU>;
-       clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
 };
 
 &gpio {
index 2264a80..015a582 100644 (file)
                        interrupt-parent = <&gic>;
                        interrupts = <0 57 4>, <0 57 4>;
                        reg = <0x0 0xff0b0000 0x0 0x1000>;
-                       clock-names = "pclk", "hclk", "tx_clk";
+                       clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        #stream-id-cells = <1>;
                        interrupt-parent = <&gic>;
                        interrupts = <0 59 4>, <0 59 4>;
                        reg = <0x0 0xff0c0000 0x0 0x1000>;
-                       clock-names = "pclk", "hclk", "tx_clk";
+                       clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        #stream-id-cells = <1>;
                        interrupt-parent = <&gic>;
                        interrupts = <0 61 4>, <0 61 4>;
                        reg = <0x0 0xff0d0000 0x0 0x1000>;
-                       clock-names = "pclk", "hclk", "tx_clk";
+                       clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        #stream-id-cells = <1>;
                        interrupt-parent = <&gic>;
                        interrupts = <0 63 4>, <0 63 4>;
                        reg = <0x0 0xff0e0000 0x0 0x1000>;
-                       clock-names = "pclk", "hclk", "tx_clk";
+                       clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
                        #address-cells = <1>;
                        #size-cells = <0>;
                        #stream-id-cells = <1>;